A 4Gbps DPPM On-chip Serial Link Based on Pipelined Vernier-Tdc

Abstract

This paper presents a double-edge Pulse Position Modulation (DPPM) time-domain serial link for on-chip interconnect. The proposed design can achieve highspeed low-power interconnect with a lower operating frequency. The time-to-digital converter (TDC) based receiver is pipelined to achieve a throughput rate of as high as 4Gbps. The overall system is designed and simulated to achieve 4Gbps data rate with 171.2fJ/bit/mm energy dissipation for 10mm on-chip interconnect on 40nm SMIC CMOS process.