Impact of Process Variability on Threshold Voltage in JLAM-VSN-FET

Vertically Stacked Nanosheet FET (VSN-FET) is considered to be the most promising device to replace FinFET beyond the 3nm node. The VSN-FET can be implemented in either inversion mode (IM) or junctionless mode (JL). In order to reduce the impact of process variations on VSN-FET without sacrificing device characteristics, a new junctionless accumulation mode (JLAM) VSN-FET is proposed in this paper. By using TCAD with a statistical impedance field method (sIFM), the process variations of VSN-FET in IM, JL, and JLAM are compared in terms of RDF, WFV, and OTV. The results show that JLAM-VSN-FET has a simpler process compared to IM-VSN-FET, and better variation immunity compared to JL-VSN-FET. Further simulations of JLAM-VSN-FET indicate that the increase of work function difference in gate metal grains leads to the degradation of σVth. Besides, the application of thicker physical gate oxide with higher-κ is confirmed to alleviate σVth_WFV. As device scaling down, nanosheet height and gate oxide thickness scaling leads to the reduction of σVth_RDF, whereas channel length and width scaling results in the degradation of σVth_RDF, σVth_OTV, and σVth_WFV.