A Low Power, wide-band input buffer for 12bit 1GS/s ADC

Abstract

A wide-band input buffer has become the design challenge for the power efficiency of an ADC system. Most of the state-of-the-arts take a relatively costly design effort to alleviate the channel-length modulation of the SF. This paper presents a low power and high linearity push-pull input buffer with replica source followers(SFs) for 1GS/s 12bit high resolution and high speed ADC. The prototype input buffer is designed in 28nm CMOS process, achieving 82.3dB SFDR with 1pF load and 1.8V output swing, consuming only 9.17mW under 1.8V supply.