基于流水线游标tdc的4Gbps DPPM片上串行链路

2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT) Pub Date : 2020-11-03 DOI:10.1109/ICSICT49897.2020.9278344

Jinhao Li, Chongbing Qu, Fan Wu, Jianfei Jiang

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引用次数: 0

摘要

提出了一种用于片上互连的双边缘脉冲位置调制(DPPM)时域串行链路。该设计可以在较低的工作频率下实现高速低功耗互连。基于时间-数字转换器(TDC)的接收器是流水线的，以实现高达4Gbps的吞吐率。在40nm中芯国际CMOS工艺上实现10mm片上互连，实现4Gbps数据速率和171.2fJ/bit/mm能耗。

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A 4Gbps DPPM On-chip Serial Link Based on Pipelined Vernier-Tdc

This paper presents a double-edge Pulse Position Modulation (DPPM) time-domain serial link for on-chip interconnect. The proposed design can achieve highspeed low-power interconnect with a lower operating frequency. The time-to-digital converter (TDC) based receiver is pipelined to achieve a throughput rate of as high as 4Gbps. The overall system is designed and simulated to achieve 4Gbps data rate with 171.2fJ/bit/mm energy dissipation for 10mm on-chip interconnect on 40nm SMIC CMOS process.

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2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)

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