Design and Implementation of Cryptographic Instruction Set

Abstract

With the development of embedded devices, power consumption and area have gradually become the bottleneck restricting chip design. Chip designers are more concerned about how to achieve higher performance under limited area and power consumption. This paper analyzes the cryptographic operations of all types of cryptographic algorithms including grouping, sequence, hashing, and public key. Then we extracts fine-grained common logic, designs corresponding cryptographic arithmetic units, follows the RISC-V instruction set architecture, and designs cryptographic extended instruction sets. Ariane, a low-power general-purpose cryptographic processor, was selected for transformation, and a low-power, high-performance cryptographic processor core was designed. The logic synthesis is performed under the 55nm CMOS process, and the results show that we have exchanged for a higher cryptographic operation speed with an area overhead of 1162718.09 µm2 and a critical delay of 2.5 ns. And the experiments show that AES-128 takes about 290ns, and ECC in the 256-bit prime field takes about 0.224ms.