A 10-bit 60MHz-BW Continuous-Time Delta-Sigma ADC for wireless applications in 40nm CMOS

In this paper, a 10-bit 60MHz-BW continuous-time (CT) Delta-Sigma ADC is presented. A 3rd-order 3-bit ADC architecture with Cascaded Integrators Feed-Forward (CIFF) is adopted for the consideration of speed, performance, stability, power consumption and tolerance to non-idealities. The feedback digital signal is delayed by one clock period to absorb excess loop delay (ELD), and a zero-order feedback path is added to retain the noise transfer function. Both two-stage feedforward-compensated and single-stage OTAs are designed in the analog loop filter. The front-end feedback DAC is design with large area to ensure 10-bit intrinsic linearity. The ADC is designed and simulated in 40nm CMOS process with a sampling frequency of 1.92GHz. The simulations show that the ADC achieves 69.6dB SNR and 64.7dB SNDR for 60MHz BW, with a power consumption of 31.6mW, corresponding to a FoM of 188fJ/Step.