A Feedback Loop-based Timing Adaptive Corrected Circuit

Abstract

This paper introduces a kind of timing adaptive corrected circuit, which quantifies the phase between data generating clock and sampling clock, compares the current phase with the target phase that meets the timing requirement, adjusts the delay of one clock based on the comparison results, and changes the current phase, forms a negative feedback loop. This technique allows the sampling timing to be always met and also compensates for sampling timing changes caused by changes in the external environment, thus achieving data transfer and synchronization at high speed. In the post-simulation the inputs are two 5GHz clocks with 0° initial phase, after the loop is stabilized, the phase between the two output clocks is locked to 90° to meet the target phase.