{"title":"A Ka-Band High-Gain and Wideband mmW Down-Conversion Mixer for 5G Communication Applications","authors":"Rongsheng Bao, Shengyu Rao, C. Shi, Jinghong Chen, Guangsheng Chen, Runxi Zhang","doi":"10.1109/ICSICT49897.2020.9278246","DOIUrl":null,"url":null,"abstract":"This paper implements a high-gain and wideband CMOS mmW down-conversion mixer for 5G communication applications. A parallel inductor is exploited to eliminate the parasitic capacitance between the transconductance transistors and the switching transistors. The dynamic current injection (DCI) method based on the cross-coupled transistors is proposed to realize the negative resistance to cancel the loss resistance, which is introduced by the parallel inductor, and then the gain is improved while the noise is reduced. A resonating peak control (RPC) technology based on the passive transformer is utilized to improve bandwidth. The chip is designed using 40-nm CMOS process and the simulated peak conversion gain (CG) is 16.78 dB at 26 GHz. The 3 dB bandwidth is from 24 to 30 GHz. The minimum noise figure (NF) is 9.65 dB and the input P1dB is -11 dBm. The DC power consumption is 16 mW.","PeriodicalId":6727,"journal":{"name":"2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)","volume":"5 1","pages":"1-3"},"PeriodicalIF":0.0000,"publicationDate":"2020-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICSICT49897.2020.9278246","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
This paper implements a high-gain and wideband CMOS mmW down-conversion mixer for 5G communication applications. A parallel inductor is exploited to eliminate the parasitic capacitance between the transconductance transistors and the switching transistors. The dynamic current injection (DCI) method based on the cross-coupled transistors is proposed to realize the negative resistance to cancel the loss resistance, which is introduced by the parallel inductor, and then the gain is improved while the noise is reduced. A resonating peak control (RPC) technology based on the passive transformer is utilized to improve bandwidth. The chip is designed using 40-nm CMOS process and the simulated peak conversion gain (CG) is 16.78 dB at 26 GHz. The 3 dB bandwidth is from 24 to 30 GHz. The minimum noise figure (NF) is 9.65 dB and the input P1dB is -11 dBm. The DC power consumption is 16 mW.