3nm栅极全能纳米片场效应管的设计技术协同优化

2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT) Pub Date : 2020-11-03 DOI:10.1109/ICSICT49897.2020.9278197

Meng Wang, Yabin Sun, Xiaojin Li, Yanling Shi, ShaoJian Hu, Enming Shang, Shoumian Chen

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引用次数: 5

摘要

本文提出了一种改进的基于TCAD的栅极全能(GAA)纳米场效应管(NSFET) 3nm技术节点的设计技术协同优化(DTCO)方法。在传统的tco方法的基础上，只增加了一个过程来提取SPICE模型，从而节省了TCAD仿真的大量计算费用。与5nm技术节点相比，优化后的3nm技术节点的环形振荡器(RO)性能提高了30%，而功耗降低了56%。此外，还研究了器件级和电路级nsfet的双k间隔设计。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Design Technology Co-Optimization for 3 nm Gate-All-Around Nanosheet FETs

In this work, an improved TCAD based Design Technology Co-Optimization (DTCO) is proposed for gate-all-around (GAA) Nanosheet FET (NSFET) at 3 nm technology node. Based on conventional DTCO, only an additional procedure is introduced to extract the SPICE model, while the huge computational expense in the TCAD simulation is saved. Compared to the 5 nm technology node, the performance of ring oscillator (RO) in the optimized 3 nm technology node increases by 30%, while the power decreases by 56%. Besides, dual-k spacer design for NSFETs at the device and circuit levels are also investigated.

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来源期刊

2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)

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