Design of High-Performance Phase-Locked Loop Using Hybrid Dual-Path Loop Architecture: an Overview (Invited Paper)

Abstract

The performance requirements of phase-locked loops (PLL) for the emerging applications such 5G and IoT are continuously growing. Compared with the conventional single-path loop based PLL, including the charge pump based PLL, sub-sampling PLL and all-digital PLL, the hybrid dual-path loop based PLL architecture (HDL-PLL) can combine the advantages of all these three kinds of single-path loop based PLL to achieve better performances. This paper first gives an overview of the basics, advantages, and the recent research progress of HDL-PLL. Then, two design examples based on our recent research with their measurement results are introduced to show that the HDL-PLL architecture can effectively improve the PLL performances.