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Influence of the acceptor-type trap on the characteristic of the short-channel GaN MOS-HEMT 受体型陷阱对短沟道GaN MOS-HEMT特性的影响
2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT) Pub Date : 2020-11-03 DOI: 10.1109/ICSICT49897.2020.9278247
Yijun Shi, Z. Fu, Bin Yao, Si Chen, Yiqiang Chen, Bin Zhou, Yun Huang, Zhizhe Wang
{"title":"Influence of the acceptor-type trap on the characteristic of the short-channel GaN MOS-HEMT","authors":"Yijun Shi, Z. Fu, Bin Yao, Si Chen, Yiqiang Chen, Bin Zhou, Yun Huang, Zhizhe Wang","doi":"10.1109/ICSICT49897.2020.9278247","DOIUrl":"https://doi.org/10.1109/ICSICT49897.2020.9278247","url":null,"abstract":"In this work, the influences of the acceptor-type trap (located at GaN/insulator interface and GaN buffer layer) on the threshold voltage and 2-dimension electron gas (2DEG) density are analyzed for short-channel GaN MOS-HEMT. Particularly, the influence of the acceptor-type trap on short-channel effect in short-channel GaN MOS-HEMT is analyzed and modeled for the first time. The analyzed results have shown that the acceptor-type trap plays an important role on the threshold voltage, 2DEG density, and short-channel effect. The calculated results are well supported by the numerical simulation and experimental measurement, which verified the correctness and accuracy of the presented model to predict the dependence of threshold voltage, 2DEG density, and short-channel effect on acceptor-type trap.","PeriodicalId":6727,"journal":{"name":"2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)","volume":"97 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2020-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80650335","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
OTA-C Filter Based on the Low Noise and HD3 Transconductance for ECG Detection $sim$ 基于低噪声和HD3跨导的OTA-C滤波器在心电检测中的应用
2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT) Pub Date : 2020-11-03 DOI: 10.1109/ICSICT49897.2020.9278183
Bo Lin, Zhiqiang Gao, Hongjun Li, Jing Xu
{"title":"OTA-C Filter Based on the Low Noise and HD3 Transconductance for ECG Detection $sim$","authors":"Bo Lin, Zhiqiang Gao, Hongjun Li, Jing Xu","doi":"10.1109/ICSICT49897.2020.9278183","DOIUrl":"https://doi.org/10.1109/ICSICT49897.2020.9278183","url":null,"abstract":"This paper presents a 5-order low-pass filter (LPF) structure based on the operational transconductance amplifier(OTA) structure that is designed with low noise and HD3. To ensure that the filter has a lower power dissipation, noise, and third harmonic distortion(HD3), the OTA operates in weak inversion region and uses technology including current division, current cancellation, source degeneration. The LPF is simulated by the 0.18 µm CMOS process, and the results show that the LPF locates within 250Hz and consumes 65.49 µW, the ripple is less than 0.2dB, and the HD3 is less than -70.21dB (@50mV). The maximum input reference noise (IRN) is $71.86 mu V/sqrt{Hz}$ The proposed LPF is suitable for Electrocardiograph (ECG) signal detection analog front circuit.","PeriodicalId":6727,"journal":{"name":"2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)","volume":"67 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83125172","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A computationally efficient nonlinear dynamic model for cMUT based on COMSOL and MATLAB/Simulink 基于COMSOL和MATLAB/Simulink的cMUT非线性动力学模型
2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT) Pub Date : 2020-11-03 DOI: 10.1109/ICSICT49897.2020.9278134
Yan Wang, Leming He, Ziwei Li, Weijiang Xu, Junyan Ren
{"title":"A computationally efficient nonlinear dynamic model for cMUT based on COMSOL and MATLAB/Simulink","authors":"Yan Wang, Leming He, Ziwei Li, Weijiang Xu, Junyan Ren","doi":"10.1109/ICSICT49897.2020.9278134","DOIUrl":"https://doi.org/10.1109/ICSICT49897.2020.9278134","url":null,"abstract":"Using the plate capacitance model, capacitive micromachined ultrasound transducers (cMUT) cells can be simulated. We present a hybrid model that predicts the dynamic behavior of a cMUT cell with uneven membrane and partial coverage electrode. COMSOL Multiphysics was used to calculate the stationary behavior of the cMUT cell. A MATLAB/Simulink model is developed based on the stationary simulation results. As a main advantage, it supplies a computationally efficient way to simulate the dynamic behavior of cMUT. The hybrid model includes the nonlinear characteristic of the dynamic system, like the resonant frequency shift. To verify this model, the deformation under various conditions is simulated. The results show the ability to capture the nonlinear CMUT behavior accurately.","PeriodicalId":6727,"journal":{"name":"2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)","volume":"36 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77829435","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A Wafer Map Defect Pattern Classification Model Based on Deep Convolutional Neural Network 基于深度卷积神经网络的晶圆图缺陷模式分类模型
2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT) Pub Date : 2020-11-03 DOI: 10.1109/ICSICT49897.2020.9278021
Dong-Yang Du, Zheng Shi
{"title":"A Wafer Map Defect Pattern Classification Model Based on Deep Convolutional Neural Network","authors":"Dong-Yang Du, Zheng Shi","doi":"10.1109/ICSICT49897.2020.9278021","DOIUrl":"https://doi.org/10.1109/ICSICT49897.2020.9278021","url":null,"abstract":"Many process problems in the Integrated Circuit (IC) manufacturing can lead to the formation of some specific defect patterns on the wafer map. The process problems can be located by classifying wafer map defect patterns (WMDPs). This paper proposed an easy-to-train deep convolutional neural network (DCNN) classification model with a high recognition rate for WMDP by using the global average pooling and parameter reducing method. This model achieved a 94.68% average recognition rate on a benchmark dataset, which is much better than the model based on artificially-designed-features and neural networks with lots of parameters","PeriodicalId":6727,"journal":{"name":"2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)","volume":"21 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80931198","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Charge Plasma-Based Junctionless FinFET for The Immune of Fin Sidewall Angle Variation 基于电荷等离子体的无结FinFET对翅片侧壁角变化的免疫
2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT) Pub Date : 2020-11-03 DOI: 10.1109/icsict49897.2020.9278301
Baoliang Liu, Hung-Chih Chin, H. Lou, Kuan‐Chang Chang, Xinnan Lin
{"title":"Charge Plasma-Based Junctionless FinFET for The Immune of Fin Sidewall Angle Variation","authors":"Baoliang Liu, Hung-Chih Chin, H. Lou, Kuan‐Chang Chang, Xinnan Lin","doi":"10.1109/icsict49897.2020.9278301","DOIUrl":"https://doi.org/10.1109/icsict49897.2020.9278301","url":null,"abstract":"In this paper, the charge-plasma concept is applied to suppress the electrical characteristics variation induced by the variation of Fin sidewall angle (θ) in the conventional junctionless FinFET (CON-JLFinFET). The electrical characteristics of the conventional JLFinFET and charge plasma-based JLFinFET (CP-JLFinFET) with a trapezoidal cross section were investigated by three-dimensional numerical simulations. It is found that the CP-JLFinFET is insensitive to the variation of θ, which illustrates that the CP-JLFinFET may be a potential candidate for the further scaling of junctionless FinFET.","PeriodicalId":6727,"journal":{"name":"2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)","volume":"30 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83342245","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
MF-Conv: A Novel Convolutional Approach Using Bit-Resolution-based Weight Decomposition to Eliminate Multiplications for CNN Acceleration MF-Conv:一种新颖的卷积方法，使用基于位分辨率的权重分解来消除CNN加速的乘法
2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT) Pub Date : 2020-11-03 DOI: 10.1109/ICSICT49897.2020.9278019
Chen Yang, Xianxian Lv, Bowen Li, Shiquan Fan, K. Mei, Li Geng
{"title":"MF-Conv: A Novel Convolutional Approach Using Bit-Resolution-based Weight Decomposition to Eliminate Multiplications for CNN Acceleration","authors":"Chen Yang, Xianxian Lv, Bowen Li, Shiquan Fan, K. Mei, Li Geng","doi":"10.1109/ICSICT49897.2020.9278019","DOIUrl":"https://doi.org/10.1109/ICSICT49897.2020.9278019","url":null,"abstract":"Convolution computation is the core of convolutional neural network (CNN). With the increasing demand for the accuracy of CNN applications, the amount of convolution computation has been increasing rapidly. Now, most FPGA-based CNN accelerators tend to utilize multiply-and-accumulate (MAC) arrays in convolution operations, whose DSP amount determines the computational roof. To elevate the roof, this paper proposed a Multiplication-Free Convolution (MF-Conv) scheme for convolution layers. MF-Conv utilizes a bit-resolution-based weight decomposition method to transform multiplications into additions. Hence, we can completely eliminate multiple operation in convolution computation, as a result, avoiding the usage of DSP. Experimental results showed that the implementation of MF-Conv on Xilinx XC7Z100 platform can run at a clock frequency of 279MHz. Moreover, Compared to ABM-SpConv, proposed MF-Conv improve the performance of 3x3 kernel by 9x. MF-Conv also has a much smaller hardware overhead compared with ABM-SpConv.","PeriodicalId":6727,"journal":{"name":"2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)","volume":"5 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89286218","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Measurements of Self-Loop Functions in High-Order Passive and Active Low-Pass Filters 高阶无源和有源低通滤波器中自环函数的测量
2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT) Pub Date : 2020-11-03 DOI: 10.1109/ICSICT49897.2020.9278402
MinhTri Tran, A. Kuwana, Haruo Kobayashi
{"title":"Measurements of Self-Loop Functions in High-Order Passive and Active Low-Pass Filters","authors":"MinhTri Tran, A. Kuwana, Haruo Kobayashi","doi":"10.1109/ICSICT49897.2020.9278402","DOIUrl":"https://doi.org/10.1109/ICSICT49897.2020.9278402","url":null,"abstract":"This paper discusses the practical measurements of self-loop functions in second-order low-pass filters based on an alternating current conservation technique. From the view point of transfer function of a network, the measurement of phase margin at unity gain of the self-loop function can verify the operating region of a high-order transfer function which can be over-damping, or critically damping, or under-damping. The overshoot and undershoot voltages will occur in both passive and active linear systems when they work on the under-damping region. Therefore, measurements of self-loop function have been useful not only in passive networks but also in feedback systems.","PeriodicalId":6727,"journal":{"name":"2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)","volume":"10 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2020-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86581508","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Scheme of Hardware Trojans Isolation for Switch Chip Buffer 开关芯片缓冲器硬件木马隔离方案
2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT) Pub Date : 2020-11-03 DOI: 10.1109/ICSICT49897.2020.9278354
Xiang-Yu Li, Li-ji Wu, Xiang-min Zhang
{"title":"Scheme of Hardware Trojans Isolation for Switch Chip Buffer","authors":"Xiang-Yu Li, Li-ji Wu, Xiang-min Zhang","doi":"10.1109/ICSICT49897.2020.9278354","DOIUrl":"https://doi.org/10.1109/ICSICT49897.2020.9278354","url":null,"abstract":"The destruction of cooperation technology can interdict the communication between hardware Trojans and adversaries. This paper discusses the design principles of the scrambling scheme and proposed a PUFFIN based scheme and its hardware structure for a switch chip's data buffer. Test shows that the proposed scheme is destructive for both static and sequential trigger conditions with about 288.6 k gates overhead for every bit of the data bus and 7.5 ns additional latency.","PeriodicalId":6727,"journal":{"name":"2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)","volume":"98 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88311024","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Low-Complexity Timing Mismatch Calibration Method for Four-Channel Time-Interleaved ADCs Based on Cross Correlation 一种基于互相关的四通道时间交错adc低复杂度时序失配校准方法
2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT) Pub Date : 2020-11-03 DOI: 10.1109/ICSICT49897.2020.9278304
Sujuan Liu, Lin Zhao, Zhiyue Deng, Zhonghou Zhang
{"title":"A Low-Complexity Timing Mismatch Calibration Method for Four-Channel Time-Interleaved ADCs Based on Cross Correlation","authors":"Sujuan Liu, Lin Zhao, Zhiyue Deng, Zhonghou Zhang","doi":"10.1109/ICSICT49897.2020.9278304","DOIUrl":"https://doi.org/10.1109/ICSICT49897.2020.9278304","url":null,"abstract":"This paper proposes an all-digital blind calibration architecture for timing mismatch of a four-channel time-interleaved analog-to-digital converter (TIADC). By calculating the cross-correlation between the signal and its derivative, the linear combination of the timing mismatch can be estimated. Then the mismatch-induced error signal is calibrated by the cascade of the differentiator and multiplier. Simulation results of a 12-bit 1GS/s four-channel TIADC behavioral model verify the effectiveness of our method. The Spurious Free Dynamic Range (SFDR) is enhanced from 34.49dB to 76.21dB. Compared with other methods, this method requires only one filter, which has the advantages of low hardware cost for implementation.","PeriodicalId":6727,"journal":{"name":"2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)","volume":"2 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83609790","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An Improved Design of Hybrid Integrated Voltage Regulator Based on DLDO and SCVR 基于DLDO和SCVR的混合集成稳压器改进设计
2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT) Pub Date : 2020-11-03 DOI: 10.1109/ICSICT49897.2020.9278025
Yuanchen Qu, Pingqiang Zhou
{"title":"An Improved Design of Hybrid Integrated Voltage Regulator Based on DLDO and SCVR","authors":"Yuanchen Qu, Pingqiang Zhou","doi":"10.1109/ICSICT49897.2020.9278025","DOIUrl":"https://doi.org/10.1109/ICSICT49897.2020.9278025","url":null,"abstract":"This paper improves a hybrid fully integrated voltage regulator based on digital low-dropout (DLDO) and switched-capacitor voltage regulator (SCVR) by improving the controllers of DLDO and SCVR, respectively. The controller is improved to achieve tunable voltage droop response and larger power efficiency during DLDO mode. Adaptive width scheme is added to increase the power efficiency during SCVR mode. As a result, tunable voltage droop response and 3% peak efficiency rising is achieved during DLDO mode. Using adaptive width scheme, the overall power efficiency is increased by 3% on average and the peak efficiency is increased by 6% during SCVR mode.","PeriodicalId":6727,"journal":{"name":"2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)","volume":"1 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83651836","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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