Scheme of Hardware Trojans Isolation for Switch Chip Buffer

Abstract

The destruction of cooperation technology can interdict the communication between hardware Trojans and adversaries. This paper discusses the design principles of the scrambling scheme and proposed a PUFFIN based scheme and its hardware structure for a switch chip's data buffer. Test shows that the proposed scheme is destructive for both static and sequential trigger conditions with about 288.6 k gates overhead for every bit of the data bus and 7.5 ns additional latency.