{"title":"开关芯片缓冲器硬件木马隔离方案","authors":"Xiang-Yu Li, Li-ji Wu, Xiang-min Zhang","doi":"10.1109/ICSICT49897.2020.9278354","DOIUrl":null,"url":null,"abstract":"The destruction of cooperation technology can interdict the communication between hardware Trojans and adversaries. This paper discusses the design principles of the scrambling scheme and proposed a PUFFIN based scheme and its hardware structure for a switch chip's data buffer. Test shows that the proposed scheme is destructive for both static and sequential trigger conditions with about 288.6 k gates overhead for every bit of the data bus and 7.5 ns additional latency.","PeriodicalId":6727,"journal":{"name":"2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)","volume":"98 1","pages":"1-3"},"PeriodicalIF":0.0000,"publicationDate":"2020-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Scheme of Hardware Trojans Isolation for Switch Chip Buffer\",\"authors\":\"Xiang-Yu Li, Li-ji Wu, Xiang-min Zhang\",\"doi\":\"10.1109/ICSICT49897.2020.9278354\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The destruction of cooperation technology can interdict the communication between hardware Trojans and adversaries. This paper discusses the design principles of the scrambling scheme and proposed a PUFFIN based scheme and its hardware structure for a switch chip's data buffer. Test shows that the proposed scheme is destructive for both static and sequential trigger conditions with about 288.6 k gates overhead for every bit of the data bus and 7.5 ns additional latency.\",\"PeriodicalId\":6727,\"journal\":{\"name\":\"2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)\",\"volume\":\"98 1\",\"pages\":\"1-3\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2020-11-03\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICSICT49897.2020.9278354\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICSICT49897.2020.9278354","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Scheme of Hardware Trojans Isolation for Switch Chip Buffer
The destruction of cooperation technology can interdict the communication between hardware Trojans and adversaries. This paper discusses the design principles of the scrambling scheme and proposed a PUFFIN based scheme and its hardware structure for a switch chip's data buffer. Test shows that the proposed scheme is destructive for both static and sequential trigger conditions with about 288.6 k gates overhead for every bit of the data bus and 7.5 ns additional latency.