MF-Conv: A Novel Convolutional Approach Using Bit-Resolution-based Weight Decomposition to Eliminate Multiplications for CNN Acceleration

Abstract

Convolution computation is the core of convolutional neural network (CNN). With the increasing demand for the accuracy of CNN applications, the amount of convolution computation has been increasing rapidly. Now, most FPGA-based CNN accelerators tend to utilize multiply-and-accumulate (MAC) arrays in convolution operations, whose DSP amount determines the computational roof. To elevate the roof, this paper proposed a Multiplication-Free Convolution (MF-Conv) scheme for convolution layers. MF-Conv utilizes a bit-resolution-based weight decomposition method to transform multiplications into additions. Hence, we can completely eliminate multiple operation in convolution computation, as a result, avoiding the usage of DSP. Experimental results showed that the implementation of MF-Conv on Xilinx XC7Z100 platform can run at a clock frequency of 279MHz. Moreover, Compared to ABM-SpConv, proposed MF-Conv improve the performance of 3x3 kernel by 9x. MF-Conv also has a much smaller hardware overhead compared with ABM-SpConv.