A Wafer Map Defect Pattern Classification Model Based on Deep Convolutional Neural Network

Abstract

Many process problems in the Integrated Circuit (IC) manufacturing can lead to the formation of some specific defect patterns on the wafer map. The process problems can be located by classifying wafer map defect patterns (WMDPs). This paper proposed an easy-to-train deep convolutional neural network (DCNN) classification model with a high recognition rate for WMDP by using the global average pooling and parameter reducing method. This model achieved a 94.68% average recognition rate on a benchmark dataset, which is much better than the model based on artificially-designed-features and neural networks with lots of parameters