Influence of Gate-Drain Underlap Length on Germanium Gate-All-Around Tunneling Field-Effect-Transistors

In this paper, the influence of gate-drain underlap length (Lun) of germanium gate-all-around tunneling field-effect-transistors (Ge-GAA- TFETs) is investigated. Based on the TCAD simulation, the I- V and C- V characteristics of GAA- TFETs with different Lunare obtained, and the results show that ambipolar current (Iamp) and Cgd considerably decrease with the increase in Lun, whereas $C$gs is independent on Lun. Moreover, the method of device circuit co-design is used to evaluate the impact of Lunon logic performance including propagation delay (tpd) and energy-delay-product (EDP). Compared with no underlap structure, the tpd reduction of 40% @VDD= 0.2 V is achieved in both inverter and two-input NAND with 10 nm underlap structure. The EDP reduction up to 67% and 66% at VDD= 0.2 V are obtained in the inverter and two-input NAND, respectively. Therefore, we can conclude that the longer Lunbenefits in mitigating both tpd and EDP.