Design for Saddle-Fin Device Performance Boosting with Dual Work Function Gate Formation Word Line

Abstract

In the past decades, dynamic random access memory(DRAM) has continued to scaling down to obtain higher data storage ability. As for the access transistor, much effort has been dedicated to reduce leakage and obtain sufficient drivability to improve retention time and access speed. However, it become more and more difficult when the technology nodes beyond 20nm. In our work, the saddle fin access transistor with a dual work function word line structure has been investigated with TCAD simulation. An improved performance with suppressed GIDL leakage and enhanced drive current have been obtained. We have analyzed the word line engineering effects on the electric field and band to band tunneling.