Influence of Gate-Drain Underlap Length on Germanium Gate-All-Around Tunneling Field-Effect-Transistors

2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT) Pub Date : 2020-11-03 DOI:10.1109/ICSICT49897.2020.9278269

Kai-Xiao Wei, Xiaojin Li, Yabin Sun, Yanling Shi

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Abstract

In this paper, the influence of gate-drain underlap length (Lun) of germanium gate-all-around tunneling field-effect-transistors (Ge-GAA- TFETs) is investigated. Based on the TCAD simulation, the I- V and C- V characteristics of GAA- TFETs with different Lunare obtained, and the results show that ambipolar current (Iamp) and Cgd considerably decrease with the increase in Lun, whereas $C$gs is independent on Lun. Moreover, the method of device circuit co-design is used to evaluate the impact of Lunon logic performance including propagation delay (tpd) and energy-delay-product (EDP). Compared with no underlap structure, the tpd reduction of 40% @VDD= 0.2 V is achieved in both inverter and two-input NAND with 10 nm underlap structure. The EDP reduction up to 67% and 66% at VDD= 0.2 V are obtained in the inverter and two-input NAND, respectively. Therefore, we can conclude that the longer Lunbenefits in mitigating both tpd and EDP.

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栅极-漏极搭接长度对锗栅极-全隧道场效应晶体管的影响

本文研究了锗栅极-全隧道场效应晶体管(Ge-GAA- tfet)栅极-漏极欠接长度(Lun)的影响。基于TCAD仿真，得到了不同月相下GAA- tfet的I- V和C- V特性，结果表明，双极电流(Iamp)和Cgd随月相的增加而显著减小，而$C$gs与月相无关。此外，采用器件电路协同设计的方法评估了Lunon逻辑性能的影响，包括传播延迟(tpd)和能量延迟积(EDP)。与无下迭结构相比，采用10 nm下迭结构的逆变器和双输入NAND的tpd均降低了40% @VDD= 0.2 V。在VDD= 0.2 V时，逆变器和双输入NAND器件的EDP分别降低了67%和66%。因此，我们可以得出结论，较长的lund有利于减轻tpd和EDP。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)

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