{"title":"Influence of Gate-Drain Underlap Length on Germanium Gate-All-Around Tunneling Field-Effect-Transistors","authors":"Kai-Xiao Wei, Xiaojin Li, Yabin Sun, Yanling Shi","doi":"10.1109/ICSICT49897.2020.9278269","DOIUrl":null,"url":null,"abstract":"In this paper, the influence of gate-drain underlap length (L<inf>un</inf>) of germanium gate-all-around tunneling field-effect-transistors (Ge-GAA- TFETs) is investigated. Based on the TCAD simulation, the I- V and C- V characteristics of GAA- TFETs with different L<inf>un</inf>are obtained, and the results show that ambipolar current (Iamp) and Cgd considerably decrease with the increase in L<inf>un</inf>, whereas <tex>$C$</tex><inf>gs</inf> is independent on L<inf>un</inf>. Moreover, the method of device circuit co-design is used to evaluate the impact of L<inf>un</inf>on logic performance including propagation delay (tpd) and energy-delay-product (EDP). Compared with no underlap structure, the tpd reduction of 40% @V<inf>DD</inf>= 0.2 V is achieved in both inverter and two-input NAND with 10 nm underlap structure. The EDP reduction up to 67% and 66% at V<inf>DD</inf>= 0.2 V are obtained in the inverter and two-input NAND, respectively. Therefore, we can conclude that the longer L<inf>un</inf>benefits in mitigating both tpd and EDP.","PeriodicalId":6727,"journal":{"name":"2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)","volume":"39 1","pages":"1-3"},"PeriodicalIF":0.0000,"publicationDate":"2020-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICSICT49897.2020.9278269","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
In this paper, the influence of gate-drain underlap length (Lun) of germanium gate-all-around tunneling field-effect-transistors (Ge-GAA- TFETs) is investigated. Based on the TCAD simulation, the I- V and C- V characteristics of GAA- TFETs with different Lunare obtained, and the results show that ambipolar current (Iamp) and Cgd considerably decrease with the increase in Lun, whereas $C$gs is independent on Lun. Moreover, the method of device circuit co-design is used to evaluate the impact of Lunon logic performance including propagation delay (tpd) and energy-delay-product (EDP). Compared with no underlap structure, the tpd reduction of 40% @VDD= 0.2 V is achieved in both inverter and two-input NAND with 10 nm underlap structure. The EDP reduction up to 67% and 66% at VDD= 0.2 V are obtained in the inverter and two-input NAND, respectively. Therefore, we can conclude that the longer Lunbenefits in mitigating both tpd and EDP.