采用超低功耗读取方案的28nm 4Mb 1T-1MTJ STT-MRAM电路

2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT) Pub Date : 2020-11-03 DOI:10.1109/ICSICT49897.2020.9278155

S. Zheng, J. Bi, K. Xi, Bo Li

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引用次数: 0

摘要

设计了基于28nm CMOS工艺的4Mb 1T-1MTJ STT-MRAM。为了提高读取性能，提出了一种超低功耗的传感放大器结构。读功耗低至1pJ/bit。整个STT-MRAM芯片的仿真结果显示了良好的性能。

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28nm 4Mb 1T-1MTJ STT-MRAM Circuits with Ultra-low Power Read Scheme

4Mb 1T-1MTJ STT-MRAM based on 28nm CMOS process has been designed. To improve reading performance, a novel sense amplifier structure, achieving ultra-low power consumption, has been proposed. The read power consumption is as low as 1pJ/bit. The simulation results of the whole STT-MRAM chip demonstrate good performance.

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来源期刊

2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)

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