{"title":"一种带PVT和RC延时抵消误差的NTV DFF时序变化皮秒分辨率传感器","authors":"Wen Wang, Shuming Cui, Yinyin Lin","doi":"10.1109/ICSICT49897.2020.9278326","DOIUrl":null,"url":null,"abstract":"A novel circuit for testing sequential element setup time and hold time variation at near threshold voltage (NTV) is proposed and verified at 28nm HKMG node. A structure of two-path with configurable delay differentiation enables to cancel testing errors introduced by PVT variations and RC delay along the testing path. Pico-seconds of resolution is achieved. Simulation of setup/hold time is implemented with variable voltage, process corner, temperature and data edge. The results indicate that the scenario of data rising edge has a larger setup&hold time than the scenario of data falling edge at NTV.","PeriodicalId":6727,"journal":{"name":"2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)","volume":"15 1","pages":"1-3"},"PeriodicalIF":0.0000,"publicationDate":"2020-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A Pico-second Resolution Sensor of NTV DFF Timing Variation with Cancelling Errors from PVT and RC Delay along Testing Path\",\"authors\":\"Wen Wang, Shuming Cui, Yinyin Lin\",\"doi\":\"10.1109/ICSICT49897.2020.9278326\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A novel circuit for testing sequential element setup time and hold time variation at near threshold voltage (NTV) is proposed and verified at 28nm HKMG node. A structure of two-path with configurable delay differentiation enables to cancel testing errors introduced by PVT variations and RC delay along the testing path. Pico-seconds of resolution is achieved. Simulation of setup/hold time is implemented with variable voltage, process corner, temperature and data edge. The results indicate that the scenario of data rising edge has a larger setup&hold time than the scenario of data falling edge at NTV.\",\"PeriodicalId\":6727,\"journal\":{\"name\":\"2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)\",\"volume\":\"15 1\",\"pages\":\"1-3\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2020-11-03\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICSICT49897.2020.9278326\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICSICT49897.2020.9278326","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A Pico-second Resolution Sensor of NTV DFF Timing Variation with Cancelling Errors from PVT and RC Delay along Testing Path
A novel circuit for testing sequential element setup time and hold time variation at near threshold voltage (NTV) is proposed and verified at 28nm HKMG node. A structure of two-path with configurable delay differentiation enables to cancel testing errors introduced by PVT variations and RC delay along the testing path. Pico-seconds of resolution is achieved. Simulation of setup/hold time is implemented with variable voltage, process corner, temperature and data edge. The results indicate that the scenario of data rising edge has a larger setup&hold time than the scenario of data falling edge at NTV.