{"title":"Vertical scale-down of Cu/low-k interconnect development for BEOL reliability improvement of 12nm DRAM","authors":"J.H. Lee, B.W. Woo, Y.M. Lee, N.H. Lee, Y.Y. Lee, Y.S. Lee, S.B. Ko, S. Pae","doi":"10.1016/j.microrel.2025.115650","DOIUrl":"10.1016/j.microrel.2025.115650","url":null,"abstract":"<div><div>The effect of vertical scale-down of Cu interconnects on power consumption efficiency and back-end of the line (BEOL) reliability was investigated in 12nm DDR5 DRAM with four metal layers. The hydrostatic stress gradient, which drives stress migration (SM) failure was calculated using the finite element method, and it decreased in the scaled interconnect, thus leading to an improvement in the SM reliability. The time-dependent dielectric breakdown (TDDB) lifetime was also enhanced by the decrease in electric field between scaled Cu interconnects, which was demonstrated by both of the simulation and measurement. Although scaled interconnect could deteriorate the EM lifetime due to the increase in grain boundary, controlling the barrier metal thickness and utilizing advanced capping layer have compensated for the electro-migration (EM) deterioration. As a result, 12nm DDR5 DRAM meets 125°C BEOL reliability criteria while implementing low power through vertical scale-down of Cu interconnect.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"168 ","pages":"Article 115650"},"PeriodicalIF":1.6,"publicationDate":"2025-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143552901","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Cioni , G. Giorgino , A. Chini , N. Zagni , G. Cappellini , S. Principato , C. Miccoli , T. Wakrim , M.E. Castagna , A. Constant , F. Iucolano
{"title":"Effect of 2DEG density and Drain/Source Field Plate design on dynamic-RON of 650 V AlGaN/GaN HEMTs","authors":"M. Cioni , G. Giorgino , A. Chini , N. Zagni , G. Cappellini , S. Principato , C. Miccoli , T. Wakrim , M.E. Castagna , A. Constant , F. Iucolano","doi":"10.1016/j.microrel.2025.115666","DOIUrl":"10.1016/j.microrel.2025.115666","url":null,"abstract":"<div><div>The effect of 2DEG density and Drain/Source Field Plate design on dynamic-R<sub>ON</sub> of 650 V p-GaN gate AlGaN/GaN HEMTs is investigated in this work. Devices presenting three different AlGaN barrier and p-GaN layer design have been tested by means of Capacitance-Voltage measurements, Static V<sub>DS</sub> stress and Pulsed I-V characterization. C<img>V measurements allowed the extraction of 2DEG density, while Static V<sub>DS</sub> stress and Pulsed I-V put in evidence the partial recovery of the dynamic-R<sub>ON</sub> at high V<sub>DS,stress</sub>, potentially explained by a field-driven hole generation mechanism that partially compensates negatively ionized Carbon acceptors in the GaN Buffer. This hypothesis is in line with the trends observed for different 2DEG density and different drain field-plate designs, suggesting that a higher electric field under the drain terminal can significantly reduce R<sub>ON</sub>-degradation at high voltages, due to an easier holes generation. Furthermore, Pulsed I-V tests under resistive load switching mode have been addressed, highlighting the impact of the distance between source field plate and drain field plate on the dynamic-R<sub>ON</sub> degradation in conventional switch mode operations.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"168 ","pages":"Article 115666"},"PeriodicalIF":1.6,"publicationDate":"2025-03-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143552894","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Sorption getter characterization under wafer-level packaging (WLP) conditions","authors":"H. Duchemin, D. Bouchu","doi":"10.1016/j.microrel.2025.115677","DOIUrl":"10.1016/j.microrel.2025.115677","url":null,"abstract":"<div><div>Combination of Wafer Level Packaging (WLP) process with Non-Evaporated Getter (NEG) integration ensures the high-level vacuum hermetic packaging required for resonator based micro-electro-mechanical systems (MEMS) such as accelerometers or gyroscopes. In this article, we report a new characterization method to measure the NEG sorption efficiency under the replicated WLP process conditions, so as to ensure that the integration of NEG is well adapted to the overall MEMS fabrication process. We integrated this characterization protocol as a step in the MEMS process flow in order to ensure that the sealed getter remain fully functional through the WLP. Our approach is validated on hermetic packaged resonators, demonstrating an 80-fold quality factor (Q-factor) increase through NEG integration.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"168 ","pages":"Article 115677"},"PeriodicalIF":1.6,"publicationDate":"2025-03-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143552899","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A screening test of GaN-HEMTs for improvement of breakdown voltage uniformity","authors":"Wataru Saito, Shin-ichi Nishizawa","doi":"10.1016/j.microrel.2025.115643","DOIUrl":"10.1016/j.microrel.2025.115643","url":null,"abstract":"<div><div>As a screening test recipe, burst unclamped inductive switching (UIS) test is proposed to improve breakdown voltage uniformity. One of the critical disadvantages of GaN-HEMTs is its lack of the UIS withstanding capability, because there is no removal structure of holes, which generated by the avalanche breakdown. Hence, at the screening in the mass-production, measurement of the avalanche breakdown voltage cannot be employed to reject low breakdown voltage devices due to catastrophic failure, and conventional static drain leakage current measurements are insufficient. This paper reports a screening test of GaN-HEMTs by repetitive overvoltage stress using burst UIS test. The experimental results show the repetitive overvoltage stress was needed to reject outliers with low breakdown voltage and optimum test current avoided to generate new outliers.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"168 ","pages":"Article 115643"},"PeriodicalIF":1.6,"publicationDate":"2025-03-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143552898","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Bernardoni, R. Illing, M. Tripolt, C. Djelassi-Tscheck
{"title":"SMART protection design of automotive power distribution systems with temperature-based electronic fuses: Mathematical background, design guidelines and drawbacks of energy-based methods","authors":"M. Bernardoni, R. Illing, M. Tripolt, C. Djelassi-Tscheck","doi":"10.1016/j.microrel.2025.115635","DOIUrl":"10.1016/j.microrel.2025.115635","url":null,"abstract":"<div><div>This work presents an overview on the power distribution design requirements in automotive power distribution systems, with focus on wire harness protections. While standard melting fuses are still widely used in automotive power distribution systems, the complexity of the future automotive platforms can be enabled only by replacing melting fuses with electronic protections. This paper will analyze the typical design requirements in terms of wire protection, which electronic protections concepts are available and how a safe wire protection can be ensured. Moreover, we introduce a correct mathematical transformation that describes the effect of a given load current onto the considered thermal system (wire or eFuse), allowing the correct representation of load, eFuse, and wire, in the isothermal domain.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"168 ","pages":"Article 115635"},"PeriodicalIF":1.6,"publicationDate":"2025-03-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143552900","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Selective hardening of RISCV soft-processors for space applications","authors":"G. Cora, C. De Sio, S. Azimi, L. Sterpone","doi":"10.1016/j.microrel.2025.115667","DOIUrl":"10.1016/j.microrel.2025.115667","url":null,"abstract":"<div><div>RISC-V soft processors are becoming popular in various fields, including safety-critical ones, thanks to their open-source nature and flexibility. Despite the rapid progress in the reliability analysis of these devices, all the mitigation techniques are usually adopted to the whole soft-processor architecture.</div><div>In this study, we aim to identify the internal components of the RISC-V architecture that are particularly prone to errors, and accordingly investigate how the reliability of the design is affected when mitigation strategies, such as Triple Modular Redundancy (TMR), are applied selectively just to them.</div><div>The proposed approach has been applied to RISC-V architecture, NEORV32 which is implemented on Zynq 7020 SoC on a PYNQ-Z2 board. While more vulnerable modules of NEORV32 were identified through accurate reliability analysis, implementing selective TMR in these modules shows achieving satisfactory reliability levels while reducing the overall space requirements compared to a complete TMR design.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"167 ","pages":"Article 115667"},"PeriodicalIF":1.6,"publicationDate":"2025-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143534754","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
W.M. Liu , C. Chen , K.W. Xiao , Y. Yu , W. Zheng , M.T. Feng , G.F. Zhai
{"title":"Reliability prediction of multi-level power supply system based on Failure Precursor Parameters","authors":"W.M. Liu , C. Chen , K.W. Xiao , Y. Yu , W. Zheng , M.T. Feng , G.F. Zhai","doi":"10.1016/j.microrel.2025.115656","DOIUrl":"10.1016/j.microrel.2025.115656","url":null,"abstract":"<div><div>Complex electronic systems exhibit multi-level characteristics, making it challenging to simulate the system performance states accurately using existing reliability modeling methods. This paper proposes a multi-level reliability prediction model that extracts Failure Precursor Parameters (FPPs) as model inputs. First, a circuit-level multi-stress simulation model is constructed. Second, the degradation and failure information is input, and system FPPs are identified through sensitivity and correlation analysis. Finally, a dynamic system model is constructed to calculate the reliability of the system's comprehensive evaluation, with FPPs as inputs. A case study on a specific power supply system demonstrates the model's improved ability to simulate the system's operational state while maintaining prediction accuracy. Additionally, the paper provides a method combining the physics of failure models and system-level reliability prediction, and various research methods are compared.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"167 ","pages":"Article 115656"},"PeriodicalIF":1.6,"publicationDate":"2025-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143534753","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Bang-Ren Chen , Cheng Sung , Yu-Sheng Hsiao , Wei-Chen Yu , Wei-Cheng Lin , Surya Elangovan , Yi-Kai Hsiao , Hao-Chung Kuo , Chang-Ching Tu , Tian-Li Wu
{"title":"Driving waveform modification for investigating trade-off between switching loss and gate overshoot in SiC MOSFETs","authors":"Bang-Ren Chen , Cheng Sung , Yu-Sheng Hsiao , Wei-Chen Yu , Wei-Cheng Lin , Surya Elangovan , Yi-Kai Hsiao , Hao-Chung Kuo , Chang-Ching Tu , Tian-Li Wu","doi":"10.1016/j.microrel.2025.115653","DOIUrl":"10.1016/j.microrel.2025.115653","url":null,"abstract":"<div><div>SiC MOSFETs are crucial for efficient power conversion in electric vehicles, especially in the traction inverters operating on 800-V battery architectures. Their unipolar nature offers significantly lower switching losses compared to bipolar Si IGBTs. However, achieving high efficiency without compromising reliability remains a challenge. This study investigates the impact of driving waveforms on the SiC MOSFET switching loss and overshoot. Unlike conventional gate drivers, our approach involves a closed-loop amplifier combined with a push-pull circuit, enabling controllable gate driving waveforms through strategically placing a low-pass filter before the amplifier, so called the pre-RC method. Compared to the conventional method of placing R<sub>G</sub> in front of the gate, the pre-RC method shows notable decrease in turn-on switching loss for the t<sub>rising</sub> shorter than about 0.4 μs. The lower switching loss can be attributed to the larger |dV<sub>GS</sub>/dt|at around the V<sub>th</sub> of the SiC MOSFET. However, the larger|dV<sub>GS</sub>/dt|also leads to the larger V<sub>GS</sub> overshoot. This work demonstrates that a well balance between the switching loss and overshoot can be found by optimizing the driving waveform.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"167 ","pages":"Article 115653"},"PeriodicalIF":1.6,"publicationDate":"2025-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143534752","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Shiwei Zhao , Yuzhu Liu , Xiaoyu Yan , Peipei Hu , Xinyu Li , Qiyu Chen , Pengfei Zhai , Teng Zhang , Yang Jiao , Youmei Sun , Jie Liu
{"title":"Effect of gate oxide thickness on gate latent damage induced by heavy ion in SiC power MOSFETs","authors":"Shiwei Zhao , Yuzhu Liu , Xiaoyu Yan , Peipei Hu , Xinyu Li , Qiyu Chen , Pengfei Zhai , Teng Zhang , Yang Jiao , Youmei Sun , Jie Liu","doi":"10.1016/j.microrel.2025.115663","DOIUrl":"10.1016/j.microrel.2025.115663","url":null,"abstract":"<div><div>SiC materials and devices hold significant promise for aerospace applications owing to their high thermal conductivity, temperature tolerance, and resistance to harsh conditions. However, SiC power devices often encounter single event effects (SEEs) induced by high-energy ions, which limit the applications in space radiation environments. In this study, we demonstrate the impact of thickness of gate oxide layer on latent gate oxide damage in Silicon carbide (SiC) power metal oxide semiconductor field effect transistors (MOSFETs) during heavy-ion irradiation, by using a combination of experiments and technical computer-aided design (TCAD) simulations. The study exposes SiC MOSFETs with gate oxide thicknesses of 40 nm and 60 nm to 78Kr ion irradiation followed by post-irradiation gate stress (PIGS) tests, scrutinizing failure characteristics induced by irradiation. Through TCAD simulations, the internal dynamics of the gate oxide layer are scrutinized, revealing that escalated electric fields and localized energy pulses predominantly precipitate gate dielectric layer damage. The results suggest that gate oxide thickness markedly impacts latent gate damage, with thinner oxide layers exhibiting heightened susceptibility to electrical breakdown. These findings enrich the comprehension of SiC power device reliability in radiation-rich environments, furnishing invaluable insights for aerospace applications.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"167 ","pages":"Article 115663"},"PeriodicalIF":1.6,"publicationDate":"2025-03-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143529661","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Yun-Chan Kim , Dong-Yurl Yu , Shin-Il Kim , Yong-Mo Kim , Dongjin Byun , Junghwan Bang , Dongjin Kim
{"title":"Heat-resistant durability of AMB substrates for SiC power devices: AlN and Si3N4, which one is thermally strong?","authors":"Yun-Chan Kim , Dong-Yurl Yu , Shin-Il Kim , Yong-Mo Kim , Dongjin Byun , Junghwan Bang , Dongjin Kim","doi":"10.1016/j.microrel.2025.115676","DOIUrl":"10.1016/j.microrel.2025.115676","url":null,"abstract":"<div><div>In terms of long-term reliability, the present study investigated the heat-resistant durability of both AlN- and Si<sub>3</sub>N<sub>4</sub> cored active metal brazing (AMB) substrates to demonstrate which material can be a better option for use in silicon carbide (SiC) power applications. Interfacial degradation behaviors, peeling strengths, and fracture modes of the AlN- and Si<sub>3</sub>N<sub>4</sub>-AMB substrates were carried out before and after thermal shock cycling tests. The interfacial microstructure analysis of the AlN- and Si₃N₄-AMB substrates observed different brazing filler metal (BFM) reaction layers depending on the type of ceramic. As a result, it was noteworthy that AlN and Si<sub>3</sub>N<sub>4</sub>-AMB substrates subjected to repeated thermal shock cycles with Δ190 °C for up to 1000 cycles represented different failure modes with different strength in the peel strength test, respectively. Namely, these two kinds of ceramic type AMB substrates have fundamental differences in thermal shock durability. Nevertheless, cracks between the AMB and ceramic layers were equally caused on the edge side of the AlN and Si<sub>3</sub>N<sub>4</sub> cases after the thermal shock test. These cracks are the underlying principles that explain the load-extension plots in the peel strength test. This study systematically discussed the heat-resistant reliability of AMB substrates with AlN and Si<sub>3</sub>N<sub>4</sub> as key materials for application to next-generation SiC power devices.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"167 ","pages":"Article 115676"},"PeriodicalIF":1.6,"publicationDate":"2025-03-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143534751","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}