Microelectronics Reliability最新文献

{"title":"Analytical solution for forced vibration of multilayer structures composed of plates with different geometric dimensions","authors":"Bin Li ,&nbsp;Xin Yao ,&nbsp;Shuantao Li ,&nbsp;Yongbin Ma","doi":"10.1016/j.microrel.2024.115472","DOIUrl":"10.1016/j.microrel.2024.115472","url":null,"abstract":"<div><p>Multilayer system composed of parallel plate components with different geometric dimensions is frequently used to describe engineering objects, such as electronic assembly. In this work, an analytical method was proposed for forced vibration of this type of multilayer system. The proposed method overcomes the limitation that the traditional wave method is only applicable to all plate components must have the same in-plane dimensions. The proposed analytical method has an efficiency advantages in parameter analysis than element-based methods such as finite element method (FEM). The connection joints between two adjacent plate components, such as ball grid array (BGA) solder interconnect, are represented by elastic springs. The vibration of each component are described in terms of general and physical analytical waves, respectively, and the dynamic coupling between them are established by an equivalent dynamic flexibility matrix. The forced responses of the multilayer system are analytically calculated by solving the system equation in wave space. In the numerical examples, the effectiveness of the proposed method is validated by comparing the present results with the FEM results. The influence of number of the defective solder joints on vibration response is also investigated.</p></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"160 ","pages":"Article 115472"},"PeriodicalIF":1.6,"publicationDate":"2024-07-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141866406","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Two-step sub-modeling framework for thermomechanical fatigue analysis of solder joints in DRAM module","authors":"Hyun Suk Lee ,&nbsp;Giseok Yun ,&nbsp;Ju-Hwan Song ,&nbsp;Do-Nyun Kim","doi":"10.1016/j.microrel.2024.115469","DOIUrl":"10.1016/j.microrel.2024.115469","url":null,"abstract":"<div><p>The characteristics of thermomechanical fatigue life of complex electronic device system, micro-scaled design, is highly sensitive to changes in design factors. The solder ball, which acts as a linkage between the circuit board and the package, is a vital part to examine the performance of electronic device system. Repeated thermal loading causes the solder crack growth in models, eventually leads to the breakdown of devices. There have been lots of studies on investigating the fatigue life of solder joints employing well-established finite element procedure. However, generating a finite element model reflecting the whole device often requires unnecessarily large finite element matrices which may increase the computational cost and solder joint fatigue life can be highly dependent on the mesh resolutions. Recent studies suggest the sub-modeling method to handle the meshing process and alleviate the computational cost. In this paper, we delineate the methodology of two-step sub-modeling framework, aimed at improving the mesh fidelity of complex models while ensuring the efficiency of labor-intensive process of solder joint fatigue analysis. We employ the strain energy-based Darveaux's fatigue model to predict the fatigue life of solder joints. Through the investigation of the predicted fatigue life of solder joints across various sets of design parameters, it has been observed that the design factors of electronic devices exhibit a clear pattern in relation to the predicted fatigue life, even when only the second step of two-step sub-modeling framework is considered. Our findings suggest that it is efficient to utilize solely the second step of two-step sub-modeling framework to identify an appropriate reduced design space, where design parameters can be strategically selected for designing an optimal model.</p></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"160 ","pages":"Article 115469"},"PeriodicalIF":1.6,"publicationDate":"2024-07-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141866315","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Fault-tolerant multiplier using self-healing technique","authors":"Raghavendra Kumar Sakali ,&nbsp;Noor Mahammad Sk","doi":"10.1016/j.microrel.2024.115458","DOIUrl":"10.1016/j.microrel.2024.115458","url":null,"abstract":"<div><p>A Field Programmable Gate Array (FPGA) is a versatile device capable of reconfiguring the logic of circuits as required. FPGAs are widely utilized in developing critical systems for space applications, defence, and aviation due to their adaptability. To facilitate the operation of these systems, a multiplier circuit is often necessary. As mission-critical systems work in a radiation environment, which affects electronic devices, the FPGA is susceptible to radiation effects that may disrupt the functionality of the configured circuit. To address this, the multiplier needs a robust fault-tolerance mechanism. Evolvable-based hardware solutions hold promise for mitigating faults, but challenges related to scalability and error recovery time persist. To address these challenges, we introduce a novel approach: a self-healing multiplier equipped with a configuration bitstream generator (CBG). This innovation effectively mitigates scalability concerns through the use of an optimized Virtual Reconfigurable Circuit (VRC) multiplier design. Additionally, the proposed solution significantly improves error recovery time through CBG integration. Our primary focus in this work is on the intrinsic approach to achieving efficient performance. In the case of the 8 × 8 multiplier, the proposed work reduces 64.59% of LUT utilization and recovers the error in 29.25 ns using an intrinsic approach. In parallel, we employ a hybrid approach to provide a comparative analysis against the intrinsic approach, demonstrating its performance. We implemented the proposed methodology on the A3PE3000 FPGA platform and conducted a comparative analysis against the proposed hybrid approach and existing methods. The results validate the superior performance and efficiency of our work using the intrinsic approach.</p></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"160 ","pages":"Article 115458"},"PeriodicalIF":1.6,"publicationDate":"2024-07-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141866407","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Synergistic effects of heating and biasing of AlGaN/GaN high electron mobility transistors: An in-situ transmission electron microscopy study","authors":"Nahid Sultan Al-Mamun ,&nbsp;Ahmad Islam ,&nbsp;Nicholas Glavin ,&nbsp;Aman Haque ,&nbsp;Douglas E. Wolfe ,&nbsp;Fan Ren ,&nbsp;Stephen Pearton","doi":"10.1016/j.microrel.2024.115470","DOIUrl":"10.1016/j.microrel.2024.115470","url":null,"abstract":"<div><p>High temperature adversely affects the reliability of AlGaN/GaN high electron mobility transistors (HEMTs). Degradation studies typically involve post-mortem visualization of the device cross-section to identify failure mechanisms. In this study, we present an in-situ technique by operating the transistor inside the transmission electron microscope (TEM) for real time observation of the defects and failure. A custom-made MEMS chip facilitates the simultaneous biasing and heating capability inside the TEM. The results indicate that the high temperature operation promotes nucleation of new defects in addition to the propagation of existing defects, which degrade the performance of the device even at low biasing conditions. The gate Schottky contact is found to be the most vulnerable region at elevated temperature. The diffusion of gate metals, especially the diffusion of Au at the metal-semiconductor interface initiates the gate degradation process, as confirmed by energy dispersive X-ray spectroscopy (EDS), followed by catastrophic failure with the increase of operation temperature and drain biasing voltage. The high-resolution TEM imaging along with geometric phase analysis reveals the evolution of defect clusters, such as dislocations networks, stacking faults, and amorphized regions, in the AlGaN and GaN layers, which increases the lattice strain leading to catastrophic failure at elevated temperature. The insights obtained from the in-situ study may be useful in improving high temperature HEMT reliability.</p></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"160 ","pages":"Article 115470"},"PeriodicalIF":1.6,"publicationDate":"2024-07-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141866404","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Revisiting row hammer: A deep dive into understanding and resolving the issue","authors":"Haibin Wang ,&nbsp;Xiaoshuai Peng ,&nbsp;Zhi Liu ,&nbsp;Xiaofeng Huang ,&nbsp;Lian'gen Qiu ,&nbsp;Tan Li ,&nbsp;Baoyao Yang ,&nbsp;Yuzheng Chen","doi":"10.1016/j.microrel.2024.115467","DOIUrl":"10.1016/j.microrel.2024.115467","url":null,"abstract":"<div><p>Row hammer is a vulnerability in Dynamic Random Access Memory (DRAM) chips, whereby repeatedly accessing a specific row in the DRAM chip may cause bit flips in memory cells. As the DRAM fabrication process scales down, DRAM chips are becoming more susceptible to row hammer. To gain a comprehensive understanding of the row hammer vulnerability, we investigate its mechanisms, attack patterns, simulation methodology and tools, as well as mitigation techniques. We also summarize several impact factors of row hammer, including timing parameters, temperature, DRAM fabrication process, radiation effects, voltage level, and data patterns. Finally, we point out future research directions, such as exploring how radiation effects and temperature impact row hammer, modeling and simulation methodology under advanced technology nodes, and deep-learning-based mitigation solutions.</p></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"160 ","pages":"Article 115467"},"PeriodicalIF":1.6,"publicationDate":"2024-07-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141774359","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"The impact of paste alloy, paste volume, and surface finish on solder joint","authors":"Abdallah Alakayleh ,&nbsp;Sa'd Hamasha ,&nbsp;Ali Alahmer","doi":"10.1016/j.microrel.2024.115457","DOIUrl":"10.1016/j.microrel.2024.115457","url":null,"abstract":"<div><p>The reliability of solder joints is significantly influenced by the microstructure of SAC (Sn-Ag-Cu) solders, which is affected by various factors, including paste alloy, paste volume, and surface finish. This study explores the impact of these factors on the microstructure, thickness of the intermetallic compound (IMC) layer, hardness, and macro void presence in as-reflowed joints. Three lead-free solder alloys, namely SAC305 (Sn - 3.0Ag - 0.5Cu), SAC-Bi (Sn - 3.0Ag - 3.0Bi - 0.8Cu), and SAC-Bi-Sb (Sn - 3.4Ag - 3.2Bi - 3.0Sb - 0.7Cu), were tested with varying solder paste-to-sphere ratios with electroless nickel immersion gold (ENIG) and organic solderability preservative (OSP) surface finishes. ENIG involves applying a thin layer of gold over a layer of nickel on the copper surfaces. Whereas OSP is a thin organic coating designed to protect copper surfaces from oxidation. The evaluation incorporated the analysis of Ag₃Sn particles, IMC thickness, and voids through scanning electron and optical microscopy and X-ray images. Additionally, microhardness was assessed by indenting seven solder joints using the Phase II Model 900–391,391 micro-Vickers hardness tester. The study revealed that the SAC305 exhibited a higher presence of Ag₃Sn particles than SAC-Bi and SAC-Bi-Sb. A direct proportionality was observed between paste volume and the quantity of Ag₃Sn particles. Conversely, an inverse relationship was identified between paste volume and IMC layer thickness, resulting in a thinner IMC layer with higher paste volume, regardless of the paste alloy used. Furthermore, the use of ENIG led to a reduction in IMC thickness, attributed to the inhibitory effect of the Ni barrier. Doped alloys, specifically SAC-Bi and SAC-Bi-Sb, displayed superior microhardness compared to SAC305, owing to the strengthening and hardening effects of Bi and Sb. Regarding solder voiding, a noteworthy observation indicated that an increase in the quantity of solder paste resulted in the formation of larger voids.</p></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"160 ","pages":"Article 115457"},"PeriodicalIF":1.6,"publicationDate":"2024-07-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141785327","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Numerical modeling of total dose effects on CD4007 MOSFET during switched-bias irradiation","authors":"L. Sambuco Salomone ,&nbsp;M. Garcia-Inza ,&nbsp;J. Lipovetzky ,&nbsp;M.V. Cassani ,&nbsp;E. Redin ,&nbsp;A. Faigón ,&nbsp;S. Carbonetto","doi":"10.1016/j.microrel.2024.115468","DOIUrl":"10.1016/j.microrel.2024.115468","url":null,"abstract":"<div><p>The response of commercial-off-the-shelf CD4007 p-channel MOSFET exposed to ⁶⁰Co radiation under switched-bias conditions is studied by real time monitoring the threshold voltage evolution with accumulated dose. The possibility to employ switched-bias techniques to recover threshold voltage is demonstrated. As reported for other devices, non-monotonic responses are observed. A physics-based numerical model that takes into account both charge buildup within the oxide and generation of interface traps is employed to reproduce the experimental results. The implications for dosimetry are discussed.</p></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"160 ","pages":"Article 115468"},"PeriodicalIF":1.6,"publicationDate":"2024-07-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141774360","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Characteristics and avalanche investigation of SiC VDMOSFETs with enhanced P-Based implantation","authors":"Houcai Luo ,&nbsp;Jingping Zhang ,&nbsp;Huan Wu ,&nbsp;Bofeng Zheng ,&nbsp;Xiao Wang ,&nbsp;Kai Zheng ,&nbsp;Guo-Qi Zhang ,&nbsp;Xianping Chen","doi":"10.1016/j.microrel.2024.115451","DOIUrl":"10.1016/j.microrel.2024.115451","url":null,"abstract":"<div><p>Two P-Based depth of SiC VDMOSFETs (group A and B) are designed and manufactured by enhanced P-Based implantation. The group A with lower P-based depth has a better static properties, while group B has a higher high frequency switching performance. Further, the avalanche reliability and failure mechanism for two groups are investigated by UIS experiment and TCAD simulation. The results show that the high temperature is generated by energy dissipation during avalanche and it drives the parasitic BJT conduction, causing I_ds out of control and instantaneous heat concentration in a very short time. Significantly, high P-Based depth exhibits higher UIS reliability due to smaller R_b and more difficult to active parasitic BJT.</p></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"160 ","pages":"Article 115451"},"PeriodicalIF":1.6,"publicationDate":"2024-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141636869","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A trench beside field limiting rings terminal for improved 4H-SiC junction barrier Schottky diodes: Proposal and investigation","authors":"Xiaofeng Ye ,&nbsp;Huihuang Ke ,&nbsp;Shubo Wei ,&nbsp;Hongjin Weng ,&nbsp;Xinwei Wang ,&nbsp;Shen Yuong Wong ,&nbsp;Weifeng Yang","doi":"10.1016/j.microrel.2024.115459","DOIUrl":"10.1016/j.microrel.2024.115459","url":null,"abstract":"<div><p>A novel trench beside field limiting rings (TBFLR) terminal for 4H-SiC junction barrier Schottky (JBS) diodes is introduced and analyzed by technical computer-aided design (TCAD) simulation, addressing the electric field crowding challenge in high-voltage applications. The design parameters of the devices are optimized by striking a balance between forward and reverse electrical performances. Comparative analysis reveals that TBFLR significantly reduces the surface peak electric field, making it particularly advantageous for shallow-junction devices. Conversely, trench inside FLR (TFLR) is suited for deep-junction applications due to its deeper junction and higher breakdown voltage (BV). The TBFLR design excels with its low on-resistance and compact terminal length, especially in ultra-high voltage (&gt;6500 V) scenarios, achieving target BV with fewer rings and reduced terminal area. Notably, the TBFLR has a terminal efficiency of at least 80 % while keeping trench depth within the 60 % range of the junction depth. Furthermore, an enhanced computational model is proposed, which introduces harmonic parameters to quantify the role of the trench in FLR, and this adaptable model can be effectively extended to the composite renewal of FLR structures. This work provides a distinct application strategy for trench-based FLR structures, significantly broadening the scope of terminal design possibilities.</p></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"160 ","pages":"Article 115459"},"PeriodicalIF":1.6,"publicationDate":"2024-07-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141636868","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A review on warpage measurement metrologies for advanced electronic packaging","authors":"Guoli Sun ,&nbsp;Shuye Zhang","doi":"10.1016/j.microrel.2024.115456","DOIUrl":"10.1016/j.microrel.2024.115456","url":null,"abstract":"<div><p>In the post-Moore era, advanced electronic packaging technology emerges as a prominent direction for the future evolution of semiconductor industry. Nevertheless, warpage remains a prevalent issue in this domain, capable of significantly disrupting the precision and automation operation of subsequent processes, thereby precipitating various operational challenges. Consequently, the comprehensive examination of warpage assumes paramount important in enhancing packaging assembly yield and ensuring device reliability. The rigorous measurement of warpage through experimental methodologies assumes a pivotal role in investigating warpage-related concerns. Thus, this review has succinctly encapsulated established warpage measurement metrologies that are extensively employed in advanced semiconductor packages, shedding light on the measurement capabilities, advantages and limitations inherent of each technique. Typically, warpage measurement techniques can be broadly categorized into two main classes: contact and noncontact methods. Noteworthy examples of the former category encompass moiré interferometry, digital image correlation (DIC), laser scanning measurement and optical interferometry, while the later involves stylus-based technique and the use of ruler for warpage data acquisition. Furthermore, this study encompasses a comprehensive examination of all the aforementioned measurement methods and offers insights into their comparative analysis, as well as future prospects. Notably, empirical investigations suggest that moiré-based methodologies reign supreme. This discourse delineates the technical challenges and future development trends facing each warpage measurement method. In essence, the goal of this study is to furnish concise and coherent guidelines and support for engineers and researchers seeking to navigate the realm of warpage measurement within the sphere of advanced electronic packaging.</p></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"160 ","pages":"Article 115456"},"PeriodicalIF":1.6,"publicationDate":"2024-07-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141636870","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}