Microelectronics Reliability最新文献

Reliability and failure analysis of AlGaN/GaN HEMT with NiPtAu and PtAu gate

IF 1.6 4区工程技术

Microelectronics Reliability Pub Date : 2025-04-01 DOI: 10.1016/j.microrel.2025.115718

M. Dammann , P. Brückner , R. Driad , S. Krause , S.A. Albahrani , B. Weber , M. Baeumler , H. Konstanzer , M. Mikulla , M. Simon-Najasek , S. Hübner , A. Graff

{"title":"Reliability and failure analysis of AlGaN/GaN HEMT with NiPtAu and PtAu gate","authors":"M. Dammann , P. Brückner , R. Driad , S. Krause , S.A. Albahrani , B. Weber , M. Baeumler , H. Konstanzer , M. Mikulla , M. Simon-Najasek , S. Hübner , A. Graff","doi":"10.1016/j.microrel.2025.115718","DOIUrl":"10.1016/j.microrel.2025.115718","url":null,"abstract":"<div><div>By comparing the reliability of 150 nm AlGaN/GaN HEMTs with PtAu gates to devices with NiPtAu SiN assisted gates, it was found that PtAu gates are more stable in terms of gate leakage current increase under HTRB step stress test and show smaller spread of the extrapolated lifetime values during long-term DC stress tests. An activation energy of 1.39 eV (1.97 eV) and a lifetime of around 10<sup>7</sup> h at T<sub>ch</sub> = 175 °C and V<sub>d</sub> = 30 V has been extrapolated for devices with PtAu (NiPtAu) SiN assisted gate. By TEM cross sectioning and EDX mapping analysis of aged devices, the degradation of NiPtAu gate devices was attributed to a stress-induced local oxidation of the SiN passivation on the drain side of the gate foot. An activation energy of 1.15 eV and a lifetime of 5 · 10<sup>4</sup> h at T<sub>ch</sub> = 175 °C and V<sub>d</sub> = 15 V has been extrapolated for devices with 100 nm T-gate reference technology. The faster degradation of the T-gate is possibly caused by a higher lateral electric field at the gate foot. T-gate reference technology lifetime is increased by more than an order of magnitude by reducing the drain voltage to 10 V.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"168 ","pages":"Article 115718"},"PeriodicalIF":1.6,"publicationDate":"2025-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143737851","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Impact of drain-source leakage on the dynamic Ron of power HEMTs with p-GaN gate

IF 1.6 4区工程技术

Microelectronics Reliability Pub Date : 2025-03-31 DOI: 10.1016/j.microrel.2025.115714

S.L. Longato , D. Favero , A. Stockman , A. Nardo , P. Vanmeerbeek , M. Tack , G. Meneghesso , E. Zanoni , C. De Santi , M. Meneghini

引用次数: 0

Risk of CuxO phase penetration between the Ag plating layer and Cu during high-temperature reliability testing of interfaces bonded to cold sintered Ag nano-porous sheets on direct Ag-plated Cu substrates

IF 1.6 4区工程技术

Microelectronics Reliability Pub Date : 2025-03-31 DOI: 10.1016/j.microrel.2025.115719

YehRi Kim , Eunjin Jo , Byeong Kwon Ju , Yoongul Lee , Jaeup Kim , Kijoon Ahn , Seungjun Noh , Dongjin Kim

{"title":"Risk of CuxO phase penetration between the Ag plating layer and Cu during high-temperature reliability testing of interfaces bonded to cold sintered Ag nano-porous sheets on direct Ag-plated Cu substrates","authors":"YehRi Kim , Eunjin Jo , Byeong Kwon Ju , Yoongul Lee , Jaeup Kim , Kijoon Ahn , Seungjun Noh , Dongjin Kim","doi":"10.1016/j.microrel.2025.115719","DOIUrl":"10.1016/j.microrel.2025.115719","url":null,"abstract":"<div><div>This study was carried out to understand the high-temperature stability of Ag nano-porous sheet bonded joints during thermal aging. The joints have been designed to be between two Ag metallization layers directly plated on copper layers of the die and substrate. The Cu<sub>x</sub>O penetration between Ag plated layer and Cu substrate formed during thermal aging at 250 °C from 125 h, during which Cu<sub>x</sub>O layer continuously grew up to 1000 h. The growing Cu<sub>x</sub>O phase penetrated between the Ag plating and Cu, leading to voids that developed into a delamination layer over time. The delamination and continuous voids formed between Cu<sub>x</sub>O layer and Cu had a critical effect on reducing the bonding strength. In this study, we thoroughly investigated the issues that may arise during thermal reliability testing at 250 °C when bonding commercial Ag nano-porous sheets directly Ag-plated onto Cu, from the perspective of microstructural development.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"168 ","pages":"Article 115719"},"PeriodicalIF":1.6,"publicationDate":"2025-03-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143737847","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Research on the degradation of contact resistance of wire-spring contacts in different wear condition

IF 1.6 4区工程技术

Microelectronics Reliability Pub Date : 2025-03-31 DOI: 10.1016/j.microrel.2025.115721

Le Xu , Yuyao Zhao , Shujuan Wang , Ji Jiang

引用次数: 0

Evaluation of the impact of body bias on the threshold voltage drift of planar SiO2 transistors 评估体偏压对平面二氧化硅晶体管阈值电压漂移的影响

IF 1.6 4区工程技术

Microelectronics Reliability Pub Date : 2025-03-30 DOI: 10.1016/j.microrel.2025.115693

Michael Waltl , Konstantinos Tselios , Theresia Knobloch , Dominic Waldhoer , Hubert Enichlmair , Eleftherios G. Ioannidis , Rainer Minixhofer , Tibor Grasser

{"title":"Evaluation of the impact of body bias on the threshold voltage drift of planar SiO2 transistors","authors":"Michael Waltl , Konstantinos Tselios , Theresia Knobloch , Dominic Waldhoer , Hubert Enichlmair , Eleftherios G. Ioannidis , Rainer Minixhofer , Tibor Grasser","doi":"10.1016/j.microrel.2025.115693","DOIUrl":"10.1016/j.microrel.2025.115693","url":null,"abstract":"<div><div>The performance of semiconductor transistors is significantly influenced by charge trapping at oxide and interface defects. The impact of charge-trapping events of defects on the characteristics of the transistor is strongly dependent on factors such as the geometry and the operating point at which the transistor is used. Understanding the complex relationships between the influence of defects and the robustness of devices is essential to optimize circuit performance and becomes particularly important in analog designs. In this work, we investigate the influence of gate oxide defects on the reliability of nanoscale MOS transistors under varying body bias conditions. Using measure-stress-measure techniques, we observe notable effects on both time-zero and time-dependent variability with the application of body bias. Furthermore, the amplitudes of the step heights are investigated as they provide an important measure in scaled technologies to estimate the impact of traps on the device behavior. The results indicate that a body bias can be strategically employed to enhance device reliability by fine-tuning the body bias conditions.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"168 ","pages":"Article 115693"},"PeriodicalIF":1.6,"publicationDate":"2025-03-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143735211","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Investigation of the long-term dynamic RDS(on) variation and dynamic high temperature operating life test robustness of Schottky gate and ohmic gate GaN HEMT with comparable stress conditions

IF 1.6 4区工程技术

Microelectronics Reliability Pub Date : 2025-03-30 DOI: 10.1016/j.microrel.2025.115708

Fawad Rauf , Muhammad Farhan Tayyab , Samir Mouhoubi , Marcelo Lobo Heldwein , Gilberto Curatola

{"title":"Investigation of the long-term dynamic RDS(on) variation and dynamic high temperature operating life test robustness of Schottky gate and ohmic gate GaN HEMT with comparable stress conditions","authors":"Fawad Rauf , Muhammad Farhan Tayyab , Samir Mouhoubi , Marcelo Lobo Heldwein , Gilberto Curatola","doi":"10.1016/j.microrel.2025.115708","DOIUrl":"10.1016/j.microrel.2025.115708","url":null,"abstract":"<div><div>The Dynamic High Temperature Operating Life (DHTOL) test, outlined in JEDEC standard JEP180.01, validates the long-term switching reliability of Gallium Nitride (GaN) High Electron Mobility Transistors (HEMTs) for power management applications. Despite the standardized testing framework, variability in switching test conditions across manufacturers necessitates a thorough investigation of GaN HEMT's long-term switching reliability within specific applications. This study adopts a holistic approach encompassing technological considerations and application demands to assess the long-term switching reliability of p-GaN HEMTs. The analysis emphasizes monitoring the degradation of the dynamic on-state resistance (<em>dR</em><sub>DS(on)</sub>). A structured methodology is employed to precisely model and validate current and voltage peaks via parasitic extraction, defining switching stress conditions. Junction temperature is estimated through FEM simulation of the package model, followed by long-term testing to evaluate degradation. In addition to the hard-switching stress tests with variable voltages, peak current, slew rates, and duty cycles, stress tests with switching loss-free conditions at different temperatures are also performed to assess the primary degradation mechanism. The comparison of long-term hard-switching stress tests and tests conducted under switching loss-free conditions highlights the hot electron effect as the primary contributor to long-term degradation during the hard-switching operation. The substantial influence of voltage and current overlap on degradation is validated by testing Schottky gate p-GaN HEMT with different slew rates. Furthermore, ohmic gate p-GaN HEMT is found to be relatively robust compared to Schottky gate-p-GaN HEMT under similar long-term hard-switching stress conditions.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"168 ","pages":"Article 115708"},"PeriodicalIF":1.6,"publicationDate":"2025-03-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143735212","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Response of the bipolar voltage regulator under neutron irradiation and consecutive pulsed gamma irradiation

IF 1.6 4区工程技术

Microelectronics Reliability Pub Date : 2025-03-28 DOI: 10.1016/j.microrel.2025.115709

Ruibin Li, Junlin Li, Chenhui Wang, Wei Chen, Weijian Liu, Shilin Yu, Xiaoyan Bai, Xiaoqiang Guo, Chao Qi, Yan Liu, Xiaoming Jin

{"title":"Response of the bipolar voltage regulator under neutron irradiation and consecutive pulsed gamma irradiation","authors":"Ruibin Li, Junlin Li, Chenhui Wang, Wei Chen, Weijian Liu, Shilin Yu, Xiaoyan Bai, Xiaoqiang Guo, Chao Qi, Yan Liu, Xiaoming Jin","doi":"10.1016/j.microrel.2025.115709","DOIUrl":"10.1016/j.microrel.2025.115709","url":null,"abstract":"<div><div>Two types of radiation experiments were carried out on a bipolar three-terminal fixed voltage regulator μA78m33. The device was first irradiated by neutron, and then by pulsed gamma irradiation, for the purpose of finding out the impact of neutron displacement damage on the pulsed gamma radiation response of the device. The results show that, as irradiated by neutrons in power-up state, the device with larger load current can withstand higher neutron fluence, which indicates that the carrier concentration in the device can alleviate the displacement damage to some extent; when the device is irradiated by pulsed gamma, the output voltage produces a significant interruption and the duration of the interruption is shortened with the increase of the neutron fluence. It is shown that the displacement defects caused by neutrons reduce the transient interruption duration of the regulator, mainly because the recombination centers formed by the displacement defects significantly reduce the minority carrier lifetime, thus reducing the duration of the photocurrent generated by pulsed gamma irradiation, but has little relation with the variation of the current gain of the transistor induced by neutron irradiation.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"168 ","pages":"Article 115709"},"PeriodicalIF":1.6,"publicationDate":"2025-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143724481","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Failure modes competition and long-term reliability in the isothermal aging of sintered Cu joints

IF 1.6 4区工程技术

Microelectronics Reliability Pub Date : 2025-03-28 DOI: 10.1016/j.microrel.2025.115717

Jianbo Xin , Xiaochun Lv , Yue Gao , Le Yang , Sushi Liu , Ke Li , Minghao Zhou , William Cai , Jing Zhang , Yang Liu

{"title":"Failure modes competition and long-term reliability in the isothermal aging of sintered Cu joints","authors":"Jianbo Xin , Xiaochun Lv , Yue Gao , Le Yang , Sushi Liu , Ke Li , Minghao Zhou , William Cai , Jing Zhang , Yang Liu","doi":"10.1016/j.microrel.2025.115717","DOIUrl":"10.1016/j.microrel.2025.115717","url":null,"abstract":"<div><div>Sintered Cu joints may experience diminished reliability due to oxidation during the operation of wide-bandgap (WBG) semiconductor devices. This study utilized the aging process of Cu sintered joints in a vacuum environment as a reference to investigate the microstructural evolution and mechanical property changes of Cu sintered joints under varying aging temperatures in air. Based on the fracture morphology, the failure modes of the joints were categorized into three primary types: (1) ductile fracture within the sintered layer, (2) brittle fracture within the sintered layer, and (3) brittle fracture at the interface. These variations are primarily attributed to increased oxidation during the aging process, which leads to a continuous increase in joint strength and a transition between distinct fracture modes characterized by competing failure mechanisms. Additionally, Kirkendall voids were observed in all joints aged at varying temperatures, and mixed ductile-brittle fracture morphology was evident on the fracture surfaces, indicating that Cu sintered joints undergo a similar aging process across different temperatures.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"168 ","pages":"Article 115717"},"PeriodicalIF":1.6,"publicationDate":"2025-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143725172","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Design and verification of silicon bridge in 2.5D advanced package based on universal chiplet interconnect express (UCIe)

IF 1.6 4区工程技术

Microelectronics Reliability Pub Date : 2025-03-26 DOI: 10.1016/j.microrel.2025.115710

Yuxuan Fan , Yunyan Zhou , Qidong Wang , Bo Lei , Gang Song , Wenwen Zhang , Hanchen Gan

{"title":"Design and verification of silicon bridge in 2.5D advanced package based on universal chiplet interconnect express (UCIe)","authors":"Yuxuan Fan , Yunyan Zhou , Qidong Wang , Bo Lei , Gang Song , Wenwen Zhang , Hanchen Gan","doi":"10.1016/j.microrel.2025.115710","DOIUrl":"10.1016/j.microrel.2025.115710","url":null,"abstract":"<div><div>This paper presents the design and verification of an embedded silicon bridge interconnect structure for 2.5D advanced packaging based on the Universal Chiplet Interconnect Express (UCIe). To enable high-speed, low-latency communication between chiplets, various routing patterns and transmission structures were explored. Layouts and test vehicles were designed with bump pitches of 45 μm and 55 μm and underwent fabrication for validation. Test results indicate that the silicon bridge demonstrates excellent signal integrity (SI) at a transmission rate of 32 Gbps, with S-parameter, Voltage Transfer Function (VTF) and eye diagram test results all meeting UCIe specifications for advanced packaging, highlighting the feasibility of this interconnect structure for high-density integration and high-speed transmission. This research provides a viable design and manufacturing solution for UCIe-based chiplet interconnects and validates the potential of embedded silicon bridges in heterogeneous integration applications.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"168 ","pages":"Article 115710"},"PeriodicalIF":1.6,"publicationDate":"2025-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143705195","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

ESD Human Body Model step stress distributions of GaN HEMTs and the correlation with one level test results

IF 1.6 4区工程技术

Microelectronics Reliability Pub Date : 2025-03-26 DOI: 10.1016/j.microrel.2025.115699

R.A. van der Berg , E. Jellema

{"title":"ESD Human Body Model step stress distributions of GaN HEMTs and the correlation with one level test results","authors":"R.A. van der Berg , E. Jellema","doi":"10.1016/j.microrel.2025.115699","DOIUrl":"10.1016/j.microrel.2025.115699","url":null,"abstract":"<div><div>Evaluation of the Electro Sensitivity Discharge (ESD) robustness of Radio Frequency (RF) GaN HEMTs can result in different Human Body Model (HBM) ESD classifications due to different sample sizes, batch-to-batch variations, different test methodology and differences in the test set-up. For example, a low sample sizes per voltage level can lead to a higher classification level.</div><div>Two GaN HEMTs processed in the same technology with different power ratings were investigated with (i) step stress testing, and (ii) with testing at one voltage level, using different test set-ups and different wafer and assembly batches. A lognormal distribution gives a good fit for the HBM failure voltages acquired from step stress testing and can quantify the differences between GaN HEMTs, test set-ups and different batches.</div><div>The failure percentages observed with one level testing can be significantly lower than what is expected based on the step stress HBM failure distribution. Furthermore, the spread observed in the HBM failure distributions acquired by testing at one voltage level is significantly larger than the spread observed in the HBM failure distribution as determined by step stress testing.</div><div>The differences between one level and the step stress failure distribution can be explained by presence of traps inside the GaN HEMT devices.</div><div>Furthermore, the ESD classification according to JS-001 [1] is discussed and how Operating Characteristics (OC) curves can be used to compare ESD test plans with different sample sizes and number of failures observed.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"168 ","pages":"Article 115699"},"PeriodicalIF":1.6,"publicationDate":"2025-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143697144","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0