Microelectronics Reliability最新文献

Study on single-event burnout hardening with reduction of hole current density by top polysilicon diode of SOI LDMOS based on TCAD simulations 基于 TCAD 仿真的 SOI LDMOS 顶部多晶硅二极管降低空穴电流密度的单次烧毁硬化研究

IF 1.6 4区工程技术

Microelectronics Reliability Pub Date : 2024-11-17 DOI: 10.1016/j.microrel.2024.115551

Wenze Niu, Hongli Dai, Luoxin Wang, Yuming Xue, Haitao Lyu, Jinjun Guo

{"title":"Study on single-event burnout hardening with reduction of hole current density by top polysilicon diode of SOI LDMOS based on TCAD simulations","authors":"Wenze Niu, Hongli Dai, Luoxin Wang, Yuming Xue, Haitao Lyu, Jinjun Guo","doi":"10.1016/j.microrel.2024.115551","DOIUrl":"10.1016/j.microrel.2024.115551","url":null,"abstract":"<div><div>In this paper, a single-event burnout (SEB)-hardened design for silicon-on-insulator lateral double-diffused MOSFET (SOI LDMOS) with a top polysilicon PN-junction diode (PN-LDMOS) is presented. By analyzing the hole current density of the device at different time points after a heavy-ion event, it is found that the introduced top polysilicon diode structure can reduce the hole current flowing to the source remarkably at a certain time. Thus, the voltage drop between the emitter and base of the parasitic NPN bipolar junction transistor (BJT) inherent in the device structure is reduced, and the deep p+ structure provides a low resistance path for the holes. The combined effect of these two structures effectively suppresses the turn-on of parasitic BJT and significantly reduces the risk of SEB occurrence. Compared to the traditional LDMOS (C-LDMOS), at a LET of 0.2 pC/μm, the SEB trigger voltage (<em>V</em><sub>SEB</sub>) of PN-LDMOS is improved from 129 V to 200 V, and the safe operating area (SOA) ratio (<em>η</em>) is increased from 58.8 % to 80 %. And the combination of polysilicon diode and field plates also optimizes the surface electric field distribution, increasing the breakdown voltage from 219.4 V to 249.7 V.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"163 ","pages":"Article 115551"},"PeriodicalIF":1.6,"publicationDate":"2024-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142657144","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

An online junction temperature detection circuit for SiC MOSFETs considering threshold voltage drift compensation 考虑阈值电压漂移补偿的 SiC MOSFET 在线结温检测电路

IF 1.6 4区工程技术

Microelectronics Reliability Pub Date : 2024-11-17 DOI: 10.1016/j.microrel.2024.115548

Ruoyin Wang , Xiaoyong Zhu

{"title":"An online junction temperature detection circuit for SiC MOSFETs considering threshold voltage drift compensation","authors":"Ruoyin Wang , Xiaoyong Zhu","doi":"10.1016/j.microrel.2024.115548","DOIUrl":"10.1016/j.microrel.2024.115548","url":null,"abstract":"<div><div>Temperature is the main factor affecting the reliability of SiC MOSFETs. Therefore, real-time monitoring technology for junction temperature has become a prerequisite for implementing thermal management strategies. Based on the temperature sensitive electrical parameter method, this paper first determines the temperature dependence of the threshold voltage Vth. Secondly, a SiC MOSFETs junction temperature detection circuit based on threshold voltage is constructed using a T flip-flop. Furthermore, based on this circuit, the junction temperature detection of SiC MOSFETs is achieved. This method has a simple circuit structure, does not require intrusion into the device interior, and can be measured online. Then, an inverter experimental platform is built, and the junction temperature detection performance of the proposed method is tested both offline and online. The experimental results showed that the proposed method has good sensitivity and linearity(-5 mV/°C), and the error is less than 3 °C. Finally, this paper further proposes a threshold voltage drift compensation strategy flow for the junction temperature model to correct the detection error caused by aging.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"163 ","pages":"Article 115548"},"PeriodicalIF":1.6,"publicationDate":"2024-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142657159","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Thermal cycling reliability of electronic components in bolted assemblies: A study of the influence of bolt position 螺栓组件中电子元件的热循环可靠性：螺栓位置影响研究

IF 1.6 4区工程技术

Microelectronics Reliability Pub Date : 2024-11-16 DOI: 10.1016/j.microrel.2024.115549

Shuaifeng Zhao , Weiqi Guo , Shaobin Wang , Weiwei Zhang , Xin Li

{"title":"Thermal cycling reliability of electronic components in bolted assemblies: A study of the influence of bolt position","authors":"Shuaifeng Zhao , Weiqi Guo , Shaobin Wang , Weiwei Zhang , Xin Li","doi":"10.1016/j.microrel.2024.115549","DOIUrl":"10.1016/j.microrel.2024.115549","url":null,"abstract":"<div><div>This paper aims to investigate the influence of bolt assembly position on the fatigue life characteristics of electronic components under thermal cycling loads. In this study, the parameters of the Unified Creep Plasticity (UCP) constitutive model for 63Sn37Pb solder were determined, along with the actual coefficients of thermal expansion (CTE) for each component within the electronic assembly. A high-precision finite element model (FEM) was developed and validated through temperature cycling tests on printed circuit board (PCB) assemblies. The error between the fatigue life of solder joints obtained from the temperature cycling tests and the FEM simulation was within 1 %. Finally, a thermal cycling simulation analysis was conducted on the PCB assembly under different bolt assembly positions. The simulation results revealed a correlation between the bolt assembly locations and the fatigue life of solder joints. The findings of this study can serve as a reference for future efforts aimed at improving the reliability of solder joints under various assembly conditions.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"163 ","pages":"Article 115549"},"PeriodicalIF":1.6,"publicationDate":"2024-11-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142657158","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Research on equivalent modeling and model testing verification methods for material mechanics parameters of TXV structure TXV 结构材料力学参数的等效建模和模型试验验证方法研究

IF 1.6 4区工程技术

Microelectronics Reliability Pub Date : 2024-11-14 DOI: 10.1016/j.microrel.2024.115545

Tingwei Gu, Ning Liu, Zhengsen Feng, Xiaodong Sun, Xiangdong Meng

{"title":"Research on equivalent modeling and model testing verification methods for material mechanics parameters of TXV structure","authors":"Tingwei Gu, Ning Liu, Zhengsen Feng, Xiaodong Sun, Xiangdong Meng","doi":"10.1016/j.microrel.2024.115545","DOIUrl":"10.1016/j.microrel.2024.115545","url":null,"abstract":"<div><div>Aiming at the problems of multi-scale mesh division and low computational efficiency encountered during TXV (through X via) structural simulation, an equivalent modeling method for material mechanics parameters of TXV structure is proposed. By conducting mechanics simulations on the minimum elements of three TXV structures, namely through silicon via (TSV), through mold via (TMV) and through glass via (TGV), the anisotropic material mechanics parameters of TXV structures corresponding to different substrate materials, via diameters, via depths and via pitches are obtained. Based on simulation data and BP (back propagation) neural network algorithm, the material mechanics parameter equivalence models of TXV structures are established. Based on the four-point bending method, the theoretical calculation and simulation analysis of the actual TSV structure are carried out, and the accuracy of the equivalent model is tested and verified by the force and strain measurement systems. The simulation and test results show that the prediction accuracy of equivalent models based on BP algorithm is high, and the prediction errors for training samples of TSV, TMV and TGV structures are less than 0.467 %, 3.571 % and 1.303 %, respectively, and the prediction errors for testing samples are less than 0.424 %, 3.130 % and 1.444 %, respectively. After equivalence and simplification, the mesh division and computational efficiency of the simulation model are improved significantly, the number of mesh elements is reduced by 95.79 %, and the calculation time is shortened by 94.17 %. The simulation accuracy based on the equivalent model is high, the strain simulation error between the simplified model and the complete model is 0.24 %, and the error between the strain simulation result of the simplified model and the actual measurement result is 2.81 %.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"163 ","pages":"Article 115545"},"PeriodicalIF":1.6,"publicationDate":"2024-11-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142657157","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

The impact of negative gate voltage on neutron-induced single event effects for SiC MOSFETs 负栅极电压对 SiC MOSFET 中子诱发的单事件效应的影响

IF 1.6 4区工程技术

Microelectronics Reliability Pub Date : 2024-11-14 DOI: 10.1016/j.microrel.2024.115547

Haibin Wang , Zhichao Nie , Xiaofeng Huang , Jianghao Gu , Zhixin Tan , Hantao Jing , Lihua Mo , Zhiliang Hu , Xueming Wang

{"title":"The impact of negative gate voltage on neutron-induced single event effects for SiC MOSFETs","authors":"Haibin Wang , Zhichao Nie , Xiaofeng Huang , Jianghao Gu , Zhixin Tan , Hantao Jing , Lihua Mo , Zhiliang Hu , Xueming Wang","doi":"10.1016/j.microrel.2024.115547","DOIUrl":"10.1016/j.microrel.2024.115547","url":null,"abstract":"<div><div>Atmospheric neutrons can cause failures in SiC power devices, especially in critical components such as SiC MOSFETs. SiC MOSFETs typically employ a negative gate bias in the off-state to prevent unnecessary false turn-on. However, this gate voltage in the off-state can influence the sensitivity to single-event effects (SEEs). In this paper, the impact of negative gate voltage on neutron-induced SEEs in SiC MOSFETs is investigated and analyzed. A high-precision irradiation test system is designed, upon which neutron irradiation experiments have been conducted at various drain-source voltages, each corresponding to two different gate-source voltages. The experimental results demonstrate that negative gate voltage increases the failure rate of SEEs. Based on Sentaurus TCAD, a 2D TCAD model of SiC MOSFET has been established for simulation, and the dependence of single-event gate rupture (SEGR) on negative gate voltage is analyzed, as well as its impact mechanism on single-event burnout (SEB).</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"163 ","pages":"Article 115547"},"PeriodicalIF":1.6,"publicationDate":"2024-11-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142657156","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Reliability optimization of dopant-free TFET performance through advanced metal layer techniques 通过先进的金属层技术优化无掺杂 TFET 性能的可靠性

IF 1.6 4区工程技术

Microelectronics Reliability Pub Date : 2024-11-12 DOI: 10.1016/j.microrel.2024.115542

Bandi Venkata Chandan, Madhura Prashant Bakshi, Kaushal Kumar Nigam

{"title":"Reliability optimization of dopant-free TFET performance through advanced metal layer techniques","authors":"Bandi Venkata Chandan, Madhura Prashant Bakshi, Kaushal Kumar Nigam","doi":"10.1016/j.microrel.2024.115542","DOIUrl":"10.1016/j.microrel.2024.115542","url":null,"abstract":"<div><div>To address the low ON-current and reliability issues of dopant-free TFETs, we have incorporated a metal-layer near the source/channel (S/C) interface. The use of this metal layer facilitates a larger flow of electrons near the junction, which helps the ON-current (<span><math><msub><mrow><mi>I</mi></mrow><mrow><mi>O</mi><mi>N</mi></mrow></msub></math></span>) exceed 10<sup>−4</sup> A/<span><math><mrow><mi>μ</mi><mi>m</mi></mrow></math></span> under lower biasing conditions. This enhancement in <span><math><msub><mrow><mi>I</mi></mrow><mrow><mi>O</mi><mi>N</mi></mrow></msub></math></span> improves various performance metrics in analog, RF, and linearity applications. Furthermore to assess dependability, we analyzed the impact of acceptor and donor charges on the DL-MS-TFET, focusing on trap effects near interface (ITCs). The results reveal that the presence of these trap charges significantly affects the flat-band voltage, leading to reduced variations in the performance of DL-MS-TFETs. Furthermore, we observed the influence of the metal strip work function on DC performance characteristics. A noticeable decrease in ON-current was found as the metal layer work function increased. Overall, the MS-dopant-free TFET demonstrates superior performance in the presence of ITCs, making it suitable for low-voltage and analog-RF applications.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"163 ","pages":"Article 115542"},"PeriodicalIF":1.6,"publicationDate":"2024-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142657147","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

The effect of oxide scaling on ionising radiation response of sense-switch flash cells 氧化物缩放对感应开关闪存电池电离辐射响应的影响

IF 1.6 4区工程技术

Microelectronics Reliability Pub Date : 2024-11-11 DOI: 10.1016/j.microrel.2024.115546

Hui Shi, Yinquan Wang, Lichao Cao, Genshen Hong, Ruocheng Zheng, Hejun Xu, Yi Wang, Rubin Xie

引用次数: 0

Experimental analysis of NBTI effects on QDI circuits with resistive bridging faults 具有电阻桥接故障的 QDI 电路的 NBTI 效应实验分析

IF 1.6 4区工程技术

Microelectronics Reliability Pub Date : 2024-11-08 DOI: 10.1016/j.microrel.2024.115544

Zina Lamine , Ghania Ait Abdelmalek , Rezki Ziani , Rabah Mokdad

{"title":"Experimental analysis of NBTI effects on QDI circuits with resistive bridging faults","authors":"Zina Lamine , Ghania Ait Abdelmalek , Rezki Ziani , Rabah Mokdad","doi":"10.1016/j.microrel.2024.115544","DOIUrl":"10.1016/j.microrel.2024.115544","url":null,"abstract":"<div><div>Detecting defects in Delay-Insensitive Circuits (DIC), particularly for clockless asynchronous circuits, poses a major challenge. Traditional testing methods are complex and result in significant overhead. The robustness of asynchronous circuits is crucial for ensuring the safety and reliability of critical systems, as undetected defects can compromise their operation. To address these challenges, our method leverages the unique voltage signatures of asynchronous circuits to identify resistive defects. Through our FPGA experiments, we demonstrated the circuits' ability to generate informative voltage signatures, thereby facilitating the detection of these defects. Additionally, we performed a combined analysis of resistive defect detection and the impact of aging caused by Negative-Bias Temperature Instability (NBTI) on Quasi Delay Insensitive (QDI) circuits. This analysis highlights how defects can evade manufacturing tests and evolve into dynamic faults over time. Our results provide a precise evaluation of this impact and propose a comprehensive approach to assess circuit robustness under realistic operating conditions.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"163 ","pages":"Article 115544"},"PeriodicalIF":1.6,"publicationDate":"2024-11-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142657145","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Signal integrity and heat transfer performance of through-boron nitride via 氮化硼通孔的信号完整性和传热性能

IF 1.6 4区工程技术

Microelectronics Reliability Pub Date : 2024-11-05 DOI: 10.1016/j.microrel.2024.115531

Chao Sun , Chunmin Cheng , Zhaofu Zhang , Gai Wu , Hutao Shi , Zhenyang Lei , Lijie Li , Kang Liang , Wei Shen , Sheng Liu

{"title":"Signal integrity and heat transfer performance of through-boron nitride via","authors":"Chao Sun , Chunmin Cheng , Zhaofu Zhang , Gai Wu , Hutao Shi , Zhenyang Lei , Lijie Li , Kang Liang , Wei Shen , Sheng Liu","doi":"10.1016/j.microrel.2024.115531","DOIUrl":"10.1016/j.microrel.2024.115531","url":null,"abstract":"<div><div>Silicon interposer is widely used in 2.5D integrated packages due to its good dielectric properties and mature process. However, silicon interposer is not suitable for high-power devices and radio frequency devices, suffering from poor signal integrity and low thermal conduction efficiency. In this work, c-BN is used as an interposer to provide a solution for electrical signal interference and thermal aggregation in the devices. In addition, PTFE, glass and h-BN, w-BN have also been studied for comparison. The finite element simulation results show that the return loss of the TBV (c) is 3.3 dB lower than that of the TSV at 40 GHz. The insertion loss of TBV (c) is 0.12 dB higher than that of TSV. The c-BN interposer performs better than the silicon interposer in terms of signal integrity, with a similar performance to the glass interposer. The accuracy of the finite element simulation is verified by the RLGC analytical model. The return loss of TBV (c) decreases due to the decrease in the interposer thickness, the increase in spacing between the Cu pillars or the increase in radius of the Cu pillars. Owing to the high thermal conductivity of c-BN, the horizontal and the vertical equivalent thermal conductivity of TBV (c) are approximately 8 times than those of TSV. The heat dissipation performance of TBV (c) is also better than that of TSV. The TBV (c) interposer shows advantages in both electrical and heat transfer aspects, which provide new perspectives for device development in 2.5D integrated packages.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"163 ","pages":"Article 115531"},"PeriodicalIF":1.6,"publicationDate":"2024-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142587129","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Modeling of HCI effect in nFinFET for circuit reliability simulation 用于电路可靠性模拟的 nFinFET 中 HCI 效应建模

IF 1.6 4区工程技术

Microelectronics Reliability Pub Date : 2024-11-05 DOI: 10.1016/j.microrel.2024.115543

Jun-an Zhang, Bo Liu, Hao Chen, Chao Li, Dan Li, Tiehu Li, Yunhua Lu, Qingwei Zhang

引用次数: 0