Microelectronics Reliability最新文献

{"title":"Influence of top-side metal layers on the performance of gold, silver, and copper wire bonds on aluminum pads","authors":"Hao-Lin Yen,&nbsp;Fang-I Lai","doi":"10.1016/j.microrel.2025.115615","DOIUrl":"10.1016/j.microrel.2025.115615","url":null,"abstract":"<div><div>This study analyzed the reliability of gold (Au), silver (Ag), and copper (Cu) wire bonds on aluminum (Al) pads coated with a multilayer Top-side metal (TSM) structure. The TSM structure was created by sequentially plating titanium (Ti), nickel–vanadium (NiV), and Ag on an Al pad, with Ag used as the surface contact layer for connection. The corrosion resistance of TSM -coated Al pads with Au, Ag, and Cu wire bonds was then examined through humidity testing, which involved pretreatment under moisture sensitivity level 3, and thermal aging at 200 °C for 5 h. The bonding interfaces of the pads were then investigated through scanning acoustic tomography, which indicated that all pads exhibited no wire bonding delamination. Testing results obtained for wire pull strength and ball shear strength indicated that the process capability index (CPK) values of the Cu wire bonds increased after thermal aging, which indicated the high thermal stability of these bonds; however, the CPK values of the Au and Ag bonds decreased marginally after thermal aging. Further analysis indicated that Au, Ag, and Cu formed solid solutions with the Ag layer of the TSM structure, and no intermetallic compound was generated; thus, the Au, Ag, and Cu wire bonds exhibited high stability and reliability even under high temperature and humidity. This study aids efforts to improve chip reliability and service life through appropriate wire material selection and TSM structure design.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"166 ","pages":"Article 115615"},"PeriodicalIF":1.6,"publicationDate":"2025-02-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143387071","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Investigation on FCBGA package with vertical-aligned carbon fiber thermal pad as thermal interface material","authors":"Mingming Yi,&nbsp;Yiou Qiu,&nbsp;Ping Wu,&nbsp;Guoliao Sun,&nbsp;Wenhui Zhu,&nbsp;Liancheng Wang","doi":"10.1016/j.microrel.2025.115607","DOIUrl":"10.1016/j.microrel.2025.115607","url":null,"abstract":"<div><div>Flip chip ball grid array (FCBGA) is the current main packaging form of CPU and GPU. With the miniaturization and intelligence of artificial intelligence chips, chip power consumption of FCBGA continues to increase (the power consumption of H100 has exceeded 800 W) and the heat dissipation problem has become increasingly serious. In the heat dissipation system of the entire chip, the thermal conductivity of thermal interface material (TIM) is a key bottleneck that limits the improvement of FCBGA package heat dissipation capability. Currently commercial TIMs such as X-23 have a thermal conductivity of 3.8–6 W/MK, which is not enough to cope with the high heat dissipation needs of existing FCBGAs. In this article, we introduced oriented carbon fibers into a silicone oil matrix to prepare a thermal pad with a thermal conductivity of 21.0 W/mK, and used it as TIM1 in FCBGA package. By optimization the key process including lid attach, dicing saw and package structure design, coverage rate reached 88.22 % after packaged. Thermal simulation shows that replace TIM in FCBGA from X-23 to homemade thermal pad, junction temperature (Tj) is reduced from 69.9 to 66.8 °C. In addition, reliability test was used carried out on FCBGA packaged incorporating carbon fiber thermal pad as TIM.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"166 ","pages":"Article 115607"},"PeriodicalIF":1.6,"publicationDate":"2025-02-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143379402","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Improved short circuit performance of silicon carbide VD-MOSFETs using a P+ implant","authors":"Prashant Singh ,&nbsp;Shreepad Karmalkar ,&nbsp;K. Akshay","doi":"10.1016/j.microrel.2025.115614","DOIUrl":"10.1016/j.microrel.2025.115614","url":null,"abstract":"<div><div>We show that the short circuit withstand time, <em>t</em>_<em>SC</em>, of a silicon carbide (SiC) Vertically Double-diffused Metal Oxide Semiconductor Field Effect Transistor (VD-MOSFET) can be raised using a P⁺ implant near the p-base corner of the device. Under short circuit conditions, this implant depletes the JFET region thereby reducing the peak short circuit current, <em>I</em>_<em>SC</em>, and consequently the lattice temperature. Hence, it takes a longer time for the peak device temperature to reach the failure threshold of ~1500 K. On the other hand, under normal on-state operation (when the drain to source voltage, <em>V</em>_<em>DS</em>, is low, ⁓20 V, <em>V</em>_<em>GS</em> = 20 V), P⁺ implant must deplete only an acceptably low fraction of the JFET width so that the on-state current remains unaffected. The window size, depth and dose of the implant can be optimized to yield the highest <em>t</em>_<em>SC</em> while simultaneously limiting the specific on-resistance, <em>R</em>_{<em>onsp</em>}. With the help of TCAD simulations calibrated with experiments, we show that the <em>t</em>_<em>SC</em> of a 0.6 kV device can be raised from 2.74 μs to 19 μs while restraining the rise in <em>R</em>_{<em>onsp</em>} within 12 % using a technologically feasible P⁺ double implant. SiC devices with the proposed implant can be switched using available gate drivers of Si IGBT and thus adopted in the industry readily.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"166 ","pages":"Article 115614"},"PeriodicalIF":1.6,"publicationDate":"2025-02-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143379403","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Increased high-temperature stiffness of an epoxy-based molding compound through high-temperature storage","authors":"Masaya Ukita,&nbsp;Keisuke Wakamoto,&nbsp;Ken Nakahara","doi":"10.1016/j.microrel.2025.115605","DOIUrl":"10.1016/j.microrel.2025.115605","url":null,"abstract":"<div><div>This paper investigates the tensile mechanical properties of epoxy-based molding compound (EMC) films containing 88 % silica filler. The EMC material was molded under 175 °C at 13.8 MPa pressure for 2 min and cured at 175 °C for 5 h to form 200 μm films. The films were cut into a dog-bone shape, whose stress–strain (<em>S</em><img><em>S</em>) curves were measured by quasi-static tensile test at a test temperature (<em>T</em>_te) of room temperature (RT), 100 °C, and 150 °C. As <em>T</em>_te increased, all the initial curves changed from brittle-like to ductile-like. Next, the films were subjected to storage at a temperature of 150 °C (<em>T</em>_st⁰) for 24, 168, and 500 h. With increasing storage time, the stiffness of the films at <em>T</em>_te = 150 °C increased, while their RT counterpart did not show significant changes. This <em>T</em>_te-dependent difference in mechanical property was likely caused by oxidation as revealed by Fourier transform infrared spectroscopy analysis, and consequently resulted in a difference in stress distribution between 150 °C and RT in an EMC-on-metal assembly, which was confirmed by finite element method stress simulation.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"166 ","pages":"Article 115605"},"PeriodicalIF":1.6,"publicationDate":"2025-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143372643","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Simulation-based FMEA for the reliability assessment of printed circuit boards","authors":"Hendrik Schmidt ,&nbsp;Markus Käß ,&nbsp;Roland Lichtinger ,&nbsp;Moritz Hülsebrock","doi":"10.1016/j.microrel.2025.115613","DOIUrl":"10.1016/j.microrel.2025.115613","url":null,"abstract":"<div><div>Simulation-based FMEA is presented as a method to estimate the reliability of printed circuit boards at the system level. A numerical simulation of relevant stress variables is combined with fatigue models and a probabilistic FMEA to determine probabilities for system level failure modes. Uncertainties of model parameters are estimated and included in the simulation to provide a comprehensive analysis of system level failure probabilities. A parametric reduced order model is used for the numerical simulation to efficiently perform the calculations with uncertain parameters. The simulation-based FMEA workflow is applied to a test printed circuit board excited by harmonic vibrations.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"166 ","pages":"Article 115613"},"PeriodicalIF":1.6,"publicationDate":"2025-02-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143208166","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Reliability analysis of the intricacies of interfacial trap charges in HD-VS-FeFinFET and its applicability as CMOS inverter","authors":"Kajal Verma ,&nbsp;Rishu Chaujar","doi":"10.1016/j.microrel.2025.115610","DOIUrl":"10.1016/j.microrel.2025.115610","url":null,"abstract":"<div><div>This paper investigates the impact of semiconductor-oxide interfacial trap charges (ITCs) on the performance of Si/SiGe strained hetero dielectric vertically stacked ferroelectric-based FinFET (HD-VS-FeFinFET), formed with the novel amalgamation of several advanced technologies. ITCs induced degradation is a major concern for device reliability, and this study examines the reliability of HD-VS-FeFinFET by analyzing: (1) temperature affectability on ITCs, (2) impact of varying ITC densities and polarities, and comparing the results with vertically stacked ferroelectric-based FinFET (VS-FeFinFET). Temperature affectability reveals that HD-VS-FeFinFET exhibits better reliability with less average variations against ITCs at all operating temperatures such as 10.65% in leakage current (I<span><math><msub><mrow></mrow><mrow><mi>o</mi><mi>f</mi><mi>f</mi></mrow></msub></math></span>) and 11.39% in output resistance (R<span><math><msub><mrow></mrow><mrow><mi>o</mi><mi>u</mi><mi>t</mi></mrow></msub></math></span>) at 300 K which further decreases to 8.13% in I<span><math><msub><mrow></mrow><mrow><mi>o</mi><mi>f</mi><mi>f</mi></mrow></msub></math></span> and 7.76% in R<span><math><msub><mrow></mrow><mrow><mi>o</mi><mi>u</mi><mi>t</mi></mrow></msub></math></span> at 400 K in contrast to huge variation shown by VS-FeFinFET like 82.05% in I<span><math><msub><mrow></mrow><mrow><mi>o</mi><mi>f</mi><mi>f</mi></mrow></msub></math></span> and 43.10% in R<span><math><msub><mrow></mrow><mrow><mi>o</mi><mi>u</mi><mi>t</mi></mrow></msub></math></span> at 300 K along with 59.35% in I<span><math><msub><mrow></mrow><mrow><mi>o</mi><mi>f</mi><mi>f</mi></mrow></msub></math></span> and 29.86% in R<span><math><msub><mrow></mrow><mrow><mi>o</mi><mi>u</mi><mi>t</mi></mrow></msub></math></span> at 400 K. Further, the analysis done at various ITCs densities and polarities reveals that, at higher donor trap charge density of 10¹³ cm⁻², the device performance alters significantly for VS-FeFinFET with degradation in I<span><math><msub><mrow></mrow><mrow><mi>o</mi><mi>f</mi><mi>f</mi></mrow></msub></math></span> by 552 times in comparison to HD-VS-FeFinFET which degrades only by 2.52 times, thus making it more reliable under varying environmental conditions. Lastly, HD-VS-FeFinFET based CMOS inverter shows improved immunity towards ITCs with negligible variations at all operating temperatures, thus with reliable circuit-level operation, HD-VS-FeFinFET proves itself an ideal choice for advanced logic circuits and low-power electronic applications in dynamic environments.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"166 ","pages":"Article 115610"},"PeriodicalIF":1.6,"publicationDate":"2025-02-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143208163","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Microstructure and mechanical evolution of sintered silver on Ni/Pd/Au and Ni/Au finished substrates","authors":"Yuchen Zhang,&nbsp;Liting Lin,&nbsp;Xin Li","doi":"10.1016/j.microrel.2025.115612","DOIUrl":"10.1016/j.microrel.2025.115612","url":null,"abstract":"<div><div>With the development of third-generation semiconductor materials, power devices are facing new challenges in high-temperature and high-power density packaging. Sintered silver, known for its high thermal conductivity, high electrical conductivity and high melting point, has become one of the most promising attachment materials. Meanwhile, gold-finished surface, with its excellent corrosion resistance and high stability characteristics, has become one of the most commonly used surface metallization in power devices. However, achieving high-strength bonding and ensuring high-temperature reliability in Ag-Au joints remains challenging due to severe unbalanced interdiffusion. Thus, it is crucial to investigate the performance and reliability, with a particular focus on the interconnect bonding mechanism, which requires further in-depth study.</div><div>In order to investigate the effect of the gold-finished surface on the Ag<img>Au interconnect mechanism, two Ag-Au interconnect joints are designed in this study based on the sintered silver pressureless interconnect process, using Ni/Au and Ni/Pd/Au finished copper substrates. The study found that the Pd layer promotes Au grain coarsening by comparing the connection strength and micro-interfacial morphology, resulting in an Au grain size four times larger than that of the Ni/Au plating. However, since the Pd/Au lattice mismatch is smaller than that of Ni/Au, Ag can diffuse through dislocations in the Ni/Pd/Au layer. The Pd layer increases the diffusion driving force by enhancing the concentration gradient, leading to a thicker and more continuous sintered dense layer. The oxidation of Ni results in delamination of the joints after a high-temperature aging test at 250 ℃, while the Pd layer can improve the reliability of the interconnect interface. Based on this phenomenon, a microstructure evolution model of Ag-Ni/Pd/Au interconnect joints is established to analyze the formation mechanism of the dense layer. Furthermore, the failure modes of interconnect joints between the two types of finished substrates and sintered silver were analyzed.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"166 ","pages":"Article 115612"},"PeriodicalIF":1.6,"publicationDate":"2025-02-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143208165","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Reliable modular designs under time-continuous input data","authors":"Salin Junsangsri,&nbsp;Fabrizio Lombardi","doi":"10.1016/j.microrel.2024.115582","DOIUrl":"10.1016/j.microrel.2024.115582","url":null,"abstract":"<div><div>This paper proposes new designs of double modular redundancy (DMR) when time-continuous data is provided as inputs. As this type of data tends slightly change over adjacent time periods, the proposed designs exploit this property by comparing consecutive outputs for reliable computing. The proposed designs are based on the difference between the two consecutive inputs/outputs, referred to as factor. These new designs are four one-factor and a single two-factor scheme. They overcome the negative feature of a previous design (referred to as self-voting) by which an uncontrollable output is encountered when input data is time-continuous and both primary inputs are not equal, i.e. in the presence of an error, the output remains at the same value prior to the occurrence of the error, so making it unsuitable for these types of applications. The proposed designs are evaluated in terms of the required decision hardware (to generate the output) and its accuracy using Cadence Genus Synthesis Solution on a 32 nm library; it is shown that the decision hardware of the two-factor scheme is more complex than for the one-factor schemes, yielding to a longer delay and higher power dissipation/area. Different data sets as well as a randomly generated data set are utilized in the evaluation. Simulation results show that the two-factor scheme provides the highest level of accuracy at the output as this is directly related to the complexity of the decision hardware:</div></div><div><h3>Index terms</h3><div>Redundancy, Double Modular Redundancy (DMR), Self-voting majority, Continuous data set, Reliable Computing</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"165 ","pages":"Article 115582"},"PeriodicalIF":1.6,"publicationDate":"2025-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143275807","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Systematic performance benchmarking of nanosheet and FinFET: An intrinsic self-heating perspective","authors":"Sunil Rathore ,&nbsp;Rajeewa Kumar Jaisawal ,&nbsp;Suneet Kumar Agnihotri ,&nbsp;Navneet Gandhi ,&nbsp;P.N. Kondekar ,&nbsp;Navjeet Bagga","doi":"10.1016/j.microrel.2025.115588","DOIUrl":"10.1016/j.microrel.2025.115588","url":null,"abstract":"<div><div>The device miniaturization and engineered structures of non-planar transistors with gate wrapping and channel stacking raise severe reliability concerns. One of the major issues in recent devices is the electrical-thermal interaction of the charge carriers at the confined geometrical active channel region, which causes a self-heating effect (SHE). Thus, systematic measures need to be investigated to standardize the benchmark of emerging devices. Thus, using well-calibrated TCAD models, we thoroughly studied the role of the ambient temperature and SHE in vertically stacked Nanosheet FET (NSFET) and multi-fin FinFET by varying the number of sheets/fins (active channels), while considering the equivalent effective area of both devices. The devices (i.e., NSFET and FinFET) are optimized and benchmarked using the observed figure of merits (FoMs), such as ON current, I_ON-I_OFF ratio, gate capacitance (C_gg), cut-off frequency (f_T), etc. Further, using mixed-mode simulations, the impact of SHE is investigated on an inverter performance followed by realizing the delay and oscillation frequency of the NSFET/FinFET-based three-stage ring oscillator to analyze the frequency compatibility of NSFETs and FinFETs with varying sheets/fins.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"165 ","pages":"Article 115588"},"PeriodicalIF":1.6,"publicationDate":"2025-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143275808","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Analyzing the electrical response of Au-GaAs Schottky diodes to proton irradiation at room temperature","authors":"Driss Saadaoui,&nbsp;Mustapha Elyaqouti,&nbsp;Imade Choulli,&nbsp;Souad Lidaighbi,&nbsp;El Hanafi Arjdal,&nbsp;Dris Ben Hmamou,&nbsp;Abdelfattah Elhammoudy,&nbsp;Ismail Abazine,&nbsp;Brahim Ydir,&nbsp;Khalid Assalaou","doi":"10.1016/j.microrel.2025.115593","DOIUrl":"10.1016/j.microrel.2025.115593","url":null,"abstract":"<div><div>This work investigates the electrical behavior of Schottky diodes fabricated by gold evaporation on n-type GaAs substrates. The substrates were cleaned using proton irradiation with a fluence of 10¹⁵ P/cm² and energy range of 0.75–3 MeV. Current-voltage (I-V) analysis revealed significant changes in the electrical properties under various irradiation conditions. Key findings show that the Schottky barrier height decreases as proton fluence increases at constant energy, while it increases with rising proton energy at constant fluence. Additionally, the ideality factor, greater than unity, varies systematically with proton energy. These results highlight complex interactions at the Semiconductor-Metal (SM) interface, likely due to defect generation from proton irradiation. <em>Re</em>-analysis of experimental data confirmed these trends and provided deeper insight into the defect generation process. This study contributes to understanding radiation effects on semiconductor devices, offering insights crucial for optimizing radiation-hardened electronics.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"165 ","pages":"Article 115593"},"PeriodicalIF":1.6,"publicationDate":"2025-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143275872","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}