Microelectronics Reliability最新文献

Facile polyol synthesis of thermally stable AgNi composite nanowires for flexible transparent heater applications 用于柔性透明加热器的热稳定AgNi复合纳米线的简单多元醇合成

IF 1.9 4区工程技术

Microelectronics Reliability Pub Date : 2026-04-01 Epub Date: 2026-02-11 DOI: 10.1016/j.microrel.2026.116054

Soomin Song

{"title":"Facile polyol synthesis of thermally stable AgNi composite nanowires for flexible transparent heater applications","authors":"Soomin Song","doi":"10.1016/j.microrel.2026.116054","DOIUrl":"10.1016/j.microrel.2026.116054","url":null,"abstract":"<div><div>Silver nanowires (Ag NWs) are considered promising alternatives to indium tin oxide (ITO) for flexible transparent electrodes because of their excellent conductivity and optical transmittance. However, their practical deployment remains limited by poor thermal stability and degradation through surface diffusion and oxidation at elevated temperatures. In this study, Ag<img>Ni composite nanowires were synthesized through a modified polyol process using two different nickel precursors to enhance the structural and thermal robustness of Ag NW networks. Ni(II) acetate increased the Ni content but suppressed anisotropic growth owing to strong ligand coordination, whereas Ni(NO₃)₂·6H₂O enabled uniform incorporation of Ni species into Ag nanowires, yielding thin, high-aspect-ratio structures with diameters of approximately 70 nm. The incorporated Ni acted as a diffusion barrier that effectively hindered Ag surface migration and grain coalescence, maintaining the one-dimensional morphology up to 300 °C, in stark contrast to pure Ag NWs which disintegrated above 200 °C. The resulting Ag<img>Ni composite films exhibited a high optical transmittance of 89.6% and a low sheet resistance of 20 Ω sq.<sup>−1</sup>, outperforming pure Ag NW films (85.9%, 35 Ω sq.<sup>−1</sup>). When implemented as flexible transparent heaters, the Ag<img>Ni films demonstrated rapid Joule heating to temperatures above 100 °C at 5 V, complete evaporation of water droplets within 3 min, and stable operation over repeated heating–cooling cycles. These results confirm that the incorporation of Ni significantly improves the electrical, optical, and thermal robustness of Ag NW networks. Overall, this work presents a facile and scalable chemical-solution route for producing thermally stable, optically transparent, and electrically conductive Ag<img>Ni nanowire films, offering strong potential for next-generation flexible electronics and transparent heating applications.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"179 ","pages":"Article 116054"},"PeriodicalIF":1.9,"publicationDate":"2026-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146175252","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Inductance and capacitance parasitic prediction thanks to data analysis applied to Si and SiC MOSFET wide frequency band characterization 基于数据分析的Si和SiC MOSFET宽频带特性电感和电容寄生预测

IF 1.9 4区工程技术

Microelectronics Reliability Pub Date : 2026-04-01 Epub Date: 2026-02-11 DOI: 10.1016/j.microrel.2026.116047

P.-E. Vidal , G. Viné , S. Baffreau , A. Gopishetti , T.L. Le

引用次数: 0

Thermo-mechanical reliability and scalability of copper-pillar solder-cap interconnects for micro-LEDs 微型led用铜柱焊帽互连的热机械可靠性和可扩展性

IF 1.9 4区工程技术

Microelectronics Reliability Pub Date : 2026-04-01 Epub Date: 2026-02-11 DOI: 10.1016/j.microrel.2026.116051

Junhyeock Kim , Ho-Jung Jeong , Dae-Myeong Geum , Yong Suk Oh , Min-Su Park , Joonhyub Kim , Daewoong Jung , Chang-Mo Kang

{"title":"Thermo-mechanical reliability and scalability of copper-pillar solder-cap interconnects for micro-LEDs","authors":"Junhyeock Kim , Ho-Jung Jeong , Dae-Myeong Geum , Yong Suk Oh , Min-Su Park , Joonhyub Kim , Daewoong Jung , Chang-Mo Kang","doi":"10.1016/j.microrel.2026.116051","DOIUrl":"10.1016/j.microrel.2026.116051","url":null,"abstract":"<div><div>Micro-LED display fabrication—for devices such as smartwatches and TVs—requires high-throughput mass-transfer and bonding processes to assemble vast numbers of micro-LED chips from a temporary substrate, known as the interposer, onto the large-area backplane panel. Currently, a key strategy for reducing the manufacturing cost of these technologies is to significantly increase the interposer area to reduce panel-level manufacturing time, and this approach has emerged as a major issue. However, as chip sizes continue to shrink, the risk of mechanical damage during bonding rises, placing limits on the expansion of the interposer area. To overcome these limitations, this study performed thermo-compression bonding and thermal cycling simulations to examine the thermo-mechanical behavior of solder joints and to determine the maximum achievable transfer area under various bonding material conditions. The results reveal that copper pillars play a critical role in relieving stress and suppressing internal solder cracking. However, a clear trade-off exists between solder-bump height and diameter: reducing stress tends to aggravate internal cracking, whereas mitigating cracking leads to higher stress. Indium solder exhibited significantly improved reliability during both bonding and post-assembly operations compared with Sn–3.0Ag–0.5Cu, and its low-temperature bonding characteristics enabled a substantially larger maximum transferable area. The findings of this study provide actionable design guidelines for realizing large-area mass transfer and robust interconnection structures for next-generation micro-LED packaging.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"179 ","pages":"Article 116051"},"PeriodicalIF":1.9,"publicationDate":"2026-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146175248","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Embedded PCB and DBC-integrated design of 650 V GaN power modules with enhanced thermal and electrical performance 650v GaN电源模块的嵌入式PCB和dbc集成设计，增强了热电性能

IF 1.9 4区工程技术

Microelectronics Reliability Pub Date : 2026-04-01 Epub Date: 2026-02-13 DOI: 10.1016/j.microrel.2026.116053

A. Yeong Choi , Jaejin Jeon , Jae Hyuk Lim , Sang Won Yoon

{"title":"Embedded PCB and DBC-integrated design of 650 V GaN power modules with enhanced thermal and electrical performance","authors":"A. Yeong Choi , Jaejin Jeon , Jae Hyuk Lim , Sang Won Yoon","doi":"10.1016/j.microrel.2026.116053","DOIUrl":"10.1016/j.microrel.2026.116053","url":null,"abstract":"<div><div>This study proposes and validates a stepwise structural design methodology to simultaneously enhance the electrical and thermal performance of 650 V gallium nitride (GaN) power modules. First, using a reference half-bridge module (DBC-based with an integrated decoupling capacitor), we shortened and widened the current path and improved current-distribution symmetry by optimizing the copper pattern and introducing an additional DC- terminal, thereby reducing loop inductance in stages. Next, we adopted embedded structures that eliminate wire bonds and exploit internal PCB copper planes and via networks. The single-sided cooled (SSC) embedded module achieved 4.86 nH (38% reduction compared to the reference model), whereas the double-sided cooled (DSC) embedded module, featuring parallel heat-conduction paths to the top and bottom surfaces and a vertically mounted decoupling capacitor, reduced inductance to 3.54 nH (55% reduction compared to the reference model). When the local decoupling capacitor was included in the commutation-loop model, the parasitic inductance dropped to 0.91 nH. In thermal analysis, the SSC peaked at 90.7 °C, while the DSC recorded 78.2<span><math><msup><mrow></mrow><mo>°</mo></msup><mi>C</mi></math></span>, about 17°<span><math><mi>C</mi></math></span> lower than the reference model (94.9<span><math><msup><mrow></mrow><mo>°</mo></msup><mi>C</mi></math></span>). The proposed SSC/DSC embedded modules simultaneously reduce parasitic inductance and thermal resistance, thereby improving stability and lifetime under high-frequency, high-power operation and providing practical guidance for next-generation commercial GaN power module designs.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"179 ","pages":"Article 116053"},"PeriodicalIF":1.9,"publicationDate":"2026-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146175250","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Characterization of the bulk moisture diffusion in epoxy-based potting compounds for IGBT semiconductor power modules IGBT半导体功率模块用环氧基灌封化合物中本体水分扩散的表征

IF 1.9 4区工程技术

Microelectronics Reliability Pub Date : 2026-04-01 Epub Date: 2026-02-12 DOI: 10.1016/j.microrel.2026.116057

Ariane Tomas , Loïc Théolier , Alexandrine Guédon-Gracia , Hélène Frémont , Pierre-Yves Pichon

引用次数: 0

Improvement in bond wire reliability by adjustments in bond wire microstructure via heat treatment 通过热处理调整焊丝显微组织，提高焊丝的可靠性

IF 1.9 4区工程技术

Microelectronics Reliability Pub Date : 2026-04-01 Epub Date: 2026-02-12 DOI: 10.1016/j.microrel.2026.116025

J. Seltsam , M. Sippel , M. Kuglstatter , R. Schmidt , P. Dreher , J. Franke , H.W. Höppel

{"title":"Improvement in bond wire reliability by adjustments in bond wire microstructure via heat treatment","authors":"J. Seltsam , M. Sippel , M. Kuglstatter , R. Schmidt , P. Dreher , J. Franke , H.W. Höppel","doi":"10.1016/j.microrel.2026.116025","DOIUrl":"10.1016/j.microrel.2026.116025","url":null,"abstract":"<div><div>Many research related to reliability of power electronic devices has been published to improve the lifetime of power modules. Especially the top side connection between the bond wires and the semiconductor chip of such devices is very prone to fail, often denoted as wire lift-off. This paper focuses how particular microstructures of the bond wires adjusted by different post wire-drawing heat treatments affect the lifetime of the bond connection and the related damage mechanisms. In order to evaluate and compare the grain structures, EBSD measurements of a wire-drawn and bonded microstructure were conducted and the influence of a subsequent heat treatment was analyzed. To evaluate the influence of heat treatments on the lifetime of bond wire connections, power cycling tests of wires either subjected to a heat treatment or without any additional heat-treatment were conducted. In all cases, the bonded wires revealed a gradient in grain size and texture within the wire. By an appropriate heat treatment at 150 °C for 120 h the lifetime can be improved significantly, while shorter or longer heat-treatment durations result in reduced lifetimes. For the latter case, it is argued that due to the recovery and recrystallization of the heat-treated wire the crack growth rate is reduced and therefore improving the lifetime.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"179 ","pages":"Article 116025"},"PeriodicalIF":1.9,"publicationDate":"2026-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146175333","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Extrapolation of the degradation on FinFET FPGA: Comparison between 20,000 h of measurement and model FinFET FPGA退化的外推：20,000 h测量与模型的比较

IF 1.9 4区工程技术

Microelectronics Reliability Pub Date : 2026-04-01 Epub Date: 2026-02-11 DOI: 10.1016/j.microrel.2026.116048

J. Sobas , F. Marc

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Thermal-optical coupled reliability for micro-LED projection systems: Mechanistic modeling and parametric analysis 微型led投影系统的热光耦合可靠性：机械建模和参数分析

IF 1.9 4区工程技术

Microelectronics Reliability Pub Date : 2026-04-01 Epub Date: 2026-02-13 DOI: 10.1016/j.microrel.2026.116044

Suli Wang

{"title":"Thermal-optical coupled reliability for micro-LED projection systems: Mechanistic modeling and parametric analysis","authors":"Suli Wang","doi":"10.1016/j.microrel.2026.116044","DOIUrl":"10.1016/j.microrel.2026.116044","url":null,"abstract":"<div><div>μLED projection technology has intensive demands on thermal management with direct implications on optical performance and reliability. In this work, an integrated thermal-optical reliability model incorporating device-level quantum well sensitivity to temperature, module-level packaging resistance to heat, and system-level dynamics of heat removal has been proposed. A multiscale comparative analysis framework was established to quantify the individual and synergistic contributions of device architecture, packaging materials, and thermal management strategies on system-level performance. Comparative analysis between baseline and advanced configurations reveals that integrated multi-level thermal management can reduce operating temperature by 15 °C (reduced from 85 °C to 70 °C), while the luminescence efficiency can be improved from 18% to 22%. Accelerated aging tests confirm that there are substantial reliabilities enhanced with 90% vs 70% lumen maintenance and 35% MTTF increase after 1000 h illumination. A 5–8% error tolerance was realized by applying the proposed thermal-optical coupling model to capture the accuracy of temperature distribution, optical efficiency, and degradation process.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"179 ","pages":"Article 116044"},"PeriodicalIF":1.9,"publicationDate":"2026-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146175247","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

In-situ TEM investigation of thermomechanical fatigue of thick copper metallizations 厚铜金属化层热机械疲劳的原位透射电镜研究

IF 1.9 4区工程技术

Microelectronics Reliability Pub Date : 2026-04-01 Epub Date: 2026-02-11 DOI: 10.1016/j.microrel.2026.116050

L. Karanja , S. Moser , M. Reisinger , M. Legros

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Influence of cooling conditions on the estimated power cycling lifetime of a large-area substrate solder joint in power modules 冷却条件对功率模块大面积基板焊点估计功率循环寿命的影响

IF 1.9 4区工程技术

Microelectronics Reliability Pub Date : 2026-04-01 Epub Date: 2026-02-13 DOI: 10.1016/j.microrel.2026.116055

N. Zöllner , O. Schilling , David Übelacker

{"title":"Influence of cooling conditions on the estimated power cycling lifetime of a large-area substrate solder joint in power modules","authors":"N. Zöllner , O. Schilling , David Übelacker","doi":"10.1016/j.microrel.2026.116055","DOIUrl":"10.1016/j.microrel.2026.116055","url":null,"abstract":"<div><div>The efficiency of wind power systems is linked to accurate lifetime modelling of the power modules used. Typical power-cycling lifetime models depend on junction temperatures, which might lead to inaccuracies in modules that are limited by substrate solder degradation during power cycling, especially if the cooling conditions change. This influence is examined in this publication. For this purpose, a lifetime model based on substrate solder temperatures is derived by substituting junction temperatures in an existing junction-based model. Then, the substrate solder and junction temperatures are calculated for three different cooling conditions from the mission profiles. Lifetimes are calculated using each lifetime model and the results are compared. It is observed that the lifetime estimates derived with the substrate solder model and junction-based model differ. Furthermore, the lifetimes estimated with substrate solder temperatures develop differently with respect to the cooling condition compared to those obtained with junction temperatures. It is shown using multiple examples that in these cases higher loads occur in the substrate solder under weaker cooling conditions compared to the junction.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"179 ","pages":"Article 116055"},"PeriodicalIF":1.9,"publicationDate":"2026-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146175251","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0