Microelectronics Reliability最新文献

{"title":"Series AC arc fault detection method based on spectrogram and deep residual network","authors":"Wenxin Dai,&nbsp;Xue Zhou,&nbsp;Zhigang Sun,&nbsp;Guofu Zhai","doi":"10.1016/j.microrel.2025.115756","DOIUrl":"10.1016/j.microrel.2025.115756","url":null,"abstract":"<div><div>The extended and excessive use of power equipment can hasten the aging of circuit cables, resulting in arc faults. The generation of arc fault will not only affect the performance of power equipment, but also bring about safety hazards. Therefore, it is necessary to detect arcing in circuits. This paper presents a framework for detecting series arc faults based on spectrogram and deep residual network. The problem of current signal detection can be converted into the problem of image recognition by this framework. In this framework, the current signal is converted into a spectrogram, which enables the characterisation of the current signal from a multi-domain perspective. Then, a deep residual network model is used to recognize the spectrogram and determine the type of arc fault. Finally, the current data is used to demonstrate the effectiveness and accuracy of the proposed method. The results show that the proposed method is able to achieve accurate arc fault detection with an accuracy of 97.50 %.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"170 ","pages":"Article 115756"},"PeriodicalIF":1.6,"publicationDate":"2025-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143874456","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Identification of mechanical responses of interconnect structures based on Bayesian regularization under board-level drop impact","authors":"Xu Long,&nbsp;Yuntao Hu","doi":"10.1016/j.microrel.2025.115755","DOIUrl":"10.1016/j.microrel.2025.115755","url":null,"abstract":"<div><div>To address the challenge of directly measuring the mechanical response of critical interconnect structures in board-level packaging structures, which is complicated by the inherent complexity of electronic components, a load identification methodology is first proposed in this study. This methodology is established based on finite element (FE) analysis to accurately identify the critical failure points in the key interconnect structures of board-level packaging. Furthermore, an indirect measurement method based on Bayesian regularization is proposed for load identification to comprehensively capture the stress conditions of critical structural components in the board-level packaging structures subjected to drop impact. During the impact process, the solder joints at the corners beneath the edge areas experience the maximum stress and strain, making them more prone to failure. The normal stress in the Z-direction (<em>S</em>₃₃) perpendicular to the printed circuit board (PCB), which is the maximum stress component, is the primary cause of damage to the interconnect structure. To address the ill-posed problem in load identification, such as the instability due to the inversion of ill-conditioned matrices and sensitivity to noise, an improved Bayesian method using augmented Tikhonov regularization is introduced. The proposed method incorporates a wavelet thresholding technique to solve the problem of poor load identification accuracy under high noise levels. It adaptively determines the optimal regularization parameters during the identification process and effectively removes the noise impact on load recognition. The established response identification methodology is capable of achieving relatively small relative error (<em>RE</em>) and high correlation coefficients when identifying the mechanical response of critical interconnections in board-level packaging structures. Furthermore, both the smoothness of the response curve and the accuracy of peak value identification are ensured. The effect of varying numbers of input points on the identification results is also considered. The results show that more input points provide more effective constraints, thereby improving recognition accuracy. Under dual-input conditions, the <em>RE</em> is controlled below 8 % at medium to low noise levels, and remains below 10 % at high noise levels, providing an effective approach for effective stress analysis during the drop impact process.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"170 ","pages":"Article 115755"},"PeriodicalIF":1.6,"publicationDate":"2025-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143874455","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Preliminary 2D elastoplastic modeling of gate cracking in SiC MOSFETs under short-circuit conditions across a wide temperature-range using rankine's damage energetic approach","authors":"Mustafa Shqair,&nbsp;Emmanuel Sarraute,&nbsp;Frédéric Richardeau","doi":"10.1016/j.microrel.2025.115757","DOIUrl":"10.1016/j.microrel.2025.115757","url":null,"abstract":"<div><div>For the first time in SiC MOSFETs, structural and physical modeling of the Intermediate-Layer-Dielectric (ILD) cracking in a planar gate under short-pulse short-circuit conditions is proposed. This approach employs an energy-based Rankine damage model, relying on the SiO₂ mechanical properties. The Rankine model has been effectively integrated into a comprehensive 2D electrothermal-metallurgical and elastoplastic-mechanical model across a wide range of temperatures. Initial results enable the extraction of crack penetration depth from a single pulse, paving the way for estimating the average number of critical cycles leading to a potentially complete destructive ILD fracture.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"170 ","pages":"Article 115757"},"PeriodicalIF":1.6,"publicationDate":"2025-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143870279","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Impact of IGBT emitter pad design and front-side aging on switching stability and temperature distribution","authors":"C. Bäumler,&nbsp;T. Basler","doi":"10.1016/j.microrel.2025.115738","DOIUrl":"10.1016/j.microrel.2025.115738","url":null,"abstract":"<div><div>This work offers a comprehensive study on temperature determination and development of IGBTs via temperature-sensitive parameters (TSEPs) during repetitive switching events. The obtained information is discussed and judged with respect to accuracy for different device technologies. This evaluation is extended by the aspect of artificial front-side aging for different emitter-pad designs. For two different designs investigated, no decreased switching robustness could be verified, even beyond the AQG 324 [1] lifetime border, which is defined by a certain forward voltage drop increase.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"170 ","pages":"Article 115738"},"PeriodicalIF":1.6,"publicationDate":"2025-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143874454","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Reliability study and optimization of TSV interconnections with silicon interposer under random vibration","authors":"Jinjie Xu ,&nbsp;Shenglin Yu ,&nbsp;Yizhou Chen","doi":"10.1016/j.microrel.2025.115753","DOIUrl":"10.1016/j.microrel.2025.115753","url":null,"abstract":"<div><div>As aerospace electronic devices continue to develop in the direction of miniaturization and high integration, 2.5D packaging technology has become a key breakthrough in aerospace chip research and development by virtue of its unique advantages. However, there is a lack of sufficient research on the reliability of 2.5D packaging in the severe vibration environment of the launch phase of the current space launch vehicle. Based on the finite element method, the reliability of the through silicon via (TSV) interconnect structure in the silicon interposer of 2.5D packaging under severe vibration environments is investigated, and the maximum stress of the micro-bumps, TSV-Cu, and C4 bumps at different locations are analyzed. It is found that the maximum stress of the micro-bumps and C4 bumps gradually decrease from the outside to the inside, and that the maximum stress of the TSV-Cu first decrease and then slightly increase. The fatigue life prediction of each part of the interconnect structure reveals that the micro-bumps are most likely to fail due to fatigue. To address this issue, a structural optimization design is carried out by using orthogonal tests with the micro-bump diameter, the micro-bump height, the thickness of the insulating layer, and the material of the bumps as the test factors for the micro-bumps’ maximum stress. The micro-bumps’ maximum stress are reduced by 36.3% after the optimization.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"170 ","pages":"Article 115753"},"PeriodicalIF":1.6,"publicationDate":"2025-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143870278","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Study on gate oxide reliability of SiC power MOSFETs under 300 MeV proton irradiation","authors":"Jingyi Xu ,&nbsp;Ying Wei ,&nbsp;Dan Zhang ,&nbsp;Xuefeng Yu ,&nbsp;Xiaowen Liang ,&nbsp;Qi Guo ,&nbsp;Yutang Xiang ,&nbsp;Jie Feng","doi":"10.1016/j.microrel.2025.115750","DOIUrl":"10.1016/j.microrel.2025.115750","url":null,"abstract":"<div><div>Although operating at a lower drain bias voltage reduces the risk of Single-Event-Burnout (SEB), whether SiC power MOSFET can be reliably applied under low-voltage irradiation conditions remains to be investigated. This study evaluated the gate oxide reliability of SiC power MOSFETs irradiated with a 300 MeV proton beam. Different drain bias levels and total fluence values were selected in the irradiation experiment. The critical voltage for SEB occurrence in the selected device samples was obtained. For devices that did not experience SEB after irradiation, their electrical characteristics remained largely unchanged; however, significant degradation in gate oxide reliability was observed during Time-Dependent Dielectric Breakdown (TDDB) tests, suggesting potential long-term reliability concerns. Furthermore, degradation of gate oxide reliability requires the irradiation bias to exceed a certain threshold, and the degradation severity is positively correlated with irradiation fluence, demonstrating a cumulative radiation damage effect. These findings provide critical insights for ensuring the reliable application of SiC power devices in aerospace systems.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"169 ","pages":"Article 115750"},"PeriodicalIF":1.6,"publicationDate":"2025-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143868297","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Failure evolution analysis of SiC power modules in electric-thermal-mechanical multi-physical fields","authors":"Yifeng Chen ,&nbsp;Xin Lan ,&nbsp;Lezhou Li ,&nbsp;Xin Li ,&nbsp;Ziyang Zhang ,&nbsp;Gongming Xin","doi":"10.1016/j.microrel.2025.115751","DOIUrl":"10.1016/j.microrel.2025.115751","url":null,"abstract":"<div><div>The reliability of SiC power devices is affected by the coupling effects of electric-thermal-mechanical multi-physical fields, and its mechanism is still not totally revealed. In this study, a coupled electric-thermal-mechanical multi-physical model is proposed for a SiC power module, and the effects of die position, power loss of bonding wires, as well as bonding position on reliability are investigated. Additionally, a failure evolution model is further developed based on the multi-physical model. The results indicate that delamination around the corner of the solder layer significantly affects the temperature distribution of the bonding wires. The farther the bonding point is away from the hot spot of the die, the greater the temperature rise of the bonding wire, and vice versa. During the failure evolution, the temperature of the damaged bonding wires first increases with slight damage and then decreases with serious damage accumulation. The temperature of the parallel bonding wires increases significantly once the damaged wire is broken.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"169 ","pages":"Article 115751"},"PeriodicalIF":1.6,"publicationDate":"2025-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143864765","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Micro-Raman and SEM analyses of failed GaN HEMT multilayer architecture","authors":"Enza Fazio ,&nbsp;Cettina Bottari ,&nbsp;Santi Alessandrino ,&nbsp;Beatrice Carbone ,&nbsp;Salvatore Adamo ,&nbsp;Alfio Russo ,&nbsp;Mariangela Latino ,&nbsp;Sabrina Conoci ,&nbsp;Fortunato Neri ,&nbsp;Ammar Tariq ,&nbsp;Carmelo Corsaro","doi":"10.1016/j.microrel.2025.115754","DOIUrl":"10.1016/j.microrel.2025.115754","url":null,"abstract":"<div><div>The challenge of accurately diagnosing and understanding failure mechanisms in GaN power devices under high-stress conditions has been a persistent issue, particularly with respect to catastrophic failures difficult to detect through conventional electrical measurements. This study focuses on p-GaN-based high-electron-mobility transistors (HEMT) technology device, subjected to high-stress conditions, to analyze the entire device architecture and mainly the structure of the gate–source bridge. SEM analyses reveal significant structural damage, including cracks and voids, particularly near the metal interconnection lines and GaN buffer layers, whereas Raman spectroscopy highlights distortions in the wurtzite GaN crystal structure. By integrating the spectroscopic and morphological results, useful insights into the GaN device layers interested by the failure mechanisms are provided. These data are useful to optimize the multi-layer stacked structures and then to enhance the GaN HEMTs main characteristics.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"169 ","pages":"Article 115754"},"PeriodicalIF":1.6,"publicationDate":"2025-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143864764","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Solder mask as a reliable insulation layer on printed circuit boards–different layouts and materials under humidity and high voltage","authors":"M. Vogt ,&nbsp;A. Brunko ,&nbsp;M.R. Meier ,&nbsp;H. Schweigart ,&nbsp;L. Henneken ,&nbsp;M. Schleicher ,&nbsp;D. Schucht ,&nbsp;N. Kaminski","doi":"10.1016/j.microrel.2025.115743","DOIUrl":"10.1016/j.microrel.2025.115743","url":null,"abstract":"<div><div>After decades of improvement, the reliability of Printed Circuit Boards (PCB) is well known and standardized. However, the standards are based on outdated material properties and old experiments and thus, they contain a large safety margin, when modern insulation materials are applied. This work focuses on the insulation properties and the reliability of solder mask under high humidity and high voltages. It has been demonstrated that significantly more robust systems can be achieved than the standards specify. This leads the way for further volume reductions.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"169 ","pages":"Article 115743"},"PeriodicalIF":1.6,"publicationDate":"2025-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143856010","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Improved device structure for electrical safe operating area in SiC 1700-V VDMOSFET","authors":"Chao-Yang Ke,&nbsp;Ming-Dou Ker","doi":"10.1016/j.microrel.2025.115749","DOIUrl":"10.1016/j.microrel.2025.115749","url":null,"abstract":"<div><div>This study provides significant advancements in SiC power device technology, improving the balance between high voltage, current handling, and reliability. The improved layout design of a SiC 1700-V vertical double-implanted MOSFET (VDMOSFET) with enhancing the characteristics of electrical safe operating (eSOA) and unclamped inductive switching (UIS) was carefully verified in this study. The experimental results show that the improved structure with an extended P+ region has a wider eSOA boundary. Furthermore, the improved structure can also tolerate higher power supply <em>V</em>_<em>CC</em>, higher switching current, and higher overshooting <em>V</em>_<em>DS</em> voltage. While the improved design sacrifices some DC performance, such as a slight increase in threshold voltage and on-resistance, it significantly boosts dynamic-switching reliability. All of the benefits can be attributed to the lower base resistance achieved by the layout design of an extended P+ region. Moreover, the experimental results from the double pulse test demonstrate that the proposed method did not compromise any switching speed or switching loss. Therefore, the improved structure without increasing manufacturing costs is recommended to enhance the robustness of dynamic switching in SiC 1700-V VDMOSFET.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"169 ","pages":"Article 115749"},"PeriodicalIF":1.6,"publicationDate":"2025-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143844254","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}