Microelectronics Reliability最新文献

{"title":"Signal integrity and heat transfer performance of through-boron nitride via","authors":"","doi":"10.1016/j.microrel.2024.115531","DOIUrl":"10.1016/j.microrel.2024.115531","url":null,"abstract":"<div><div>Silicon interposer is widely used in 2.5D integrated packages due to its good dielectric properties and mature process. However, silicon interposer is not suitable for high-power devices and radio frequency devices, suffering from poor signal integrity and low thermal conduction efficiency. In this work, c-BN is used as an interposer to provide a solution for electrical signal interference and thermal aggregation in the devices. In addition, PTFE, glass and h-BN, w-BN have also been studied for comparison. The finite element simulation results show that the return loss of the TBV (c) is 3.3 dB lower than that of the TSV at 40 GHz. The insertion loss of TBV (c) is 0.12 dB higher than that of TSV. The c-BN interposer performs better than the silicon interposer in terms of signal integrity, with a similar performance to the glass interposer. The accuracy of the finite element simulation is verified by the RLGC analytical model. The return loss of TBV (c) decreases due to the decrease in the interposer thickness, the increase in spacing between the Cu pillars or the increase in radius of the Cu pillars. Owing to the high thermal conductivity of c-BN, the horizontal and the vertical equivalent thermal conductivity of TBV (c) are approximately 8 times than those of TSV. The heat dissipation performance of TBV (c) is also better than that of TSV. The TBV (c) interposer shows advantages in both electrical and heat transfer aspects, which provide new perspectives for device development in 2.5D integrated packages.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":null,"pages":null},"PeriodicalIF":1.6,"publicationDate":"2024-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142587129","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Modeling of HCI effect in nFinFET for circuit reliability simulation","authors":"","doi":"10.1016/j.microrel.2024.115543","DOIUrl":"10.1016/j.microrel.2024.115543","url":null,"abstract":"<div><div>This paper proposes an equivalent circuit model for simulating the Hot Carrier Injection (HCI) effect. This model is developed based on the N-FinFET in the 12 nm Process Design Kit (PDK) and incorporates arithmetic units and electrical components from the Electronic Design Automatic (EDA) software. Input parameters can be freely modified by the user, such as stress time, ambient temperature, gate length, gate width and process corner. The model also considers the influence of the voltage at each end of the transistor on the HCI effect. The model can be accessed in the EDA tool just like a normal transistor and can be used to evaluate the HCI effect on circuits without modifying the SPICE model. The accuracy and applicability of this model has been verified by comparing it with measured results from other published literature.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":null,"pages":null},"PeriodicalIF":1.6,"publicationDate":"2024-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142587128","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A comprehensive investigation of total ionizing dose effects on bulk FinFETs through TCAD simulation","authors":"","doi":"10.1016/j.microrel.2024.115534","DOIUrl":"10.1016/j.microrel.2024.115534","url":null,"abstract":"<div><div>This study investigates the total-ionizing-dose (TID) effect on bulk FinFETs under ON-state irradiation bias, aiming to analyze the cause and physical mechanism of irradiation enhancement effects. Utilizing technology computer-aided design (TCAD), for the first time, we find that parasitic transistors located at the apex of the shallow trench isolation (STI) oxide significantly contribute to the subthreshold degradation of the device, leading to a notable increase in off-state leakage current. Furthermore, under identical irradiation bias conditions, narrower-fin and shorter-channel devices exhibit a more pronounced increase in off-state leakage current. This escalation is attributed to an increased amount of trapped charge in the STI oxide and the elevated electrostatic potential of the punch-through stop (PTS) layer, respectively. Additionally, higher drain voltage reduces the threshold voltage of the STI parasitic transistors, resulting in an increased off-state current as drain voltage rises. In summary, investigating the TID effect of bulk FinFETs under ON-bias is crucial, as it can provide theoretical support for reinforcing nanostructured devices against irradiation-induced degradation.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":null,"pages":null},"PeriodicalIF":1.6,"publicationDate":"2024-11-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142577875","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Solder joints stress analysis and optimization of chip component under shear and tensile load based on orthogonal experimental design and gray correlation analysis","authors":"","doi":"10.1016/j.microrel.2024.115529","DOIUrl":"10.1016/j.microrel.2024.115529","url":null,"abstract":"<div><div>The solder joint finite element analysis model of the 0201 chip component was established, by carrying out the shear loading and tensile loading finite element analysis respectively, the stress distribution pattern of the solder joint shear stress and tension stress were obtained. A solder joint stress measurement platform for the chip component was built, the solder joint stress measurement for the chip component under shear load was completed, and the accuracy of the simulation analysis results was verified. Selecting the solder joint volume, pad gap height, and pad length as design variables, and taking the maximum shear and tensile stress of the solder joint as the target, 16 groups of different parameter level combinations were designed by orthogonal test method, and combining with gray correlation analysis method, the bi-objective optimization design of shear and tensile stress of chip component solder joints was carried out—the optimal level combination of shear and tensile stress was obtained and verified by simulation. The results show that the influence ranking of maximum shear stress and tensile stress in solder joints of chip component are both pad gap height, pad length, and solder joint volume. The optimal parameter level combination is the solder joint volume of 0.0147mm<span><math><msup><mrow></mrow><mrow><mn>2</mn></mrow></msup></math></span>, pad gap height of 0.05 mm, pad length of 0.35 mm, the maximum shear stress and the maximum tensile stress of the chip component solder joints increase by 44% and 23% respectively after the optimization, enhancing the shear strength and tensile strength of the solder joints in chip component simultaneously.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":null,"pages":null},"PeriodicalIF":1.6,"publicationDate":"2024-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142572879","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Effects of different air gaps of underfill encapsulant on multi-stack printed circuit board","authors":"","doi":"10.1016/j.microrel.2024.115533","DOIUrl":"10.1016/j.microrel.2024.115533","url":null,"abstract":"<div><div>This paper studies the effect of different air gaps on multi-stack printed circuit board (PCB) using finite volume method (FVM). Air gaps of 150 mm² and 450 mm² were introduced to investigate their influence on flow parameters such as filling time, pressure distribution, and void formation during the capillary underfill encapsulation process. It was found that increasing the air gap size improved the filling time by 10 %, though it also doubled the pressure, which helps reduce void formation but requires careful control to prevent encapsulant overflow. Throughout the study, an L-type dispensing method was applied on a perimeter type multi-stack BGA with wall type barrier added on the sides of the multi-stack PCB to prevent encapsulant. This new wall type barrier henceforth requires comprehensive study on the size of the air gaps to ensure crucial flow parameters such as void formation, filling time, pressure distribution and flow front pattern are optimized. Two air gap sizes given as 150 mm² and 450 mm² are used in this study. Moreover, the fluid flow patterns from both studies are investigated to determine the problem of racing effect and void formation. Based on the findings, it was found that 10 % improvement in the filling time can be made by using a bigger air gap of 450 mm². However, with bigger air gap, the pressure increases two-fold which can be good in reducing the void formation though the trade-off can be on the risk of excessive overflow of encapsulant.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":null,"pages":null},"PeriodicalIF":1.6,"publicationDate":"2024-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142572880","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"The evolution of defects in n-type 4H-SiC Schottky barrier diode irradiated with swift heavy ion using the Deep Level Transient Spectroscopy","authors":"","doi":"10.1016/j.microrel.2024.115532","DOIUrl":"10.1016/j.microrel.2024.115532","url":null,"abstract":"<div><div>The evolution of deep levels in n-type 4H-SiC Schottky barrier diodes (SBDs) irradiated with 9.5 MeV/u ²⁰⁹Bi ions at room temperature was investigated by Deep Level Transient Spectroscopy (DLTS). DLTS scans from 40 K to 800 K indicated the presence of <em>EN</em>_<em>1</em><em>, EH</em>_{<em>Ti(h)</em>} (<em>E</em>_<em>C</em>-0.13(1) eV), <em>EH</em>_<em>1</em>(<em>E</em>_<em>C</em>-0.48(2) eV), <em>EH</em>_<em>4</em> (<em>E</em>_<em>C</em>-0.97(3)eV), and <em>EH</em>_<em>6/7</em> (<em>E</em>_<em>C</em><em>-</em>1.60(1) eV) defects levels within the energy range from 0.12 to 1.6 eV below the conduction band edge (<em>E</em>_<em>C</em>). The DLTS results for the 4H-SiC SBD samples before and after irradiation clearly demonstrated that swift heavy ion (SHI) irradiation induced the evolution of deep level defects or defect states in 4H-SiC SBD device. Notably, at a fluence of 1 × 10¹¹ ions/cm², the ion-induced deep level defects or defect states exhibited significant recovery due to the cumulative effect of heat, leading to SiC re-crystallization.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":null,"pages":null},"PeriodicalIF":1.6,"publicationDate":"2024-10-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142553762","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"The variation in Anand model parameters – How does that affect the bond's response? A comparative study considering sintered Ag bonds","authors":"","doi":"10.1016/j.microrel.2024.115528","DOIUrl":"10.1016/j.microrel.2024.115528","url":null,"abstract":"<div><div>Finite element analysis (FEA) is a widely used technique for simulating the thermally induced mechanical behavior of die bonding materials in electronics. The Anand unified viscoplasticity model is commonly employed to simulate the mechanical responses of such interconnections. This model comprises nine parameters, the individual effects of which are not fully understood in the literature. This paper aims to investigate the impact of each Anand parameter on the mechanical response of sintered silver (Ag) bonds through extensive finite element simulations. Various Anand models for sintered Ag, sourced from literature, are utilized to create a systematic study matrix for each parameter. These material coefficients are then incorporated into thermal and thermomechanical simulations to induce inelastic deformations in the sintered Ag bonds. The bonding layer response is analyzed in terms of stress-strain relationships, inelastic strains, and inelastic strain energy density. The results indicated that certain Anand parameters could cause the bond response to shift towards brittle behavior, while others could result in a more ductile behavior. Using statistical factorial analysis, it is found that the significance of each parameter varied greatly, from negligible to highly significant. The findings of this study are valuable for understanding the behavior of various bonds configurations and their expected thermal fatigue performance based on their Anand creep constants. Additionally, this paper lays the groundwork for understanding the meaning of Anand constants and their influence on the mechanical response of any bond material which is not discussed in literature yet.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":null,"pages":null},"PeriodicalIF":1.6,"publicationDate":"2024-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142536161","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Finite element analysis of 2.5D packaging processes based on multi-physics field coupling for predicting the reliability of IC components","authors":"","doi":"10.1016/j.microrel.2024.115530","DOIUrl":"10.1016/j.microrel.2024.115530","url":null,"abstract":"<div><div>The 2.5D packaging technology is a high–performance method for electronic packaging. This study addresses the reliability issues of 2.5D packaging during the manufacturing process. A multi–physics field coupling Finite Element Method (FEM) has been developed, combined with sub–modeling techniques, to investigate the curing of underfill adhesive, the curing of Epoxy Molding Compound (EMC), and the reflow soldering between the interposer and substrate in a 2.5D packaging entity during various manufacturing procedures. The focus is on the thermo–mechanical–chemical behavior of viscoelastic components within the packaging structure, as well as the viscoplastic characteristics of the micro solder balls and microbumps. A systematic analysis is conducted on the warpage deformation and stress distribution of the 2.5D packaging at crucial time points. The results demonstrate that after curing, the overall warpage of the packaging exhibits a ‘concave’ warpage profile. Additionally, as the thickness of the EMC above the chip increases, the warpage value of the packaging also increases. The warpage value defined by linear elasticity is larger than that defined by viscoelasticity. The maximum Von Mises stress value in the key areas of the submodel is greater than the maximum Von Mises stress value in the corresponding key areas of the global model. After reflow soldering, the stress concentration in the micro solder balls occurs at the edge of the micro solder ball array. The maximum stress values for each component of the packaging are observed in the interface areas between the components. Packaging components that undergo the curing process have notably higher warpage and Von Mises stress values than those that do not undergo the curing process. The simulation method established in this study can accurately predict the warpage deformation and stress distribution state of 2.5D packaging, providing significant engineering application value for process optimization and reliability enhancement of 2.5D packaging in the production process.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":null,"pages":null},"PeriodicalIF":1.6,"publicationDate":"2024-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142536160","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Research on the multi-physical field coupling modelling of IGBT package module and the effect of different structure failure interaction","authors":"","doi":"10.1016/j.microrel.2024.115527","DOIUrl":"10.1016/j.microrel.2024.115527","url":null,"abstract":"<div><div>As the key package structure of insulated gate bipolar transistor (IGBT), the bond wire and solder layer are susceptible to failure due to alternating thermal stress, which can seriously change the operating characteristics of the package structure. In this paper, an electrical-thermal-mechanical multi-physical field coupling simulation model of IGBT including the fine bond wire and solder layer structure is constructed, whose equivalence and accuracy are verified by experiments and characteristic curves. Based on the constructed healthy model, the simulation results find that the fourth bond wire at the center location shows the highest temperature of 38.7 °C and the maximum mechanical stress of 55.5 MPa. Subsequently, the researches on single-structure failure and dual-structure simultaneous failure are carried out. The results show that bond wire failure only significantly affects its own operating characteristics, while solder layer failure affects itself and bond wire simultaneously. Moreover, the temperature rise due to the bond wire failure is more significant with an 86.8 % increase, while the mechanical stress change due to the solder layer failure is larger with a 178.2 % increase. The research in this paper can guide the reliability improvement of IGBT and the optimization of IGBT package structure.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":null,"pages":null},"PeriodicalIF":1.6,"publicationDate":"2024-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142535285","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Investigation of thermal efficiency of recessed Γ gate over Γ gate, T gate and rectangular gate AlGaN/GaN HEMT on BGO substrate","authors":"","doi":"10.1016/j.microrel.2024.115522","DOIUrl":"10.1016/j.microrel.2024.115522","url":null,"abstract":"<div><div>High electron mobility transistors (HEMTs) based on a wider bandgap AlGaN channel prove more efficient for high-voltage operation. The significant advantages of AlGaN channel HEMTs include a high critical electric field and higher saturation velocity. These characteristics contribute substantially to expanding the operating regime of power electronics, making them more suitable for applications requiring high voltage. This research work introduces a novel structure for a HEMT based on AlGaN/GaN with a recessed Gamma (Γ)-gate. The proposed HEMTs are composed of a 30 nm supply/barrier layer and an 18 nm channel layer, constructed on a Beta Gallium Oxide (BGO) substrate. Additionally, a delta-doped layer is incorporated to enhance device characteristics. The Direct Current (DC) features of the introduced scheme are compared with those of Γ-gate, rectangular and T-gate configurations, and analyzed using Silvaco TCAD software under various considerations. Key parameters including threshold voltage and transconductance are extracted from the DC characteristics. The proposed device provides a comparable cut-off frequency of 998 GHz for 20 nm gate length. Finally, the thermal efficiency of the introduced scheme, utilizing lateral lattice thermal conductivity, results in peak temperatures of 398.2 K, demonstrating superior performance compared to existing gate structures. The optimized performance of the device is assessed against existing devices, demonstrating its superiority among the compared schemes.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":null,"pages":null},"PeriodicalIF":1.6,"publicationDate":"2024-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142535284","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}