Microelectronics Reliability最新文献

{"title":"Performance and reliability analysis of redistribution layers under interfacial crack","authors":"Vandana Kumari,&nbsp;Shivangi Chandrakar,&nbsp;Kamal Solanki,&nbsp;Manoj Kumar Majumder,&nbsp;Senior Member, IEEE","doi":"10.1016/j.microrel.2025.115728","DOIUrl":"10.1016/j.microrel.2025.115728","url":null,"abstract":"<div><div>The growing demand for high-density and high-performance semiconductor devices has accelerated the adoption of three-dimensional (3D) integration technologies, where redistribution Layer (RDL) structures play a critical role in signal routing and interconnect reliability. However, as the technology advances, it imposes significant stress on the RDL structure that can compromise its mechanical integrity and lead to cracks formation. Consequently, the likelihood of crack formation within these structures increases, and neglecting these issues can lead to severe problems, including reduced device performance and even permanent damage to the device. To address these confronting challenges, the study proposes an analytical modeling to analyze the influence of the RDL structure, considering interfacial cracks in both heating and cooling conditions. In this context, the result reveals a notable improvement in the crosstalk delay, with a reduction of 22.29 % observed when the minimum crack width of 0.18 μm under heating conditions approached the defect-free condition. A thorough validation of the analytical results demonstrates an excellent agreement with the electromagnetic (EM) result, for a negligible deviation of only 3.4 % observed in the scattering parameter. This close correspondence between the simulated and quantitative results lends solid support for the accuracy and reliability of the research findings. Additionally, the analysis highlighted that the crack under the cooling condition is significantly more susceptible to power delay product (PDP) than heating conditions, with a vulnerability of 7.19 % higher at a crack width of 0.18 μm. These findings provide valuable insight into the effects of interfacial cracks on the <em>via</em> performance and offer a robust foundation for ensuring high-density packages of semiconductors.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"169 ","pages":"Article 115728"},"PeriodicalIF":1.6,"publicationDate":"2025-04-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143768750","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Degradation mode analysis of Cu bond wires on Cu plated SiC power semiconductors stressed by active power cycling","authors":"Rasched Sankari ,&nbsp;Ulrich Kessler ,&nbsp;Martin Rittner ,&nbsp;Borja Kilian ,&nbsp;Youssef Maniar ,&nbsp;Olaf Wittler ,&nbsp;Martin Schneider-Ramelow","doi":"10.1016/j.microrel.2025.115715","DOIUrl":"10.1016/j.microrel.2025.115715","url":null,"abstract":"<div><div>Silicon carbide (SiC) is used as a new generation of power semiconductors to meet the increasing demands of modern electrified automotive powertrains. The state of the art involves Al-plated SiC semiconductors, which are bonded with Al bond wires. A known failure mode is the occurrence of cracks along the interface near the area between the Al bond foot and the Al metallization. In this study, an Al-free system with a fully copper-plated structure is used. The investigated SiC MOSFET is electroplated with <span><math><mrow><mn>30</mn><mspace></mspace><mi>μ</mi><mi>m</mi></mrow></math></span> Cu and contacted on top with <span><math><mrow><mn>300</mn><mspace></mspace><mi>μ</mi><mi>m</mi></mrow></math></span> Cu bond wires. The degradation mode of the copper bond wire as a topside contact for copper-plated SiC is to be analyzed, as limited results on the typical failure modes and mechanisms are available in the literature. The components are stressed in different configurations and measured by active power cycling tests. The investigations revealed different degradation modes depending on the degree of oxidation of the copper during the test. In the case of oxidation exclusion, the propagation and direction of cracks differ from the variant with strong oxidation. The experimental data of the oxidation-excluded variant are then analyzed using finite element simulation, focusing on the applied thermo-mechanical stress.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"169 ","pages":"Article 115715"},"PeriodicalIF":1.6,"publicationDate":"2025-04-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143768751","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Lidded SiP module: Warpage reduction techniques and thermal regime map","authors":"Javed Shaikh ,&nbsp;Krishnendu Saha ,&nbsp;Pouya Talebbeydokhti ,&nbsp;Stephan Stoeckl","doi":"10.1016/j.microrel.2025.115727","DOIUrl":"10.1016/j.microrel.2025.115727","url":null,"abstract":"<div><div>System-in-Package (SiP) modules, while common in mobile devices, face significant warpage and thermal challenges due to their large size and the close proximity of various components. Both package warpage and thermal performance play a vital role in the reliability of System in Package (SiP) modules. This study investigated novel warpage mitigation techniques, including Molded Thin Substrates (MTS), Back Side Stiffeners (BSS), enhanced Molded Thin Substrates (eMTS) and Lidded package. A test vehicle is developed to measure and characterize the warpage in different SiP module variants using the Shadow-Moiré technique. While MTS, BSS and eMTS showed some improvement, they ultimately fell short of meeting the required warpage reduction targets except Lidded package. The warpage mitigation techniques are further optimized for reducing the warpage below the target limits using a validated finite element warpage model. Lidded package emerged as the most effective solution for warpage control of the SiP module which can keep the SiP warpage within the targets. However, the addition of a lid introduced new thermal considerations due to an extra thermal interface material (TIM) layer at the lid interface.</div><div>A comprehensive thermal analysis is performed to study the impact of combination of system and package TIM resistances on the lid thermal performance, including the development of a novel metric - RTIM_r, which represents the ratio of system TIM resistance (RTIM_s) to package TIM resistance (RTIM_p). The study found that a lidded SiP module can achieve superior thermal performance compared to a bare die SiP module when the <span><math><msub><mi>RTIM</mi><mi>r</mi></msub><mo>≥</mo><mn>4</mn></math></span>. This research offers valuable insights into the complex interplay between warpage and thermal performance in the SiP modules. It provides a practical guideline for selecting appropriate system and package TIM combinations to optimize the thermal performance of lidded SiP modules. Future research can build upon these findings by further investigating the impact of package TIM thermal resistances on the warpage of lidded SiP modules.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"169 ","pages":"Article 115727"},"PeriodicalIF":1.6,"publicationDate":"2025-04-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143768753","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Improvement of sensitivity for power cycle degradation by a new device structure","authors":"Koki Okame ,&nbsp;Yuki Yamakita ,&nbsp;Shin-ichi Nishizawa ,&nbsp;Wataru Saito","doi":"10.1016/j.microrel.2025.115713","DOIUrl":"10.1016/j.microrel.2025.115713","url":null,"abstract":"<div><div>This paper reports a demonstration of a new sensor device structure designed to increase the current change for detecting power cycle degradation. In a previous study, a low-cost and high-accuracy sensor device was proposed, which can be integrated into power device chip. The sensor device consists of a Schottky barrier MISFET. Power cycling degradation is detected by a decrease in the drain current of the SB-MISFET, as repetitive mechanical stress increases the interface state density of the MIS gate. The sensor devices demonstrated the basic operation of a decrease in drain current due to repetitive mechanical stress. However, the change in current was only 4 to 5 times smaller than initial current. In this study, it is clarified that this current change is limited by leakage current, and a new structure is proposed to suppress this leakage current. The proposed structure achieved a current change 12 to 13 times smaller than the initial current, due to the leakage current 1/8 times smaller compared to the conventional structure.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"168 ","pages":"Article 115713"},"PeriodicalIF":1.6,"publicationDate":"2025-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143760922","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Comparison of electro-thermal-mechanical stress in SiC MOSFETs under several short-circuit types","authors":"Bin Yu ,&nbsp;Xingjian Shi ,&nbsp;Haoze Luo ,&nbsp;Wenbo Wang ,&nbsp;Zhiwen Chen ,&nbsp;Min Zhang ,&nbsp;Francesco Iannuzzo ,&nbsp;Wuhua Li","doi":"10.1016/j.microrel.2025.115720","DOIUrl":"10.1016/j.microrel.2025.115720","url":null,"abstract":"<div><div>In this paper, the electro-thermal-mechanical stress of SiC MOSFETs under current-limited short circuit (CL-SC) conditions, as employed in DC solid-state power controllers (DC-SSPCs), is investigated. The low on-resistance and high operating junction temperature (<em>T</em>_<em>J</em>) characteristics of SiC MOSFETs make them ideal power devices for DC-SSPC applications. During the clearing of a short circuit fault, the short circuit current is limited to a lower value by the DC-SSPC for an extended duration before being cut off. This leads to an increase in <em>T</em>_<em>J</em> within the SiC MOSFET, which raises reliability concerns. Research on the short circuit (SC) reliability of SiC MOSFETs has predominantly focused on the electro-thermal-mechanical stress under SC conditions in high-frequency converters (HFCs). However, the electro-thermal-mechanical stress and aging mechanisms of SiC MOSFETs under CL-SC conditions remain unclear. In this paper, SPICE-based and FEM-based simulations are conducted to analyze the electro-thermal-mechanical stress of SiC MOSFETs under CL-SC for DC-SSPCs and SC for HFCs. Results indicate that bonding wire lift-off, edge delamination, and voids in the middle of the solder layer are more likely to occur under CL-SC conditions, differing from those observed in SC for HFCs. Experimental results are presented to validate the simulation findings, providing a valuable reference for evaluating the reliability of SiC MOSFETs in DC-SSPC applications.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"168 ","pages":"Article 115720"},"PeriodicalIF":1.6,"publicationDate":"2025-04-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143748655","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Thermal management of automotive radar: Overcoming design challenges in constrained environments","authors":"Myong Hun Oh ,&nbsp;Su Hyun Yoon ,&nbsp;Soo Il Jeon ,&nbsp;Minsuk Choi","doi":"10.1016/j.microrel.2025.115725","DOIUrl":"10.1016/j.microrel.2025.115725","url":null,"abstract":"<div><div>Effective thermal management of automotive radar sensors operating under natural convection is essential for their optimal performance and reliability. This study introduces a comprehensive thermal design methodology for an automotive radar sensor using both experimental measurements and numerical simulations. Major heat-generating components in the radar sensor were firstly identified, and their temperatures were measured to determine the heat generation rates. Numerical simulations were then conducted to model the sensor's thermal behavior with and without its enclosure, focusing on natural convection as the primary cooling mechanism. Various thermal design strategies, including thermal bridges, were tested to improve the sensor's cooling. Experimental results demonstrated that the proposed methodology could increase the duty cycle of the radar sensor by approximately 6 % at room temperature and 8 % at high temperatures. This research highlights the effectiveness of the proposed thermal design methodology in addressing thermal management challenges, thereby improving the performance and reliability of automotive radar sensors in confined spaces.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"168 ","pages":"Article 115725"},"PeriodicalIF":1.6,"publicationDate":"2025-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143748654","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Reliability and failure analysis of AlGaN/GaN HEMT with NiPtAu and PtAu gate","authors":"M. Dammann ,&nbsp;P. Brückner ,&nbsp;R. Driad ,&nbsp;S. Krause ,&nbsp;S.A. Albahrani ,&nbsp;B. Weber ,&nbsp;M. Baeumler ,&nbsp;H. Konstanzer ,&nbsp;M. Mikulla ,&nbsp;M. Simon-Najasek ,&nbsp;S. Hübner ,&nbsp;A. Graff","doi":"10.1016/j.microrel.2025.115718","DOIUrl":"10.1016/j.microrel.2025.115718","url":null,"abstract":"<div><div>By comparing the reliability of 150 nm AlGaN/GaN HEMTs with PtAu gates to devices with NiPtAu SiN assisted gates, it was found that PtAu gates are more stable in terms of gate leakage current increase under HTRB step stress test and show smaller spread of the extrapolated lifetime values during long-term DC stress tests. An activation energy of 1.39 eV (1.97 eV) and a lifetime of around 10⁷ h at T_ch = 175 °C and V_d = 30 V has been extrapolated for devices with PtAu (NiPtAu) SiN assisted gate. By TEM cross sectioning and EDX mapping analysis of aged devices, the degradation of NiPtAu gate devices was attributed to a stress-induced local oxidation of the SiN passivation on the drain side of the gate foot. An activation energy of 1.15 eV and a lifetime of 5 · 10⁴ h at T_ch = 175 °C and V_d = 15 V has been extrapolated for devices with 100 nm T-gate reference technology. The faster degradation of the T-gate is possibly caused by a higher lateral electric field at the gate foot. T-gate reference technology lifetime is increased by more than an order of magnitude by reducing the drain voltage to 10 V.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"168 ","pages":"Article 115718"},"PeriodicalIF":1.6,"publicationDate":"2025-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143737851","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"An integrated physical model and extant data based approach for fault diagnosis and failure prognosis: Application to a photovoltaic module","authors":"Nassima Mebarki ,&nbsp;Leïla-Hayet Mouss ,&nbsp;Toufik Bentrcia ,&nbsp;Samir Benmoussa","doi":"10.1016/j.microrel.2025.115711","DOIUrl":"10.1016/j.microrel.2025.115711","url":null,"abstract":"<div><div>Nowadays, the increasing tendency towards the exploitation of solar energy has yielded many technological advancements. Hybrid approaches are attracting attention worldwide to ensure the comprehensive assessment of photovoltaic modules reliability becoming a crucial issue. The present study is dedicated to the investigation of an innovative approach integrating Bond graph theory, Gaussian mixture models and Similarity-based method for fault detection and remaining useful life prediction. In this context, Bond graphs are exploited first to create a dataset covering diverse operational modes of the system. The identification and evaluation of critical sensors for fault observability is also considered, where the dataset is optimized based on the variance analysis. The Gaussian mixture model with its semi-supervised initialization is then utilized for clustering and fault diagnosis, while remaining useful life estimation is performed using a pairwise similarity technique. Validation results on a photovoltaic panel model demonstrate that the Gaussian mixture model consistently outperforms the classical k-Nearest Neighbors model across all key metrics (accuracy of 0.9396 vs. 0.7577, precision of 0.9192 vs. 0.5570, recall of 0.7849 vs. 0.5628, and F1-score of 0.8666 vs. 0.6707), highlighting its superior performance. The remaining useful lifetime model also achieves high accuracy, with Root Mean Square Error values ranging from 0.0282 to 0.0300, indicating minimal prediction error. Additionally, the R-Squared value of ~0.92 shows that the model explains approximately 92% of the variance in remaining useful lifetime predictions, underscoring its strong predictive capability. The results demonstrate the practical effectiveness of the proposed framework for both single and multiple faults. However, some limitations are noted, such as the exclusion of the transition phase in training data and the reliance on controlled conditions. The outcomes of this work are expected to provide valuable insights into the implementation of efficient hybrid frameworks, contributing to the sustainable development of solar energy.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"168 ","pages":"Article 115711"},"PeriodicalIF":1.6,"publicationDate":"2025-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143748656","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"The behaviour of 350 V GaN HEMTs during heavy ion irradiations","authors":"F. Velardi ,&nbsp;G. Canale Parola ,&nbsp;S. Palazzo ,&nbsp;E. Martano ,&nbsp;A. Sanseverino ,&nbsp;L. Silvestrin ,&nbsp;C. Abbate ,&nbsp;G. Busatto","doi":"10.1016/j.microrel.2025.115723","DOIUrl":"10.1016/j.microrel.2025.115723","url":null,"abstract":"<div><div>The behaviour of a 350 V Enhancement Mode GaN power HEMT during heavy ion irradiation is presented. A new experimental setup has been developed to increase the sensitivity of the measurement. It allowed the measurement of the charge collected at the terminals following the impact with energetic particles to be extended by almost an order of magnitude. The results obtained, interpreted with the help of two-dimensional finite element simulations, demonstrate that the tested devices exhibit very different behaviour from those previously characterized. They do not show significant charge amplification and are not subjected to single-event gate rupture. Furthermore, it is demonstrated that the device failure is due to a recursive mechanism like that which develops in silicon PiN diodes when exposed to heavy ion irradiation.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"168 ","pages":"Article 115723"},"PeriodicalIF":1.6,"publicationDate":"2025-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143748653","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Impact of drain-source leakage on the dynamic Ron of power HEMTs with p-GaN gate","authors":"S.L. Longato ,&nbsp;D. Favero ,&nbsp;A. Stockman ,&nbsp;A. Nardo ,&nbsp;P. Vanmeerbeek ,&nbsp;M. Tack ,&nbsp;G. Meneghesso ,&nbsp;E. Zanoni ,&nbsp;C. De Santi ,&nbsp;M. Meneghini","doi":"10.1016/j.microrel.2025.115714","DOIUrl":"10.1016/j.microrel.2025.115714","url":null,"abstract":"<div><div>We present an extensive analysis of the impact of drain-source off-state leakage current on the dynamic on-resistance of GaN HEMTs with p-GaN gate. We analyzed two wafers with epitaxial layers grown under different conditions. The difference in the epitaxial layers gives an impact on the off-state leakage. We analyzed all the leakage components demonstrating that the wafer with lower off-state leakage shows a large dynamic R_on instability. Based on current transient measurements performed in temperature, this difference is explained by considering that a larger leakage (still below the nA) through the unintentionally-doped channel layer can ease the generation of positive charge at the bottom of the buffer, with consequent compensation of the dynamic R_on effect. The methodology presented in this paper constitutes a rapid and effective approach to evaluate the conductivity of the GaN channel layer, and its contribution to device stability.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"168 ","pages":"Article 115714"},"PeriodicalIF":1.6,"publicationDate":"2025-03-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143737845","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}