Microelectronics Reliability最新文献

{"title":"Condition monitoring of a DC-link capacitor in an inverter with a front-end diode rectifier under imbalanced three-phase supply voltage","authors":"Takuma Yamasoto ,&nbsp;Kazunori Hasegawa","doi":"10.1016/j.microrel.2025.115873","DOIUrl":"10.1016/j.microrel.2025.115873","url":null,"abstract":"<div><div>DC-link capacitors in inverters have a shorter lifetime than the other devices, and thus degrade reliability of the inverters. The inverters are usually fed by three-phase supply voltages; however, the three-phase voltages are frequently imbalanced due to the connection of single-phase power sources and loads, such as renewable energy, which places additional stress on the DC-link capacitors. This paper proposes a condition monitoring method of a DC-link capacitor without an additional current sensor in an inverter system under the imbalanced three-phase supply voltage. This inverter system employs a front-end six-pulse diode rectifier with a DC reactor. The method is based on an analysis of the rectifier output ripple voltage including the uncharacteristic harmonics that result from imbalanced supply voltage, which is valid in a practical imbalance ratio around 5%. Experimental results obtained from a 200-V 1.5-kW laboratory system confirmed that both the capacitance and ESR were monitored even though the supply voltage was imbalanced.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"173 ","pages":"Article 115873"},"PeriodicalIF":1.6,"publicationDate":"2025-07-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144714523","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Effect of Al content on microstructure and solder joint reliability of SAC305-2.0Sb-3.0Bi-0.1Ni solder alloys","authors":"Yipeng Xiang ,&nbsp;Jiayi Xu ,&nbsp;Biao Wang ,&nbsp;Jianhua Zhao ,&nbsp;Jikang Yan","doi":"10.1016/j.microrel.2025.115874","DOIUrl":"10.1016/j.microrel.2025.115874","url":null,"abstract":"<div><div>Currently, most studies on solder alloy reliability focus on six-element systems, while research on seven-element solder alloy alloys, particularly concerning the influence of Al is limited. To address this gap, this study investigates the effect of Al microalloying on the mechanical and interfacial properties of a newly developed seven-element solder alloy. SAC305-2.0Sb-3.0Bi-0.1Ni was used as the base composition, and varying amounts of Al were added to form the SACSBN-<em>x</em>Al alloy system. Microstructural analysis and mechanical testing were conducted, including X-ray diffraction (XRD), scanning electron microscopy (SEM), and high-temperature aging, to evaluate hardness, tensile strength, and intermetallic compound (IMC) growth behavior. The results show that the addition of Al significantly refines the microstructure and promotes a more uniform phase distribution. Notably, at 0.2 wt% Al addition, the solder exhibited the highest hardness (22.133 HV) and tensile strength (67.575 MPa), indicating substantial performance enhancement. Furthermore, high-temperature aging tests revealed that the IMC growth coefficient at the solder/substrate interface reached a minimum of 0.0128, suggesting improved interfacial stability. These findings demonstrate that Al microalloying, particularly at 0.2 wt%, effectively enhances the reliability and mechanical performance of the solder joint.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"173 ","pages":"Article 115874"},"PeriodicalIF":1.6,"publicationDate":"2025-07-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144711935","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Physics-informed deep learning approach for nanoindentation-based thin film analysis","authors":"Yusuf Burak Ozdemir ,&nbsp;Oguzhan Orkut Okudur ,&nbsp;Mario Gonzalez ,&nbsp;Clement Merckling","doi":"10.1016/j.microrel.2025.115875","DOIUrl":"10.1016/j.microrel.2025.115875","url":null,"abstract":"<div><div>This study presents an application of a physics-informed deep learning framework to improve and accelerate the yield stress characterization of thin films used in microelectronics to ensure long-term mechanical reliability via nanoindentation measurements. By combining finite element modeling (FEM) with neural networks, an accurate model for thin film yield stress has been demonstrated. This model offers comprehensive insights into the mechanical properties and plasticity of thin films under various loading conditions. The decision-making process of the model is investigated using explainable AI visualization techniques, enhancing the model's transparency and interpretability. Nanoindentation experiments on metal and dielectric thin films validate the high accuracy of the proposed deep learning models. This approach allows for the rapid analysis of load-displacement curves in milliseconds while providing high accuracy in yield stress estimations. Consequently, the proposed methodology significantly accelerates the characterization process and provides accurate yield stress estimations for thin film nanoindentation measurements, which is crucial for applications in microelectronics and the reliability of semiconductor devices.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"173 ","pages":"Article 115875"},"PeriodicalIF":1.6,"publicationDate":"2025-07-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144702883","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Accelerated flowers of sulfur test method for power semiconductor modules","authors":"Daniel T. Kaminski ,&nbsp;Christopher Genthe ,&nbsp;Benjamin C. Church","doi":"10.1016/j.microrel.2025.115870","DOIUrl":"10.1016/j.microrel.2025.115870","url":null,"abstract":"<div><div>In humid sulfur-bearing gas application environments, power semiconductor modules can be susceptible to a corrosion failure mechanism consisting of electrically conductive copper sulfide dendrite filaments formed within insulation trenches leading to electrical shorting. A simple, safe, and low-cost corrosion test method is presented here for reliability testing for this type of failure mechanism. The test method is based on a modified version of ASTM B809–95 that was first reported for use on sulfur resistant thick film chip resistors. Here, the test was further modified to include DC voltage for accelerated reliability testing of commercially available power semiconductor modules. It is shown that the field corrosion failure mechanism can be replicated by this accelerated test within as little as 120 h in fully populated commercial modules and can discern comparative susceptibility of packaging between manufacturers. This test method adds to the collection of accelerated corrosion tests previously reported for investigation of the dendritic filament corrosion failure mechanism and stands as an option that is less complex and less toxic. A three-stage hypothesis for the corrosion dendritic failure mechanism is also presented.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"173 ","pages":"Article 115870"},"PeriodicalIF":1.6,"publicationDate":"2025-07-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144694363","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Low-voltage Schottky p-GaN HEMT properties under extreme repetitive short-circuit operation conditions: 2DEG pinch-off, stability, aging, robustness and failure-modes analysis","authors":"F. Richardeau ,&nbsp;L. Ghizzo ,&nbsp;D. Trémouilles ,&nbsp;S. Vinnac","doi":"10.1016/j.microrel.2025.115871","DOIUrl":"10.1016/j.microrel.2025.115871","url":null,"abstract":"<div><div>The authors proposed in-depth experimentation and physical analysis showing the extreme robustness capability of low-voltage GaN HEMT in single and repetitive short-circuit. A 2DEG pinch-off behavior is analyzed depending on V_DS voltage and charges' trapping / de-trapping relaxation time. A new drain–gate leakage-current mechanism at turn-off is suggested to explain the ultimate thermal-runaway failure-mechanism.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"173 ","pages":"Article 115871"},"PeriodicalIF":1.6,"publicationDate":"2025-07-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144694304","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Conducted EMI assessment of aging power Si-MOSFET in 3 phase inverter","authors":"Mohamed TLIG ,&nbsp;Bassem ZITOUNA ,&nbsp;Moncef KADI ,&nbsp;Mahmoud HAMMOUDA ,&nbsp;Jaleleddine BEN HADJ SLAMA","doi":"10.1016/j.microrel.2025.115872","DOIUrl":"10.1016/j.microrel.2025.115872","url":null,"abstract":"<div><div>In this paper, we demonstrate that accelerated aging tests of power electronic components (specifically Si-based N-MOSFETs in our case) have an adverse effect on the conducted emissions (common and differential mode) in a 3-phase inverter used to drive an induction motor. To achieve this, we conduct electric accelerated aging tests while operating the power transistors to measure their conducted emissions before and after aging. A comparison between measurements in the time and frequency domains is presented to deduce the effect of aging on the Si-based N-MOSFETs. Experimental results show that after aging, there is an increase in the amplitude of conducted electromagnetic interference (EMI). Furthermore, this increase leads to electrical parameter degradation that has been investigated in EMI tests.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"173 ","pages":"Article 115872"},"PeriodicalIF":1.6,"publicationDate":"2025-07-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144694362","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"RHBD current-mode bandgap with SET isolation using PVT-independent sensors","authors":"Jaime Cardenas Chavez ,&nbsp;Ming Yan ,&nbsp;Tejinder Sandhu ,&nbsp;Adriana Noguera Cundar ,&nbsp;Kamal El-Sankary ,&nbsp;Li Chen","doi":"10.1016/j.microrel.2025.115865","DOIUrl":"10.1016/j.microrel.2025.115865","url":null,"abstract":"<div><div>This manuscript introduces a single event transient (SET) detecting circuit which is used in a current- mode bandgap reference circuit to reduce the magnitude of SET-induced voltage pulses at the bandgap output. Switches controlled by the SET detectors are inserted between the bandgap and output. When either a positive or negative voltage transient is detected at bandgap, one of the switches will be turned off to temporarily isolate the bandgap circuit from the output, thus preventing the SET glitches from propagating to the load devices. A capacitor at the output was used to keep the output voltage stable in case of an SET. Once the collected charge is dissipated and the bandgap reference circuit resumes normal operation, the switches will be turned on so that normal reference voltage will be reconnected to the output. This proposed structure was fabricated in a 28-nm FDSOI technology. Simulated results revealed a significant reduction in the SET magnitude. These results were also validated experimentally by using a 105 MeV proton radiation facility, and the SET magnitude at the bandgap reference output can be limited to 10 mV. The implemented SET detector is a versatile structure that can be applicable to DC circuits including LDOs, DC-DC converters and other types of bandgap reference circuits, enhancing their reliability when operating in high radiation environments.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"173 ","pages":"Article 115865"},"PeriodicalIF":1.6,"publicationDate":"2025-07-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144687579","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Degradation of high reliability lead-free solder joints under harsh thermal cycling test","authors":"Jeyun Yeom,&nbsp;Hans Rudolf Elsener,&nbsp;Tobias Burgdorf,&nbsp;Regina Bischoff,&nbsp;Lars P.H. Jeurgens,&nbsp;Jolanta Janczak-Rusch","doi":"10.1016/j.microrel.2025.115868","DOIUrl":"10.1016/j.microrel.2025.115868","url":null,"abstract":"<div><div>In this study, the degradation behavior of solder joints made using pre-selected, highly reliable lead-free solder alloys was investigated under thermal cycling conditions. Innolot (Sn 3.8Ag 0.7Cu 3.0Bi 1.5Sb 0.2Ni) and SB6NX (Sn 3.5Ag 0.8Cu 0.5Bi 6.0In) as well as reference solders: SAC305 (Sn 3Ag 0.5Cu) and SnPb solder were selected for this study, and solder joints of R1812 ceramic chip resistors on a printed circuit board were prepared by reflow soldering. The mechanical and microstructural degradation of the solder joints was investigated after thermal cycles (3000 cycles) from −55 to +100 °C with extended dwell times of 30 min. The crack length and void area were determined by optical microscopy from joint cross-sections and correlated with maximum shear force degradation obtained in mechanical shear tests. The results of the study support the development of highly reliable surface-mounted components for aerospace applications.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"173 ","pages":"Article 115868"},"PeriodicalIF":1.6,"publicationDate":"2025-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144680518","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Towards Extended Hückel model-based reliability performance enhancement of gate stack graphene nanoribbon field effect transistor","authors":"Anshul ,&nbsp;Rishu Chaujar","doi":"10.1016/j.microrel.2025.115869","DOIUrl":"10.1016/j.microrel.2025.115869","url":null,"abstract":"<div><div>This paper examines the performance and reliability of the gate stack graphene nanoribbon field effect transistor (GS-GNRFET) with the varied number of carbon atoms along the graphene nanoribbon width (n) in the channel material. Initially, the Extended Hückel (EH) model approach is used to calculate bandgap and density of states (DOS) and transmission spectrum (TS) of bulk configured armchair graphene nanoribbon (ACGNR) with <em>n</em> = 4 and 7. Then, these ACGNR (<em>n</em> = 4 and 7) are used in channel material to analyze the performance of proposed devices, namely the A4 device (GS-GNRFET with ACGNR (n = 4) in channel material) and the A7 device (GS-GNRFET with ACGNR (<em>n</em> = 7) in channel material. The result shows that the bandgap value is lower in ACGNR (<em>n</em> = 7) with a value of 1.09 eV compared with ACGNR (<em>n</em> = 4). Also, the ACGNR (n = 7) shows improved DOS and TS. Also, the EH model shows good agreement with DFT methods, validating its reliability and efficiency for modeling ACGNR-based low-power devices. The variation in the value of ‘n’ from 4 to 7 enhances the on current (I_on, 481 times ↑), decreases off current (I_off, 99.92 % ↓), improves the switching ratio (SR), reduces threshold voltage (V_th, 27 % ↓), reduces drain induced barrier lowering (DIBL, 16 % ↓) in A7 device as compared with A4 device. Also, the higher device efficiency (DE) value for the A7 device indicates lower voltage for significant current modulation, making it highly reliable for low-power applications. Moreover, the A7 device exhibits better transport properties, namely the Device Density of States (DDOS), projected density of states (PLDOS), transmission coefficient T (E), transmission pathways (TP), and Electron Difference Density (EDD). These parameters provide a unique way to evaluate device performance in terms of resonance peaks and electrical structure. The DDOS and contour plot of PLDOS analysis indicate a higher electron occupation, leading to better performance of the A7 device. The T(E) and TP analysis confirms stronger conductance, faster switching, and lower power consumption due to robust electron tunneling in the A7 device compared to the A4 device. The EDD analysis reveals more effective gate control with reduced electron density variations, resulting in improved switching behavior in the A7 device. Additionally, the A7 device has a very low value of static power (1.58 × 10⁻¹³ watt) compared to previous devices available in the literature. The improved findings regarding DE, SR, V_th (27 % ↓), DIBL (16 % ↓), TP, EDD, DDOS, and static power analysis of the A7 device make it suitable for applications in low-power areas like biomedical devices, sensors, and signal amplification areas. Owing to enhanced findings, this research article highlights the A7 device as a reliable and suitable candidate for low–power applications.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"173 ","pages":"Article 115869"},"PeriodicalIF":1.6,"publicationDate":"2025-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144680519","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Grain morphology effect on interfacial void closure in Cu–Cu bonding for advanced semiconductor packaging","authors":"Han Jiang ,&nbsp;Yaohua Xu ,&nbsp;Saranarayanan Ramachandran ,&nbsp;Shuibao Liang","doi":"10.1016/j.microrel.2025.115864","DOIUrl":"10.1016/j.microrel.2025.115864","url":null,"abstract":"<div><div>Driven by the demands of increased integration density and heterogeneous integration in the post-Moore era, Cu–Cu direct bonding has become a critical technology for enabling fine-pitch interconnects in advanced packaging. However, achieving reliable bonds remains challenging due to the existence of interfacial voids and the complex grain morphology that develops during the bonding process. In this work, a phase field model is developed and employed to investigate the effect of grain morphology on the kinetics of interfacial void closure during the Cu–Cu bonding process. Representative configurations are constructed by varying grain size and morphology in both bonded Cu pads to simulate realistic microstructural scenario. The results show that configurations with a larger number of smaller grains on both sides of the bonding structures promote faster void closure and achieve more uniform interfacial densification. This behavior is attributed to the increased presence of grain boundaries, which serve as enhanced diffusion pathways across the interface. Furthermore, the evolution of stress fields during bonding indicates that stress becomes more evenly distributed as voids close. The stress triaxiality near void regions remains below −1 throughout the closure process, demonstrating a favorable hydrostatic compressive state for void elimination. These findings provide further fundamental understanding of the mechanisms of void closure and may offer valuable guidance for improving the reliability of Cu–Cu bonding in advanced packaging applications.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"173 ","pages":"Article 115864"},"PeriodicalIF":1.6,"publicationDate":"2025-07-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144670372","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}