Microelectronics Reliability最新文献

{"title":"Microstructural and reliability analysis of SAC305/Sn-57Bi-1Ag composite solder joints with different printing aspect ratios","authors":"Taeyoon Im ,&nbsp;Jahyeon Kim ,&nbsp;Dongyurl Yu ,&nbsp;Young-Bae Park ,&nbsp;Yong-Ho Ko","doi":"10.1016/j.microrel.2026.116045","DOIUrl":"10.1016/j.microrel.2026.116045","url":null,"abstract":"<div><div>In semiconductor packaging, solders electrically connect the chip to the printed circuit board (PCB) while providing mechanical integrity. Sn–Ag–Cu (SAC) alloys are widely used because of their reliability, however, their high melting temperature of about 217 °C can induce PCB warpage and other defects during bonding. Therefore, low-melting Sn–Bi-based solders have attracted attention. In the case of Sn–57Bi–1Ag, it offers improved properties over eutectic Sn<img>58Bi and its Bi-related brittleness still remains a concern. To combine the advantages of both alloys, we investigated composite joints using SAC305 balls with Sn–57Bi–1Ag paste. Meanwhile, the influence of the printing aspect ratio (AR), which we define as the ratio of stencil opening diameter to printed paste height, on microstructure and reliability has not been clarified. This study elucidates how the aspect ratio affects Bi diffusion, intermetallic formation, and fracture behavior under two reflow profiles at a peak temperature of 180 °C (R180) and a peak temperature of 270 °C (R270). For the smaller aspect ratio with a larger opening and lower paste height, enhanced wetting and wicking promoted deeper Bi penetration and a broader Bi-enriched region, whereas the larger aspect ratio with a smaller opening and higher paste height led to shallower, peripheral Bi distribution with localized coarsening near the Cu₆Sn₅ intermetallic layer. After thermal shock from −40 °C to 85 °C for up to 2000 cycles, low-speed shear tests showed an increasing proportion of interfacial fracture at Cu₆Sn₅ for the smaller aspect ratio, while the larger aspect ratio under R270 remained ductile. Under high-speed shear, strain-rate effects promoted more brittle fracture overall. For the smaller aspect ratio, the fracture mode showed mixed ductile–brittle fracture from 0 to 1500 cycles under R180 and became fully interfacial brittle at 2000 cycles while it remained mixed under R270. For the larger aspect ratio, the fracture mode was brittle at all cycles under R180 and mixed under R270. These results identified the printing aspect ratio as a critical factor to control Bi diffusion, distribution, and coarsening, and to optimize the reliability of low-temperature SAC/Sn–Bi composite solder joints.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"179 ","pages":"Article 116045"},"PeriodicalIF":1.9,"publicationDate":"2026-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146175249","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Optimal bonding of 4H-SiC parallel diodes in a single TO-247 package for improved surge current robustness: experimental investigation","authors":"Vincenzo Terracciano ,&nbsp;Alessandro Borghese ,&nbsp;Carlo Ceresa ,&nbsp;Vincenzo d'Alessandro ,&nbsp;Andrea Irace","doi":"10.1016/j.microrel.2026.116049","DOIUrl":"10.1016/j.microrel.2026.116049","url":null,"abstract":"<div><div>In this study, the surge current capability of a 60 A–1200 V 4H-SiC diode fabricated by paralleling two 30 A dies is experimentally evaluated. Three bond wire configurations are investigated using a non-repetitive surge current test at 25 °C and 110 °C. The results reveal that the <em>stitch</em> configuration, which employs 3 × 20 mil bonding wires, significantly outperforms the alternative 4 × 15 mil and 4 × 12 mil counterparts in terms of maximum surge current robustness. An extensive analysis is also conducted to identify key differences in the failure mechanisms among the three configurations during surge current stress.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"179 ","pages":"Article 116049"},"PeriodicalIF":1.9,"publicationDate":"2026-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146175246","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Failure mechanisms of GaN HEMTs in single event destructive short-circuit at different VDS voltage levels","authors":"M.L. Dedew ,&nbsp;S. Lefebvre ,&nbsp;T.A. Nguyen ,&nbsp;T.L. Le ,&nbsp;V. Rustichelli ,&nbsp;J. Oliveira ,&nbsp;M. Alam ,&nbsp;J.P. Fradin ,&nbsp;A. Marie ,&nbsp;F. Coccetti","doi":"10.1016/j.microrel.2026.116059","DOIUrl":"10.1016/j.microrel.2026.116059","url":null,"abstract":"<div><div>In this work, the short-circuit (SC) robustness of 650 V normally-off SP-GaN HEMTs is investigated. The devices under test (DUTs) were subjected to single-event destructive SCs at different drain-source voltage levels. Overall, the DUTs exhibited a significant withstand time of several hundred microseconds. The experimental results first reveal the absence of a critical SC energy threshold, indicating that energy alone does not govern the failure mechanism. Instead, device failure is found to be more thermally driven, occurring once the junction temperature exceeds a specific limit. To support this conclusion, the junction temperature (T_j) evolution during the SC event was estimated using a highly simplified thermal model with a uniform heat dissipation based on the finite-element method (FEM), implemented in ANSYS APDL and calibrated with device geometries and material parameters extracted from its construction analysis. The simulation results show that all DUTs reached nearly the same T_j threshold at the instant of failure, regardless of the applied V_DS. However, due to the simplifying assumptions underlying the FEM simulations presented in this study, the estimated temperatures should be regarded as indicative rather than exact.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"179 ","pages":"Article 116059"},"PeriodicalIF":1.9,"publicationDate":"2026-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146175245","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Micro-scale fabrication and aging driven IMC evolution in SAC305/Sn-58Bi composite solder joints: A microstructural and mechanical correlation study","authors":"Dipayan Chakraborty ,&nbsp;Nisar Ahamad Khan ,&nbsp;Manish Kaushik ,&nbsp;V Ravindra ,&nbsp;Ajay Kumar","doi":"10.1016/j.microrel.2026.116023","DOIUrl":"10.1016/j.microrel.2026.116023","url":null,"abstract":"<div><div>The increasing push for miniaturization and multifunctionality in microelectronics is fueling the development of smaller solder joints to meet the demands of advanced electronic packaging. To address environmental and health concerns, a lead free composite micro-solder joint has been designed using Sn-3.0Ag-0.5Cu (SAC-305) and Sn-58Bi solders between two copper substrates. The reliability of these micro-solder joints is heavily influenced by their structural integrity under various operating temperatures, primarily due to the growth of intermetallic compound (IMC) layers. In this work, a miniature experimental setup was developed to fabricate micro-solder joints with thicknesses ranging from 40 to 60 μm, followed by a systematic investigation of IMC growth kinetics during thermal aging. Microstructural analysis reveals that Cu₆Sn₅ and Cu₃Sn are the dominant IMC phases formed at the solder copper interface during prolonged aging. Nanoindentation results reveal a progressive increase in joint hardness with aging time, driven by interfacial IMC thickening and secondary phase formation. Prolonged aging leads to joint embrittlement, promoting crack initiation and reducing mechanical reliability.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"178 ","pages":"Article 116023"},"PeriodicalIF":1.9,"publicationDate":"2026-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146025829","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Predictive modeling for aging performance of quantum dots composite under temperature-humidity dual stress coupling effect","authors":"Xuan Yang ,&nbsp;Linyi Xiang ,&nbsp;Bin Xie ,&nbsp;Xiaobing Luo","doi":"10.1016/j.microrel.2026.116013","DOIUrl":"10.1016/j.microrel.2026.116013","url":null,"abstract":"<div><div>Quantum dots (QDs) face significant challenges in high-temperature and high-humidity environments, where both thermal and humidity-induced degradation as well as humidity-induced enhancement can occur simultaneously. This dual stress coupling effect can lead to complex intensity evolution in QDs. Given the critical importance of performance and lifetime prediction in optoelectronic devices, a systematic study and predictive modeling of the aging performance of QDs under temperature-humidity conditions are essential. In this work, we experimentally investigated the light intensity evolution of QDs composites under various temperature-humidity conditions. The results showed both increases and decreases in intensity within a single aging curve. By analyzing the underlying mechanisms of these intensity changes, we developed a predictive model by modifying the Kohlrausch-Williams-Watts equation with an asymmetric Gaussian pulse function (AsG-KWW), which demonstrated excellent agreement with the experimental data under each aging condition. According to this model, three distinct stages were identified: a sharp initial intensity drop, a recovery, and a stable attenuation. Additionally, the mean time to failure (MTTF) of the samples was derived and analyzed using the AsG-KWW model. Analysis of the fitting parameters revealed that intensity recovery only occurred under relatively mild aging conditions.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"178 ","pages":"Article 116013"},"PeriodicalIF":1.9,"publicationDate":"2026-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146025825","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A BiLSTM-based digital twin model for photovoltaic strings under current mismatch condition","authors":"Yihan Chen ,&nbsp;Mingyao Ma ,&nbsp;Wenting Ma ,&nbsp;Rui Zhang ,&nbsp;Zhenyu Fang","doi":"10.1016/j.microrel.2026.116020","DOIUrl":"10.1016/j.microrel.2026.116020","url":null,"abstract":"<div><div>The reliability of photovoltaic (PV) systems is increasingly challenged by string-level faults affecting both performance and safety. To address this issue, this study proposes a four-layer digital twin (DT) framework for intelligent monitoring and fault diagnosis of PV strings under mismatch conditions. In the virtual layer, the Sandia Array Performance Model and the Perez model are employed to estimate module temperature and plane-of-array irradiance, which are then input into a bidirectional long short-term memory (BiLSTM) network for current prediction. To enhance adaptability, a solar-elevation-based Current Mismatch Ratio (CMR) is introduced as an auxiliary correction factor, enabling dynamic modeling of mismatch behavior. The CMR-assisted BiLSTM achieves a root mean square error (RMSE) of 0.4306 and a coefficient of determination (<span><math><msup><mrow><mi>R</mi></mrow><mrow><mn>2</mn></mrow></msup></math></span>) of 0.9594, demonstrating high predictive accuracy. In the decision layer, a sliding-window mechanism combined with a support vector machine classifier distinguishes bypass diode short-circuit faults from mismatch phenomena using statistical features of <span><math><msup><mrow><mi>R</mi></mrow><mrow><mn>2</mn></mrow></msup></math></span> and RMSE. Validation based on operational data from actual PV power plants shows that the proposed DT-based approach achieves an accuracy of 96.76%, precision of 93.39%, recall of 97.96%, and an F1-score of 95.63%, outperforming traditional reference string–based methods by 1.22%, 3.12%, and 1.59% in accuracy, precision, and F1-score, respectively. These results confirm that the proposed DT framework provides real-time fault diagnosis and predictive maintenance, significantly improving the operational reliability of PV systems under dynamic environmental conditions.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"178 ","pages":"Article 116020"},"PeriodicalIF":1.9,"publicationDate":"2026-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145993604","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Analytical reliability performance maps for bond wire interfaces in power modules under cyclic thermomechanical loads","authors":"Clément Chedozeau ,&nbsp;Merouane Ouhab ,&nbsp;Natasha Vermaak ,&nbsp;Nicolas Degrenne ,&nbsp;François Hild","doi":"10.1016/j.microrel.2026.116027","DOIUrl":"10.1016/j.microrel.2026.116027","url":null,"abstract":"<div><div>Reliability of power modules based on Insulated Gate Bipolar Transistors (IGBTs) is majorly challenged by thermomechanical fatigue, especially at the wirebond–chip interface where lift-off failure mechanisms commonly occur. This paper introduces a novel analytical model tailored to the geometry and material properties of the wirebond–chip interface to rapidly predict reliability performance maps highlighting different zones of expected elastoplastic behaviors under thermomechanical cycling. The model integrates a thermomechanical stress formulation with a Dugdale Cohesive Zone Model to capture plastic zone development at the interface and applies the Lower Bound Shakedown Theorem to identify elastoplastic behaviors without having to perform full cyclic incremental finite element simulations. The proposed analysis enables classification of cyclic behaviors into elastic, shakedown, and alternating plasticity regimes, providing a deeper understanding of the transition to low cycle fatigue at the shakedown/alternating plasticity boundary. Analytical predictions are compared to 2D finite element analyses, which confirm the ability of the model to capture key features like plastic strain evolution and its stabilization. The proposed modular model serves as a rapid and adaptable tool for early-stage reliability assessment as a function of geometric, material, and loading parameters.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"178 ","pages":"Article 116027"},"PeriodicalIF":1.9,"publicationDate":"2026-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146173979","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A junction-engineered SCR-based ESD protection device for radio-frequency and high-speed serial link interface circuits","authors":"Chen-Yu Liang,&nbsp;Ming-Dou Ker","doi":"10.1016/j.microrel.2026.116040","DOIUrl":"10.1016/j.microrel.2026.116040","url":null,"abstract":"<div><div>With the continuous increase in operating frequency of RF integrated circuits (RF ICs) and high-speed serial link (HSSL), optimizing electrostatic discharge (ESD) protection robustness per unit capacitance has become critical. Traditional solutions, such as dual diodes, stacked diodes, and silicon-controlled rectifier (SCR), face limitations including high parasitic capacitance, elevated conduction resistance, and difficulties in maintaining low trigger voltages (V_t1) and sufficiently high holding voltages (V_h) above the latch-up threshold. These challenges render them less effective for high-frequency applications.</div><div>In this work, a P-type diode integrated with a P-type ESD (P-ESD) implantation layer is first fabricated and characterized. Building upon this, an enhanced diode-triggered SCR (DTSCR) incorporating the P-ESD implantation layer is proposed and implemented in 28-nm CMOS technology. The proposed DTSCR exhibits improved ESD performance, including reduced V_t1, lowered V_h, and enhanced human-body model (HBM) robustness normalized by the product of conduction resistance and parasitic capacitance. These results demonstrate the potential of the DTSCR with P-ESD implantation as a promising solution for parasitic capacitance efficiency and high-robustness ESD protection in RF ICs and HSSL applications.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"178 ","pages":"Article 116040"},"PeriodicalIF":1.9,"publicationDate":"2026-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146173975","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Degradation modeling considering multiple performance parameters degradation based on mixed effects models","authors":"Junpeng Gao,&nbsp;Xuerong Ye,&nbsp;Qisen Sun,&nbsp;Cen Chen,&nbsp;Hao Chen,&nbsp;Guofu Zhai","doi":"10.1016/j.microrel.2026.116017","DOIUrl":"10.1016/j.microrel.2026.116017","url":null,"abstract":"<div><div>With the rapid evolution of prognostics and health management, reliability models now require higher accuracy and extrapolation capabilities. Despite advances in measurement technology, a certain degree of measurement error remains inevitable. Additionally, material variability and equipment inaccuracies during manufacturing lead to initial product values that follow a distribution correlated with degradation rates. Significant differences in degradation rates are also observed under various stress combinations. Furthermore, competing failure relationships among different performance parameters make it insufficient to consider only a single parameter. To address these challenges, this paper introduces a novel nonlinear mixed-effects model that accounts for both measurement errors and stochastic effects from random initial conditions. The model efficiently captures the coupling among stress factors and the competing failure relationships among multiple performance parameters. Model parameters are estimated using the least squares method. Finally, the proposed model was verified through degradation test data obtained from electrolytic capacitors subjected to combined temperature and voltage stresses. The results demonstrate that incorporating multiple performance parameters enables a more accurate representation of the degradation process and significantly improves prediction performance compared with single-parameter approaches. Furthermore, the reliability function derived from the model effectively characterizes the probability of failure over time, validating the model's capability to capture long-term reliability behavior. This degradation model can be widely applied to various components and shows considerable potential for system-level degradation analysis.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"178 ","pages":"Article 116017"},"PeriodicalIF":1.9,"publicationDate":"2026-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146025824","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Analysis of single event effects in full-customized modules for clock and data recovery circuits in 16 Gbps SerDes","authors":"Yahao Fang,&nbsp;Jianjun Chen,&nbsp;Bin Liang,&nbsp;Yaqing Chi,&nbsp;Deng Luo,&nbsp;Hanhan Sun,&nbsp;Qian Sun,&nbsp;Bo Yu","doi":"10.1016/j.microrel.2026.116011","DOIUrl":"10.1016/j.microrel.2026.116011","url":null,"abstract":"<div><div>Single event effects are investigated through heavy-ion experiments and laser experiments on full-customized modules for clock and data recovery circuits in 16 Gbps Serializer/Deserializer (SerDes). The experimental results show that the BER is highly susceptible to single event effects. Laser experiments identified several sensitive points, all located within the Voltage-Controlled Oscillator (VCO). The results of the study provide theoretical guidance for the future targeted hardened design of full-customized modules.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"178 ","pages":"Article 116011"},"PeriodicalIF":1.9,"publicationDate":"2026-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146025823","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}