Microelectronics Reliability最新文献_第2页

C-SMART: A preprocessor for neural network performance and reliability under radiation C-SMART：辐射下神经网络性能和可靠性的预处理器

IF 1.6 4区工程技术

Microelectronics Reliability Pub Date : 2025-07-21 DOI: 10.1016/j.microrel.2025.115859

Anuj Justus Rajappa , Philippe Reiter , Paolo Rech , Siegfried Mercelis , Jeroen Famaey

{"title":"C-SMART: A preprocessor for neural network performance and reliability under radiation","authors":"Anuj Justus Rajappa , Philippe Reiter , Paolo Rech , Siegfried Mercelis , Jeroen Famaey","doi":"10.1016/j.microrel.2025.115859","DOIUrl":"10.1016/j.microrel.2025.115859","url":null,"abstract":"<div><div>Edge AI brings the benefits of AI, such as neural networks for computer vision analysis, to low-power edge computing platforms. However, application and resource constraints leading to inadequate protection can make edge devices vulnerable to environmental factors, such as cosmic rays that continually shower on Earth. These factors can cause bit-flips that affect the reliability of the neural network inferences computed using these edge devices. To address this issue, we developed the Conditional-SMART (C-SMART) preprocessor designed to answer the question ‘When to use SMART?’, for obtaining both reliability and performance benefits. SMART is a reliability improvement technique introduced in our previous work, which involves skipping the multiply–accumulate operations performed on the zero-valued inputs to the layers of the neural network. We demonstrated C-SMART with a commercial bare-metal system containing an ARM microprocessor by exposing the system to real-world, atmospheric-like neutron radiation using the ChipIr facility in Oxfordshire, UK. We also conducted timing and energy measurements for performance analysis. Our experiments with C-SMART for inference with a neural network revealed a reliability boost against soft errors by more than 26% while improving performance by more than 35%. We foresee these benefits in various COTS devices by integrating C-SMART with compilers and neural network generators.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"173 ","pages":"Article 115859"},"PeriodicalIF":1.6,"publicationDate":"2025-07-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144670373","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Microstructure and diffusion mechanisms in nano-Cu sintered joints during aging: Effects of joint size, porosity, and aging atmosphere 纳米cu烧结接头在时效过程中的微观组织和扩散机制：接头尺寸、孔隙率和时效气氛的影响

IF 1.6 4区工程技术

Microelectronics Reliability Pub Date : 2025-07-14 DOI: 10.1016/j.microrel.2025.115863

Shuaiqi Wang , Guisheng Zou , Jinpeng Huo , Rongbao Du , Lei Liu

{"title":"Microstructure and diffusion mechanisms in nano-Cu sintered joints during aging: Effects of joint size, porosity, and aging atmosphere","authors":"Shuaiqi Wang , Guisheng Zou , Jinpeng Huo , Rongbao Du , Lei Liu","doi":"10.1016/j.microrel.2025.115863","DOIUrl":"10.1016/j.microrel.2025.115863","url":null,"abstract":"<div><div>Sintering bonding by nano-Cu is receiving great interests in die bonding of both power electronics and integrated circuits (IC) due to its low cost compared with nano-Ag/Au. However, oxidation of sintered Cu joints, having nanoporous microstructure, remains a concern for the reliability. This study systematically studied the effects of joint size, porosity, and aging atmosphere on the oxidation mechanisms of sintered Cu. An abnormal void growth was observed for the first time in low-porosity (4.27 %) Cu bumps (60 μm diameter) during high-temperature ambient aging, which was not observed in large-area sintered Cu (3 × 3 mm<sup>2</sup>). A hypothesis was proposed based on diffusion driven by oxidization. It indicated that the microscale bump size caused high chemical potential gradient between the nanoporous Cu and the Cu<sub>2</sub>O surface oxide, leading to a massive Cu atom diffusion through grain boundaries. Vacuum aging showed Ostwald ripening in bump center and vacancies in bump edge diffusing out of bumps, which was totally different from ambient condition. For high-porosity (17.12 %) Cu bumps, oxide was directly formed inside voids due to the penetration of O<sub>2</sub> through the connected voids. The findings revealed the oxidation mechanisms in microscale sintered Cu interconnects, which was essential for the advanced packaging of both IC and power electronics.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"173 ","pages":"Article 115863"},"PeriodicalIF":1.6,"publicationDate":"2025-07-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144623338","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Monitoring method for bond wire aging in IGBT modules based on gate voltage ringing frequency 基于栅极电压振铃频率的IGBT模块焊线老化监测方法

IF 1.6 4区工程技术

Microelectronics Reliability Pub Date : 2025-07-10 DOI: 10.1016/j.microrel.2025.115842

Mingxing Du, Jinlin Zhou, Jianxiong Yang, Haiqing Gu

{"title":"Monitoring method for bond wire aging in IGBT modules based on gate voltage ringing frequency","authors":"Mingxing Du, Jinlin Zhou, Jianxiong Yang, Haiqing Gu","doi":"10.1016/j.microrel.2025.115842","DOIUrl":"10.1016/j.microrel.2025.115842","url":null,"abstract":"<div><div>Aging monitoring of IGBT modules in power converters not only effectively improves system operational reliability, but also significantly reduces maintenance costs. This paper proposes a novel method for monitoring bond wire aging in IGBT modules based on the ringing frequency characteristics of the turn-on gate voltage. Initially, based on the turn-on characteristics of IGBT module and equivalent circuit model, this paper systematically analyzes the reasons for turn-on gate voltage ringing, and points out that the ringing frequency can be used as an indicator to reflect the aging of bond wires. Then, experimental validation of the proposed monitoring strategy was conducted on a buck converter testbed, with comprehensive analysis of operational impacts induced by DC-link voltage variations, gate resistance selection, and junction temperature fluctuations. Finally, this work presents a bond wire degradation monitoring scheme based on gate ringing frequency threshold analysis. The experimental results show that the voltage ringing frequency at the gate Miller plateau of the IGBT module decreases with the aging of the bond wires. The method is non-invasive, and achieves decoupling of the junction temperature using a set threshold.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"173 ","pages":"Article 115842"},"PeriodicalIF":1.6,"publicationDate":"2025-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144588048","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A physics-based electromigration model for advanced interconnects 基于物理的高级互连电迁移模型

IF 1.6 4区工程技术

Microelectronics Reliability Pub Date : 2025-07-10 DOI: 10.1016/j.microrel.2025.115862

Wangyong Chen , Binyu Yin , Linlin Cai , Yi Wan

引用次数: 0

Investigation of DFF cells SEU effect for 14 nm bulk silicon FinFET technology irradiated by heavy ions 重离子辐照14nm块体硅FinFET技术DFF电池SEU效应研究

IF 1.6 4区工程技术

Microelectronics Reliability Pub Date : 2025-07-10 DOI: 10.1016/j.microrel.2025.115857

Hai-song Li, Bin Wang, Yi-hu Jiang, Bo Yang, Li-jun Gao, Hong-ju Yue

{"title":"Investigation of DFF cells SEU effect for 14 nm bulk silicon FinFET technology irradiated by heavy ions","authors":"Hai-song Li, Bin Wang, Yi-hu Jiang, Bo Yang, Li-jun Gao, Hong-ju Yue","doi":"10.1016/j.microrel.2025.115857","DOIUrl":"10.1016/j.microrel.2025.115857","url":null,"abstract":"<div><div>A single-event effect test circuit was implemented in 14 nm bulk silicon FinFET technology, incorporating five flip-flop configurations: a standard D-type flip-flop (DFF), a logic depth DFF (LOG-DFF), a compact triple modular redundancy DFF (TMR-DFF), an interleaved TMR-DFF (INTER-TMR-DFF), and a dual interlocked storage cell DFF (DICE-DFF). Radiation testing was performed using heavy ion accelerator facilities with four ion species (F, Cl, Ge, and Ta). Experimental results demonstrated that the INTER-TMR-DFF achieved optimal single-event upset (SEU) resistance, although with area overhead, higher propagation delay, and greater power consumption compared to the baseline DFF. Both TMR-DFF and DICE-DFF exhibited effective radiation hardening at low linear energy transfer (LET) values, but showed degraded performance at higher LET levels. Notably, the DICE-DFF displayed a 40.7% increase in saturation cross-section relative to the standard DFF at LET values equal to 83.8 MeV·cm<sup>2</sup>/mg. This performance degradation under high-LET conditions correlates with technology scaling effects in advanced nanoscale processes: reduced feature sizes and increased transistor density exacerbate charge sharing phenomena. These parasitic charge redistribution effects fundamentally influence SEU mechanisms, compromising the radiation hardening benefits of both TMR-DFF and DICE-DFF architectures. Comprehensive comparative analysis evaluated all five flip-flop designs across multiple metrics: area occupation, propagation delay, power consumption, transistor count, and SEU resistance performance.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"173 ","pages":"Article 115857"},"PeriodicalIF":1.6,"publicationDate":"2025-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144588025","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Thermal-mechanical coupling analysis of Micro-LED bonding based on copper pillar bump 基于铜柱凸点的微型led键合热-力耦合分析

IF 1.6 4区工程技术

Microelectronics Reliability Pub Date : 2025-07-09 DOI: 10.1016/j.microrel.2025.115858

Hao Fu , Zhu Yang , Xinhui Meng , Hong Fan , Xiuzhen Lu , Luqiao Yin , Jianhua Zhang

{"title":"Thermal-mechanical coupling analysis of Micro-LED bonding based on copper pillar bump","authors":"Hao Fu , Zhu Yang , Xinhui Meng , Hong Fan , Xiuzhen Lu , Luqiao Yin , Jianhua Zhang","doi":"10.1016/j.microrel.2025.115858","DOIUrl":"10.1016/j.microrel.2025.115858","url":null,"abstract":"<div><div>With the rapid development of automotive electronics and near-eye display, more stringent requirements are put forward for the heterogeneous integration technology of Micro-LED, especially in interconnect structure. The copper pillar bumps with better electrical conductivity, thermal conductivity and mechanical properties can meet the packaging requirements of higher density and smaller pitch for application of Micro-LED array. The application of copper bumps in small pitch interconnect structures have been discussed in many studies while the application of copper pillar bumps in Micro-LED interconnection is currently rare. An equivalent model method of simulation combined with sub-model technique is proposed in this paper. The feasibility and accuracy of the equivalent method was investigated. Simulation of Micro-LED bonding process based on copper pillar bumps with equivalent method was performed. Low-temperature (40 °C) and high-temperature (280 °C) were applied to the upper bonding interface respectively to investigate the influence of bonding temperature on the stress of the device. Micro-LED bonding experiment was performed to validate the results of bonding simulation.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"173 ","pages":"Article 115858"},"PeriodicalIF":1.6,"publicationDate":"2025-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144580279","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Effect of electro-mechanical coupling on the electrical performance and microvoid evolution of Sn3.0Ag0.5Cu solder joint 机电耦合对Sn3.0Ag0.5Cu焊点电学性能及微空洞演变的影响

IF 1.6 4区工程技术

Microelectronics Reliability Pub Date : 2025-07-09 DOI: 10.1016/j.microrel.2025.115861

Weiqi Guo , Peng Liu , Yinghao Bi , Shuaifeng Zhao , Ping Wu

{"title":"Effect of electro-mechanical coupling on the electrical performance and microvoid evolution of Sn3.0Ag0.5Cu solder joint","authors":"Weiqi Guo , Peng Liu , Yinghao Bi , Shuaifeng Zhao , Ping Wu","doi":"10.1016/j.microrel.2025.115861","DOIUrl":"10.1016/j.microrel.2025.115861","url":null,"abstract":"<div><div>The evolution of microstructure and internal voids in Sn3.0Ag0.5Cu solder joints under electro-mechanical coupling loading conditions was systematically investigated. Experimental results revealed that under electrical loading (1.5 × 10<sup>4</sup> A cm<sup>−2</sup>), the solder joint resistance exhibited initial stability followed by a progressive increase until catastrophic failure through melting and open-circuit formation at 405 h. This phenomenon was accompanied by accelerated Cu dissolution, leading to extensive intermetallic compound formation and significant void growth perpendicular to the current direction. However, under electro-mechanical coupling conditions with an applied force of 5 N and current density of 1.5 × 10<sup>4</sup> A cm<sup>−2</sup>, the solder joint microstructure demonstrated remarkable stability, with void volume variations remaining below 1 %. This enhanced stability was attributed to the external stress gradient effectively counteracting the electron wind force, thus suppressing atomic migration. These findings provide new insights into the beneficial effects of applied stress on solder joint reliability, suggesting a novel approach for enhancing long-term solder joint performance.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"173 ","pages":"Article 115861"},"PeriodicalIF":1.6,"publicationDate":"2025-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144580487","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Free-standing silver nanobelt foils for sintering die bonding of power electronics and its power cycle reliability 电力电子烧结模键合用独立式纳米银带箔及其功率循环可靠性

IF 1.6 4区工程技术

Microelectronics Reliability Pub Date : 2025-07-07 DOI: 10.1016/j.microrel.2025.115860

Xinda Wang , Yanli Xu , Wei Guo , Zilong Peng , Hongqiang Zhang , Xingwen Zhou

引用次数: 0

Influence of die and lid shapes on void formation in solder thermal interface materials 模盖形状对焊料热界面材料中空洞形成的影响

IF 1.6 4区工程技术

Microelectronics Reliability Pub Date : 2025-07-07 DOI: 10.1016/j.microrel.2025.115847

Nurul Ashikin Mohd Nazrul Aman , Mohd Zulkifly Abdullah , Loh Wei Keat , Ooi Chun Keang

{"title":"Influence of die and lid shapes on void formation in solder thermal interface materials","authors":"Nurul Ashikin Mohd Nazrul Aman , Mohd Zulkifly Abdullah , Loh Wei Keat , Ooi Chun Keang","doi":"10.1016/j.microrel.2025.115847","DOIUrl":"10.1016/j.microrel.2025.115847","url":null,"abstract":"<div><div>Thermal interface material (TIM) is used to improve heat transfer between surfaces such as die to the lid. Solder-TIM is the popular choice for lidded electronic packages to effectively remove the heat from the compute die during operation due to its high thermal conductivity. However, solder-TIM is susceptible to form voids between the lid and the die which reduces the heat transfer effectiveness. In this study, computational fluid dynamics (CFD) was used to understand the mechanisms and behaviors of solder-TIM voiding for different die and lid shapes. Results from the simulations were validated with error less than 1 % to the experiments. It was found that the die shape is a crucial factor that influences the solder-TIM voiding. At same flatness of 60 μm, concave die resulted more voids at 30 % located near the die centre as compared to 3.66 % voids for convex die located near the die edges. For the lid shapes, it was found that conforming the lid to the die shape reduces the air gaps and which translated to minimum voids. For concave lid matching to convex die of same flatness, significant solder-TIM voids reduction of 0.55 % from 3.66 % was observed. This study signifies the importance of die and lid shapes to understand the solder-TIM voiding behavior and accurate method to mitigate it.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"173 ","pages":"Article 115847"},"PeriodicalIF":1.6,"publicationDate":"2025-07-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144570341","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Electrical and reliability characterization with an optimized extrapolation model of two- and three-dimensional metal-insulator-metal decoupling capacitors with ZrAlxOy high-κ dielectric under BEoL-friendly conditions 基于优化外推模型的ZrAlxOy高介电介质二维和三维金属-绝缘体-金属去耦电容器在beol友好条件下的电气和可靠性表征

IF 1.6 4区工程技术

Microelectronics Reliability Pub Date : 2025-07-07 DOI: 10.1016/j.microrel.2025.115845

Konstantinos Efstathios Falidas , Kati Kühnel , Matthias Rudolph , Maximilian Everding , André Reck , Malte Czernohorsky , Johannes Heitmann

{"title":"Electrical and reliability characterization with an optimized extrapolation model of two- and three-dimensional metal-insulator-metal decoupling capacitors with ZrAlxOy high-κ dielectric under BEoL-friendly conditions","authors":"Konstantinos Efstathios Falidas , Kati Kühnel , Matthias Rudolph , Maximilian Everding , André Reck , Malte Czernohorsky , Johannes Heitmann","doi":"10.1016/j.microrel.2025.115845","DOIUrl":"10.1016/j.microrel.2025.115845","url":null,"abstract":"<div><div>This study investigates the material properties, electrical characteristics, and reliability/lifetime aspects of ZrAl<sub>x</sub>O<sub>y</sub> dielectric films deposited by atomic layer deposition for Metal-Insulator-Metal decoupling capacitors in advanced CMOS technology under Back-End-of-Line-friendly conditions. Through experimental investigation, including structural and electrical characterization, the impact of Al concentration on capacitance behavior, leakage current, and breakdown characteristics in both 2D and 3D configurations is explored. Results indicate that higher Al concentrations contribute to higher field linearity and reduced leakage in both topologies, while thinner dielectrics exhibit a power-law relationship with breakdown temperature. Notably, 3D samples demonstrate a breakdown behavior less influenced by chemical composition. Lifetime analyses reveal excellent reliability in 2D devices with the highest Al concentration, necessitating higher Al concentrations to improve reliability, especially in challenging deep 3D topologies. These findings underscore the importance of material composition in conjunction with structural stability and their relation to reliability, ensuring stable and long-term performance of decoupling devices.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"173 ","pages":"Article 115845"},"PeriodicalIF":1.6,"publicationDate":"2025-07-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144570412","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0