Microelectronics Reliability最新文献_第2页

Study on the degradation mechanism of GaN MMIC PAs under on-state stress with different drain bias 氮化镓MMIC PAs在不同漏极偏压下的状态应力降解机理研究

IF 1.9 4区工程技术

Microelectronics Reliability Pub Date : 2025-09-15 DOI: 10.1016/j.microrel.2025.115898

Jia-Long Wang , Xue-Feng Zheng , Hao Zhang , Vazgen Melikyan , Xiao-Hua Ma , Yue Hao

{"title":"Study on the degradation mechanism of GaN MMIC PAs under on-state stress with different drain bias","authors":"Jia-Long Wang , Xue-Feng Zheng , Hao Zhang , Vazgen Melikyan , Xiao-Hua Ma , Yue Hao","doi":"10.1016/j.microrel.2025.115898","DOIUrl":"10.1016/j.microrel.2025.115898","url":null,"abstract":"<div><div>In this work, the degradation mechanisms of Gallium Nitride (GaN) Monolithic Microwave Integrated Circuit (MMIC) Power Amplifiers (PAs) under on-state stress with different drain bias have been studied. It is found that the direct current (DC) and Radio Frequency (RF) characteristics degrade significantly at high drain bias, which is mainly attributed to hot-electron effect. Using emission microscopy (EMMI) techniques, it can be concluded that the main degradation in GaN MMIC power amplifiers occurs in active components instead of passive components. The channel hot electron effect shows two impacts. The first one is the leakage current path near the drain edge, which is caused by the high-energy hot electrons that surmount AlGaN/GaN barrier. The second one is electron trapping within the active region between gate and drain, which can reduce the DC and RF performance. Finally, it is also found that the generated traps during the stress cannot recover easily even at high temperature of 250 °C, which indicates these traps are probably located at deep energy levels.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"175 ","pages":"Article 115898"},"PeriodicalIF":1.9,"publicationDate":"2025-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145061342","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A quantitative analysis and testing assessment method for functional damage state of electronic circuits under impact loads 冲击载荷作用下电子电路功能损伤状态的定量分析与试验评估方法

IF 1.9 4区工程技术

Microelectronics Reliability Pub Date : 2025-09-12 DOI: 10.1016/j.microrel.2025.115905

Dahai Li , Li Long , Peng Peng , Zhaodong Lin , Yongjian Zhang , Cong Xu , Changan Di , Junsong Ren

引用次数: 0

Microstructure and analysis of Au-Pd-Ag alloy bonding wires for enhanced optocoupler packaging performance 提高光耦合器封装性能的Au-Pd-Ag合金焊线的微观结构与分析

IF 1.9 4区工程技术

Microelectronics Reliability Pub Date : 2025-09-12 DOI: 10.1016/j.microrel.2025.115907

Zhiqian Yang , Kaixiang Hu , Rongsong Ge , Lite Zhao , Tingting Jin , Yizhan Chen

{"title":"Microstructure and analysis of Au-Pd-Ag alloy bonding wires for enhanced optocoupler packaging performance","authors":"Zhiqian Yang , Kaixiang Hu , Rongsong Ge , Lite Zhao , Tingting Jin , Yizhan Chen","doi":"10.1016/j.microrel.2025.115907","DOIUrl":"10.1016/j.microrel.2025.115907","url":null,"abstract":"<div><div>This study investigates the microstructural characteristics and formation mechanisms in Au-Pd-Ag alloy bonding wires for optocoupler packaging. Bonding wires with different gold contents (20 %, 60 %, and 99.99 %) were analyzed using SEM and EDS. The results show that the alloy wire with 60 % gold content exhibits uniform elemental distribution and forms a stable layer at the bonding interface, significantly enhancing bonding strength and reliability. Under accelerated aging tests, including intermetalic compound highly accelerated stress test and high-temperature storage test, the alloy wire demonstrates excellent resistance to aging, with growth following a parabolic law. Optimizing the Au and Pd content effectively slows intermetallic compound (IMC) formation, improving long-term stability. Additionally, the optimized alloy composition enhances optocoupler performance by improving <em>Iceo</em> and <em>V</em><sub><em>F</em></sub> characteristics while reducing production costs. This study provides a high-performance alternative for optocoupler packaging and offers insights into the microstructural design and layer control of alloy bonding wires, advancing electronic packaging technology.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"175 ","pages":"Article 115907"},"PeriodicalIF":1.9,"publicationDate":"2025-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145050026","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Accurate and efficient simulation of PCB warpage during manufacturing processes using partitioned equivalent model 利用分段等效模型精确、高效地模拟PCB制造过程中的翘曲

IF 1.9 4区工程技术

Microelectronics Reliability Pub Date : 2025-09-11 DOI: 10.1016/j.microrel.2025.115903

Mengxuan Cheng , Guoshun Wan , Hao Zheng , Xiaohui Zhao , Zhiyan Zhao , Yong Jiang , Yuxi Jia

{"title":"Accurate and efficient simulation of PCB warpage during manufacturing processes using partitioned equivalent model","authors":"Mengxuan Cheng , Guoshun Wan , Hao Zheng , Xiaohui Zhao , Zhiyan Zhao , Yong Jiang , Yuxi Jia","doi":"10.1016/j.microrel.2025.115903","DOIUrl":"10.1016/j.microrel.2025.115903","url":null,"abstract":"<div><div>During the complex manufacturing processes of printed circuit boards (PCBs), residual stresses inevitably accumulate, leading to warpage and stress concentration that can damage solder joints and interfaces, ultimately compromising the long-term reliability of electronic systems. To address these issues, this study proposes a partitioned equivalent model based on the multiscale finite element method, and comprehensively simulates the effects of lamination, etching and surface treatments (hot air solder leveling and solder mask coating) on PCB warpage. A key feature of this model is the integration of a post-processing strategy, which uses the correlation between copper content and coating thickness of the surface wiring layer to improve the prediction accuracy of PCB surface flatness and warpage. Additionally, the model incorporates specific boundary conditions for each wiring layer to more accurately calculate the equivalent material properties, under realistic manufacturing conditions. The multiscale simulation results are compared with the warpage and displacement curves obtained from both the shadow Moiré experiments and the finite element model with fully detailed wiring. The comparisons reveal a high level of agreement in warpage morphology, with the accuracy for warpage values of the partitioned equivalent model after surface treatments exceeding 75 %. Besides, this model shows significant advantages in computational efficiency, with simulation time reduced by up to 80 % compared to the fully detailed wiring model. Therefore, the proposed modeling approach can serve as an effective tool for optimizing PCB manufacturing processes, structural designs, and material selection, thereby enhancing the reliability and performance of electronic products.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"175 ","pages":"Article 115903"},"PeriodicalIF":1.9,"publicationDate":"2025-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145050027","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A 14-bit 3-MS/s SAR ADC with self-calibration for single-event transient mitigation 一种14位3毫秒/秒SAR ADC，具有自校准功能，用于单事件瞬态缓解

IF 1.9 4区工程技术

Microelectronics Reliability Pub Date : 2025-09-10 DOI: 10.1016/j.microrel.2025.115904

Mengwei Chen, Bin Wang, Jiarong Chen, Hui Wang, Yuan Liu, Longsheng Wu

{"title":"A 14-bit 3-MS/s SAR ADC with self-calibration for single-event transient mitigation","authors":"Mengwei Chen, Bin Wang, Jiarong Chen, Hui Wang, Yuan Liu, Longsheng Wu","doi":"10.1016/j.microrel.2025.115904","DOIUrl":"10.1016/j.microrel.2025.115904","url":null,"abstract":"<div><div>This paper proposes a 14-bit 3-MS/s SAR ADC architecture integrating digital front-end self-calibration and single-event transient (SET) hardening, implemented in a 55 nm 1P4M process. The segmented capacitive digital-to-analog converter (CDAC) employs a low-bit capacitor calibration mechanism in place of a traditional external DAC, achieving capacitor mismatch calibration while reducing area and power consumption. For radiation hardening, an overvoltage suppression circuit limits the sensitive node voltage of the sampling switch within the 3.3-V process specification. A bulk built-in current sensor (BBICS) is embedded in the CDAC to eliminate irradiation effects by dynamically switching the top plate and common-mode nodes, without introducing additional conversion cycles or complex compensation circuits. Additionally, a dynamic comparator with a dual interlocked storage cell (DICE) structure is used to reduce radiation-sensitive nodes. Simulation results show that after calibration, differential non-linearity (DNL) and integral non-linearity (INL) are both less than 1 Least Significant Bit (LSB), and the sampling switch overshoot voltage is effectively suppressed. Under radiation conditions with linear energy transfer (LET) = 37 <span><math><mfenced><mrow><mi>MeV</mi><mo>∙</mo><msup><mi>cm</mi><mn>2</mn></msup></mrow></mfenced><mo>/</mo><mi>mg</mi></math></span>, the hardened CDAC exhibits an output error of only 2 mV and an effective number of bits (ENOB) of 13.42, approaching the pre-irradiation level. This study provides a systematic SET hardening solution for high-reliability ADC design.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"175 ","pages":"Article 115904"},"PeriodicalIF":1.9,"publicationDate":"2025-09-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145027833","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

YOLO-APGC: A lightweight method for BGA surface defect detection based on cross-scale feature fusion YOLO-APGC：一种基于跨尺度特征融合的BGA表面缺陷轻量化检测方法

IF 1.9 4区工程技术

Microelectronics Reliability Pub Date : 2025-09-10 DOI: 10.1016/j.microrel.2025.115906

Liwei Fan , Yijia Wang , Yongbing Zhou , Jian Zhang , Haojie Chen

{"title":"YOLO-APGC: A lightweight method for BGA surface defect detection based on cross-scale feature fusion","authors":"Liwei Fan , Yijia Wang , Yongbing Zhou , Jian Zhang , Haojie Chen","doi":"10.1016/j.microrel.2025.115906","DOIUrl":"10.1016/j.microrel.2025.115906","url":null,"abstract":"<div><div>Ball Grid Array (BGA) surface defect detection is critical for ensuring the safety and reliability of electronic products. In recent years, numerous deep learning-based BGA surface defect detection algorithms have achieved significant detection performance in this field. However, the computational complexity of existing high-precision models has limited their application in real-time detection on industrial production lines. To address this issue, this paper proposes a lightweight detection architecture based on You Only Look Once v8 (YOLOv8), named YOLO-ADown and Partial Group-shuffle Cross-scale Feature Fusion (YOLO-APGC), which aims to significantly reduce the number of model parameters and computational costs while maintaining high detection accuracy. First, in the feature extraction stage, Adaptive Downsampling (ADown) is introduced, and a novel lightweight Double Partial-Block (PP-Block) module is constructed to synergistically optimize the information retention efficiency and computational cost during the high-dimensional feature compression process. Then, to achieve efficient fusion of multi-scale features, a novel cross-scale dynamic feature fusion network, the Partial Group-shuffle Cross-scale Feature Fusion Network (PG-CCFN), is proposed. Finally, a new BGA dataset is constructed based on industrial scenarios, and a series of experiments are conducted. The results show that the number of parameters in YOLO-APGC is reduced by 68.21 % compared to the baseline model. Additionally, the Giga Floating-point Operations Per Second (GFLOPs) is reduced by 54.32 %, and the Frames Per Second (FPS) is improved by 9.1 %. This model offers a low-cost, highly robust intelligent quality inspection solution for the microelectronics packaging industry, providing significant engineering value in ensuring the long-term reliability of microelectronics packaging.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"175 ","pages":"Article 115906"},"PeriodicalIF":1.9,"publicationDate":"2025-09-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145027753","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A novel simulated annealing algorithm for TTSV placement optimization in 3D integrated circuits with inhomogeneous heat sources 非均匀热源三维集成电路中TTSV布局优化的模拟退火算法

IF 1.9 4区工程技术

Microelectronics Reliability Pub Date : 2025-09-09 DOI: 10.1016/j.microrel.2025.115902

Feng Dai, Zhongliang Pan

引用次数: 0

A method for integrated circuit trimming focused on separation of trim codes 一种集成电路切边的方法，重点是切边码的分离

IF 1.9 4区工程技术

Microelectronics Reliability Pub Date : 2025-09-07 DOI: 10.1016/j.microrel.2025.115889

Wenfa Zhan , Yangxinzi Zhou , Jiangyun Zheng , Xiaoqing Wen

{"title":"A method for integrated circuit trimming focused on separation of trim codes","authors":"Wenfa Zhan , Yangxinzi Zhou , Jiangyun Zheng , Xiaoqing Wen","doi":"10.1016/j.microrel.2025.115889","DOIUrl":"10.1016/j.microrel.2025.115889","url":null,"abstract":"<div><div>In advanced processes, the addition of trimming circuits can effectively improve the yield of high-end chips. However, the mapping relationship between trimming parameters and trim codes in traditional methods is often segmented and discontinuous. This paper proposes a method that separates the trim codes into computational trim codes and applied trim codes. By reconstructing the mapping relationships between trimming parameters and computational trim codes, as well as between computational trim codes and applied trim codes, the proposed method achieves a linear mapping relationship between trimming parameters and computational trim codes, and a logical relationship between computational trim codes and applied trim codes. This novel method effectively reduces the number of trimming iterations and trimming time, thereby improving trimming efficiency. Two different hardware and software-based implementations have been designed to validate its feasibility. Experiments using two optimization algorithms demonstrate that trimming time can be reduced by an average of 44.97% and 40.00%, respectively, fully validating the effectiveness of the proposed method.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"174 ","pages":"Article 115889"},"PeriodicalIF":1.9,"publicationDate":"2025-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145010529","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Application of machine learning modeling for predicting the reliability of solder joints under thermal cycling 机器学习模型在热循环下焊点可靠性预测中的应用

IF 1.9 4区工程技术

Microelectronics Reliability Pub Date : 2025-09-06 DOI: 10.1016/j.microrel.2025.115900

Qiulin Yu , Chinmay Nawghane , Zihan Zhang , Bart Vandevelde , Karl Fendt , Thomas Krivec , Dieter P. Gruber

引用次数: 0

Enhancement on interface and shear properties of Sn-1.0Ag-0.5Cu solder joints by 0.05 % Ge under isothermal aging and thermal cycling 等温时效和热循环对Sn-1.0Ag-0.5Cu焊点界面和剪切性能的增强

IF 1.9 4区工程技术

Microelectronics Reliability Pub Date : 2025-08-30 DOI: 10.1016/j.microrel.2025.115899

Han Yan, Yu Ding, Fengjiang Wang

{"title":"Enhancement on interface and shear properties of Sn-1.0Ag-0.5Cu solder joints by 0.05 % Ge under isothermal aging and thermal cycling","authors":"Han Yan, Yu Ding, Fengjiang Wang","doi":"10.1016/j.microrel.2025.115899","DOIUrl":"10.1016/j.microrel.2025.115899","url":null,"abstract":"<div><div>This study evaluated the influence of trace Ge addition into Sn-1.0Ag-0.5Cu solder on the interface and shear properties during isothermal aging and thermal cycling. After reflow soldering, trace Ge preferentially dissolved in the β-Sn matrix, modified the interfacial geometry from serrated to scallop with reduced thickness of the interfacial compounds (IMCs), and increased the shear strength on solder joints. During aging, Ge reduced the diffusion of Sn atoms and the production of Cu<sub>6</sub>Sn<sub>5</sub> and Cu<sub>3</sub>Sn at the interface, and enhanced the high temperature-resistance on the shear strength of the joints. In thermal cycling tests, Ge addition considerably reduced the thermal stress within the joints, prevented the propagation of fractures from the solder to the interface, and increased the thermal cycling reliability of the joints. By comparing the failure modes, the IMC growth during thermal cycling was slower than that during aging, and the trace Ge addition had a better inhibitory effect on the growth of IMC layer during thermal cycling.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"174 ","pages":"Article 115899"},"PeriodicalIF":1.9,"publicationDate":"2025-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144920182","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0