A 14-bit 3-MS/s SAR ADC with self-calibration for single-event transient mitigation

This paper proposes a 14-bit 3-MS/s SAR ADC architecture integrating digital front-end self-calibration and single-event transient (SET) hardening, implemented in a 55 nm 1P4M process. The segmented capacitive digital-to-analog converter (CDAC) employs a low-bit capacitor calibration mechanism in place of a traditional external DAC, achieving capacitor mismatch calibration while reducing area and power consumption. For radiation hardening, an overvoltage suppression circuit limits the sensitive node voltage of the sampling switch within the 3.3-V process specification. A bulk built-in current sensor (BBICS) is embedded in the CDAC to eliminate irradiation effects by dynamically switching the top plate and common-mode nodes, without introducing additional conversion cycles or complex compensation circuits. Additionally, a dynamic comparator with a dual interlocked storage cell (DICE) structure is used to reduce radiation-sensitive nodes. Simulation results show that after calibration, differential non-linearity (DNL) and integral non-linearity (INL) are both less than 1 Least Significant Bit (LSB), and the sampling switch overshoot voltage is effectively suppressed. Under radiation conditions with linear energy transfer (LET) = 37 $\left(\mathrm{MeV}\bullet {\mathrm{cm}}^2\right)/\mathrm{mg}$, the hardened CDAC exhibits an output error of only 2 mV and an effective number of bits (ENOB) of 13.42, approaching the pre-irradiation level. This study provides a systematic SET hardening solution for high-reliability ADC design.