A novel simulated annealing algorithm for TTSV placement optimization in 3D integrated circuits with inhomogeneous heat sources

As the integration of three-dimensional integrated circuits (3D-ICs) increases, thermal management becomes increasingly important. The insertion of thermal through silicon via (TTSV) among 3D-IC is considered an effective way to solve thermal dissipation. In this paper, an optimized simulated annealing (OSA) algorithm that considers the distribution of TTSVs is proposed. The algorithm takes into account how the TTSV distribution affects the 3D-ICs heat distribution under inhomogeneous heat sources. In the global simulation of 3D-IC, this optimization algorithm can effectively reduce the temperature of 3D-IC. The algorithm was then simulated with COMSOL software, which matched the previous calculation results. The simulation results reveal that the peak temperatures of the TTSVs distribution using the OSA algorithm in single-layer and four-layer chip simulations are reduced by 1.78 K and 1.2 K, respectively, compared to the uniform distribution. Therefore, this algorithm effectively reduces the hotspot temperature of the chip and increases its stability.