Microelectronics Reliability最新文献

{"title":"Gas breakdown characteristic and ablation defect formation mechanism of micro-scale gap in MEMS","authors":"Jiaqi Zheng ,&nbsp;Renzhi Hu ,&nbsp;Jie Yang ,&nbsp;Guofen Xie ,&nbsp;Xuhui Gong ,&nbsp;Chunlin Liu ,&nbsp;Baolin Zhao","doi":"10.1016/j.microrel.2025.115936","DOIUrl":"10.1016/j.microrel.2025.115936","url":null,"abstract":"<div><div>Gas breakdown at the microscale dimension has become one of the critical challenges one of urgent challenges along with the miniaturization and high-performance development of MEMS (Micro-Electro-Mechanical Systems) devices. However, comprehensive theoretical frameworks for micro-scale gas discharge characteristic and damage mechanisms in MEMS devices remains to be developed. In the article, the gas discharge behaviors of silicon-based MEMS devices with 1.5 μm gap were investigated, whose I-V characteristics during the initial breakdown process under DC voltage and the subsequent breakdown behavior upon reapplication of voltage were characterized in detail. A theoretical investigation incorporating field emission theory was performed to examine the twice breakdown phenomena, elucidating the critical factors and underlying mechanisms of micro-gap gas discharge. Incorporating ablation defect morphology, compositional analysis, and finite element simulation, the formation process of ablation defects on silicon electrodes was investigated, revealing the breakdown characteristics of MEMS devices with micro-gaps.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"175 ","pages":"Article 115936"},"PeriodicalIF":1.9,"publicationDate":"2025-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145363518","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A novel simulated annealing algorithm for TTSV placement optimization in 3D integrated circuits with inhomogeneous heat sources","authors":"Feng Dai,&nbsp;Zhongliang Pan","doi":"10.1016/j.microrel.2025.115902","DOIUrl":"10.1016/j.microrel.2025.115902","url":null,"abstract":"<div><div>As the integration of three-dimensional integrated circuits (3D-ICs) increases, thermal management becomes increasingly important. The insertion of thermal through silicon via (TTSV) among 3D-IC is considered an effective way to solve thermal dissipation. In this paper, an optimized simulated annealing (OSA) algorithm that considers the distribution of TTSVs is proposed. The algorithm takes into account how the TTSV distribution affects the 3D-ICs heat distribution under inhomogeneous heat sources. In the global simulation of 3D-IC, this optimization algorithm can effectively reduce the temperature of 3D-IC. The algorithm was then simulated with COMSOL software, which matched the previous calculation results. The simulation results reveal that the peak temperatures of the TTSVs distribution using the OSA algorithm in single-layer and four-layer chip simulations are reduced by 1.78 K and 1.2 K, respectively, compared to the uniform distribution. Therefore, this algorithm effectively reduces the hotspot temperature of the chip and increases its stability.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"175 ","pages":"Article 115902"},"PeriodicalIF":1.9,"publicationDate":"2025-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145020832","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"An interface trap density evaluation method for SiC MOSFET based on neural network","authors":"Borui Yang ,&nbsp;Guicui Fu ,&nbsp;Bo Wan ,&nbsp;Xiangfen Wang","doi":"10.1016/j.microrel.2025.115934","DOIUrl":"10.1016/j.microrel.2025.115934","url":null,"abstract":"<div><div>The high density of interface defects at the gate oxide interface is closely related to the device characteristics and reliability of silicon carbide metal-oxide-semiconductor field effect transistors. However, an efficient and reliable characterization method for interface defects remains to be developed. In this work, we propose a neural network method for evaluating the interface trap density distribution and fixed oxide charge density using the transfer characteristics of devices. The neural network utilizes a long short-term memory structure to capture the mapping relationship between the transfer characteristic and the interface defect parameters. The numerical simulation data are used to form the training dataset of the network, and an effective preprocessing method is also presented. The proposed method was successfully verified by comparing simulated transfer characteristics using the evaluated results of commercial devices with corresponding measurements. Also, the interface defect parameters were evaluated by the subthreshold current method for comparison. The result shows that the evaluated results of the proposed method are close to the experimental evaluated results, with relative errors of 3.3 %, 6.6 %, and 28.2 % for the three devices under threshold voltage, respectively. Further, the proposed method was successfully applied during the high temperature gate bias tests to detect the degradation trend of the gate oxide interface. The result reflects its practicality for the interface reliability analysis of silicon carbide metal-oxide-semiconductor field effect transistors.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"175 ","pages":"Article 115934"},"PeriodicalIF":1.9,"publicationDate":"2025-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145333335","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Exploring the use of extreme temperatures to facilitate fault propagation in ReRAMs","authors":"T.S. Copetti ,&nbsp;A. Chordia ,&nbsp;M. Fieback ,&nbsp;M. Taouil ,&nbsp;S. Hamdioui ,&nbsp;L.M. Bolzani Poehls","doi":"10.1016/j.microrel.2025.115919","DOIUrl":"10.1016/j.microrel.2025.115919","url":null,"abstract":"<div><div>Resistive Random-Access Memories (ReRAMs) represent a promising candidate to complement and/or replace CMOS-based memories adopted in several emerging applications. Despite all their advantages – mainly CMOS process compatibility, zero standby power, and high scalability and density – the use of ReRAMs in real applications depends on guaranteeing their quality after manufacturing. As observed in CMOS-based memories, ReRAMs are also susceptible to manufacturing deviations, including defects and process variations, that can cause faulty behaviors different from those observed in CMOS technology, increasing not only the manufacturing test complexity but also the time required to perform the test. In this context, this paper proposes to study the use of temperature to facilitate fault propagation in ReRAMs, reducing the required test time. A case study composed of a 3x3 word-based ReRAM with peripheral circuitry implemented based on a 130 nm Predictive Technology Model (PTM) library was adopted. During the proposed study, a total of 17 defects were injected in different positions of the ReRAM cell, and their respective faulty behavior was classified into conventional and unique faults, considering three different temperatures (25, 100, and -40 °C). The obtained results show that the temperature can, depending on the position of the defect, facilitate fault propagation, which reduces the time required for performing manufacturing testing.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"175 ","pages":"Article 115919"},"PeriodicalIF":1.9,"publicationDate":"2025-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145226994","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Reliability assessment of graphene channel vertical TFET: Role of trap-assisted tunneling","authors":"Vanshika Ghai ,&nbsp;Sidhartha Dash ,&nbsp;Guru Prasad Mishra","doi":"10.1016/j.microrel.2025.115943","DOIUrl":"10.1016/j.microrel.2025.115943","url":null,"abstract":"<div><div>This paper proposes a graphene channel-based Vertical Tunnel Field Effect Transistor (V-TFET) and analyzes its reliability using Trap-Assisted Tunneling (TAT). The Graphene Channel V-TFET (GC V-TFET) improves device performance because of graphene's two-dimensional honeycomb structure enhancing electron tunneling. Compared to ordinary V-TFETs, this GC V-TFET offers over one decade of improvement in drain current, a two-decade increase in the I_ON/I_OFF ratio, a higher electric field, a lower energy bandgap width, and a one-fold improvement in transconductance. The Silvaco ATLAS TCAD tool compares the simulations of V-TFET and GC V-TFET. To assess reliability, the impact of TAT on the GC V-TFET has been investigated. The results showed an increase of about one decade in the I_OFF value, increase in electric field of approximately 3.0 × 10⁴ V/cm, decrease in potential of about 0.04 V, an upward shift in energy bands of about 0.02 eV, increased transconductance of 1.5 × 10⁻⁶ S, electron concentration at source side is reduced by 4 × 10¹⁶ cm⁻³, hole concentration at channel region decreases by approximately 20 %, electron current density is increased by three and two orders at channel and drain region respectively, hole current density is increased by approximately four orders at source region and decrease in the recombination rate of 4.2 × 10⁴ cm⁻¹ s⁻¹.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"175 ","pages":"Article 115943"},"PeriodicalIF":1.9,"publicationDate":"2025-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145424713","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Research on the lifetime model of IGBT modules based on coupling failure of bonding wire and solder layer","authors":"Biao Li ,&nbsp;Zhaolei Zheng ,&nbsp;Feng Wang ,&nbsp;Zhuangzhuang Li ,&nbsp;Jun Liu","doi":"10.1016/j.microrel.2025.115923","DOIUrl":"10.1016/j.microrel.2025.115923","url":null,"abstract":"<div><div>To address the issues of insulated gate bipolar transistor module failure and lifetime prediction, a physical model of the insulated gate bipolar transistor module has been established. Through thermo-electrical structural coupling simulations, the failure mechanisms of the bonding wire and solder layer have been analyzed. Based on the failure mechanisms of both components, a lifetime model for insulated gate bipolar transistor modules, considering the coupling failures of the bonding wire and solder layer, has been constructed. Additionally, the failure model has been fitted using data from power cycling tests, and a comparative analysis has been conducted between the parallel failure lifetime model and the energy-based lifetime model and Coffin-Manson lifetime model in terms of prediction accuracy. The results indicate that the insulated gate bipolar transistor module lifetime model based on parallel failures of the bonding wire and solder layer has an average error of less than 5 %, reducing the error by 7.74 % compared to the classical lifetime model. Furthermore, it shows a 59.38 % reduction in error compared to the energy-based lifetime model that considers only solder layer failure, significantly improving prediction accuracy. The development of the model and its results provide important reference significance for the reliability assessment of insulated gate bipolar transistor modules.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"175 ","pages":"Article 115923"},"PeriodicalIF":1.9,"publicationDate":"2025-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145158881","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"An FPGA-based architecture for time-resolved polarization probing of FeRAM fatigue","authors":"Yubin Liao ,&nbsp;Zerong He ,&nbsp;Xiangyin Chen ,&nbsp;Zhongguang Xu","doi":"10.1016/j.microrel.2025.115920","DOIUrl":"10.1016/j.microrel.2025.115920","url":null,"abstract":"<div><div>Traditional approaches to assessing Ferroelectric RAM (FeRAM) reliability rely on direct electrical access to individual capacitors. While effective on isolated test structures, such methods are infeasible for high-density, packaged memory arrays, creating a critical gap between device-level physics and system-level reliability assessment. To bridge this gap, we propose Time-Resolved Polarization Probing (TRPP), a novel indirect methodology that infers the internal polarization state by precisely measuring the minimum switching time accessible at the cell terminals. We implement TRPP on a custom FPGA-based platform that integrates a flexible MBIST engine for controlled fatigue stressing with a carry-chain programmable delay generator offering 53<!--> <!-->ps resolution. Experimental results on FeRAM devices demonstrate that TRPP effectively quantifies the progressive degradation of polarization kinetics under stress up to <span><math><mrow><mn>1</mn><msup><mrow><mn>0</mn></mrow><mrow><mn>9</mn></mrow></msup></mrow></math></span> cycles. The measurements further reveal disproportionately severe degradation at lower operating voltages, underscoring critical implications for low-power and compute-in-memory applications. Overall, this work establishes TRPP as a high-resolution, scalable methodology for reliability characterization, bridging the gap between device physics and system-level deployment.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"175 ","pages":"Article 115920"},"PeriodicalIF":1.9,"publicationDate":"2025-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145158882","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Theoretical performance and reliability optimization of graphene based electrically doped tunnel FET under interface trap charge constraints: A device-level approach","authors":"Bandi Venkata Chandan,&nbsp;Kaushal Kumar Nigam,&nbsp;Bibhudendra Acharya,&nbsp;Adil Tanveer","doi":"10.1016/j.microrel.2025.115928","DOIUrl":"10.1016/j.microrel.2025.115928","url":null,"abstract":"<div><div>This article investigates the performance of graphene based electrostatic doped tunnel field-effect transistors (G-ED-TFET) for energy-efficient applications. In this design, the drain and source regions are induced by applying polarity gate (PG) bias voltages, respectively. This approach eliminates doping control issues, reduces thermal budget constraints, and simplifies fabrication compared to conventional TFETs. Graphene is utilized in the channel region as a promising alternative material to silicon (Si) due to exceptional characteristics such as high electron mobility and a zero band gap. The G-ED-TFET device achieve an ON current of 1.34 × <span><math><mrow><mn>1</mn><msup><mrow><mn>0</mn></mrow><mrow><mo>−</mo><mn>5</mn></mrow></msup></mrow></math></span> A/<span><math><mrow><mi>μ</mi><mi>m</mi></mrow></math></span>, threshold voltage (V<span><math><msub><mrow></mrow><mrow><mi>t</mi><mi>h</mi></mrow></msub></math></span>) of 0.32 V, subthreshold swing (SS) of 3.34 mV/decade, and a switching ratio of 2.86 × <span><math><mrow><mn>1</mn><msup><mrow><mn>0</mn></mrow><mrow><mn>14</mn></mrow></msup></mrow></math></span>. Analog/RF metrics suggest that their is minimum 10<span><math><mo>×</mo></math></span> improvement in every figure-of-metrics because graphene has an intrinsically small bandgap, which allows efficient tunneling from the P<span><math><msup><mrow></mrow><mrow><mo>+</mo></mrow></msup></math></span> source to the graphene channel. To further use of G-ED-TFET device, it is important to assess its reliability for which we have chosen interface trap charges (ITCs) approach. In the presence of ITCs, G-ED-TFET shows less variation, as compare to ED-TFET indicates that the G-ED-TFET is more reliable. Overall, this work offers significant insights into the analog/RF characteristics of G-ED-TFET, enabling the development of optimized devices and ensuring dependable performance in many applications.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"175 ","pages":"Article 115928"},"PeriodicalIF":1.9,"publicationDate":"2025-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145267477","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A quantitative analysis and testing assessment method for functional damage state of electronic circuits under impact loads","authors":"Dahai Li ,&nbsp;Li Long ,&nbsp;Peng Peng ,&nbsp;Zhaodong Lin ,&nbsp;Yongjian Zhang ,&nbsp;Cong Xu ,&nbsp;Changan Di ,&nbsp;Junsong Ren","doi":"10.1016/j.microrel.2025.115905","DOIUrl":"10.1016/j.microrel.2025.115905","url":null,"abstract":"<div><div>Focusing on the assessment of the functional damage state in electronic circuits under impact loads, this paper conducted research encompassing the analysis of damage scenarios, quantitative calculation of functional damage probabilities, and the construction of damage probability curve. Additionally, we developed a comprehensive set of quantitative analysis methods for assessing the functional damage state of electronic circuits. We designed a board-level drop impact test and monitored the dynamic response curves of circuit signals under impact loads in real time. Finally, we constructed the functional damage probability curve using the damage characteristic data from the circuit signals. These results verify the reasonableness and effectiveness of the proposed quantitative analysis and testing assessment method.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"175 ","pages":"Article 115905"},"PeriodicalIF":1.9,"publicationDate":"2025-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145050025","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Microstructure and analysis of Au-Pd-Ag alloy bonding wires for enhanced optocoupler packaging performance","authors":"Zhiqian Yang ,&nbsp;Kaixiang Hu ,&nbsp;Rongsong Ge ,&nbsp;Lite Zhao ,&nbsp;Tingting Jin ,&nbsp;Yizhan Chen","doi":"10.1016/j.microrel.2025.115907","DOIUrl":"10.1016/j.microrel.2025.115907","url":null,"abstract":"<div><div>This study investigates the microstructural characteristics and formation mechanisms in Au-Pd-Ag alloy bonding wires for optocoupler packaging. Bonding wires with different gold contents (20 %, 60 %, and 99.99 %) were analyzed using SEM and EDS. The results show that the alloy wire with 60 % gold content exhibits uniform elemental distribution and forms a stable layer at the bonding interface, significantly enhancing bonding strength and reliability. Under accelerated aging tests, including intermetalic compound highly accelerated stress test and high-temperature storage test, the alloy wire demonstrates excellent resistance to aging, with growth following a parabolic law. Optimizing the Au and Pd content effectively slows intermetallic compound (IMC) formation, improving long-term stability. Additionally, the optimized alloy composition enhances optocoupler performance by improving <em>Iceo</em> and <em>V</em>_<em>F</em> characteristics while reducing production costs. This study provides a high-performance alternative for optocoupler packaging and offers insights into the microstructural design and layer control of alloy bonding wires, advancing electronic packaging technology.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"175 ","pages":"Article 115907"},"PeriodicalIF":1.9,"publicationDate":"2025-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145050026","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}