Microelectronics Reliability最新文献

{"title":"Modelling thermomechanical degradation of moulded electronic packages using physics-based digital twin","authors":"A. Inamdar ,&nbsp;M. van Soestbergen ,&nbsp;A. Mavinkurve ,&nbsp;W.D. van Driel ,&nbsp;G.Q. Zhang","doi":"10.1016/j.microrel.2024.115416","DOIUrl":"https://doi.org/10.1016/j.microrel.2024.115416","url":null,"abstract":"<div><p>Semiconductor devices are commonly encapsulated with Epoxy-based Moulding Compounds (EMC) to form an electronic package. EMC typically occupies a large volume within a package, and thus, governs its thermomechanical behaviour. When exposed to high temperatures (150<!--> <!-->°C and above), electronic packages predominantly show oxidation of the outer layer of EMC. Oxidized EMC exhibits notably different material properties, resulting in a modified deformation pattern of a thermally aged package under varying thermal loads. As the oxidation layer grows in thickness, its mechanical properties also evolve, indicating distinct phases of the oxidized material at different stages of thermal ageing. Reflecting these changes (<em>i.e.</em>, the current state of degradation) into a Finite Element (FE) model-based analysis can provide better insights into failure prediction and component reliability. It requires updating the geometry and material behaviour as a function of ageing. This paper presents a systematic procedure to build a continuously updated physics-based Digital Twin of a thermally aged flip-chip package that can represent intermediate oxidation stages. First, experimental measurements are carried out to quantify the growth of the oxidation thickness at 150<!--> <!-->°C and a diffusion-dominant mathematical model is proposed. Then, an accurate geometry of the test package is prepared with a parametric outer layer from all exposed sides of EMC to represent the oxidized layer at different stages of thermal ageing. Next, the experimental characterization of a few partially oxidized EMC specimens is done, and analytical methods are utilized to extract the thermomechanical properties of the oxidized EMC at different stages of ageing. Experimental warpage data of aged test packages are utilized to verify the defined material-model parameters that represent curing shrinkage, thermal expansion, glass transition, and corresponding elasticity moduli of the oxidized EMC at select stages of ageing. Then, a workflow to establish continuity in the material model is presented. Finally, the developed Digital Twin is utilized for an FE analysis to study the change in the trend of out-of-plane package deformations as a function of several stages of EMC oxidation.</p></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"157 ","pages":"Article 115416"},"PeriodicalIF":1.6,"publicationDate":"2024-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://www.sciencedirect.com/science/article/pii/S0026271424000969/pdfft?md5=6ed972a9531e1625ff198ea30ce84567&pid=1-s2.0-S0026271424000969-main.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140917679","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"SiC Super-Junction MOSFET robustness assessment and method to improve avalanche capability","authors":"De-Xin Chen ,&nbsp;Ying Wang ,&nbsp;Yan-Xing Song ,&nbsp;Xin-Xing Fei ,&nbsp;Hao Huang","doi":"10.1016/j.microrel.2024.115418","DOIUrl":"https://doi.org/10.1016/j.microrel.2024.115418","url":null,"abstract":"<div><p>In this paper, the reliability of super-junction MOSFET under single-pulse Unclamped Inductive Switching (UIS) was simulated using Sentaurus TCAD software. Through simulation of etching source metal, it was proved that the conduction of parasitic bipolar transistor in parallel multi-cell structure is the main cause of temperature concentration leading to burnout. The method of reinforcing super-junction MOSFET is proposed by using the conduction of parasitic transistors as the criterion for evaluating UIS performance. In the proposed two-layer alternating PN column stack structure, the upper PN columns have a charge imbalance structure with a higher p-column concentration than the n-column. The simulation results show that the improved structure has higher avalanche energy and wider process variation range compared to the traditional structure. Compared with the traditional device, the improved device achieves a continuous avalanche duration of 1.3 × 10⁻³ s and an avalanche robustness of 8.24 joules (J) when the parasitic bipolar transistor is non-conductive, significantly reducing the process difficulty by increasing the P-base concentration deviation to 5.8 × 10¹⁷ cm⁻³ under the same avalanche duration range.</p></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"157 ","pages":"Article 115418"},"PeriodicalIF":1.6,"publicationDate":"2024-05-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140893746","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A low power TNU-resilient hardened latch design","authors":"Zhengfeng Huang ,&nbsp;Lei Ai ,&nbsp;Xinyu Jiang ,&nbsp;Zhouyu Gong ,&nbsp;Xiaolei Wang ,&nbsp;Yingchun Lu ,&nbsp;Tai Song ,&nbsp;Yiming Ouyang ,&nbsp;Aibin Yan","doi":"10.1016/j.microrel.2024.115417","DOIUrl":"https://doi.org/10.1016/j.microrel.2024.115417","url":null,"abstract":"<div><p>Technology scaling of integrated circuits into nanoscale feature sizes has decreased the effectiveness of existing single-node-upset and double-node-upset hardening techniques in harsh radiation environments. This paper proposes a low-power triple-node-upset resilient latch (LP-TNU) based on approximate C-elements and cross-interlocking structure. The proposed LP-TNU achieves TNU resilience based on the filtering feature of C-elements and redundant feedback structure. Extensive simulation results demonstrate the robustness of the proposed latch. The proposed LP-TNU achieves extremely low power consumption because of the clock-gating technique and fewer transistors. Compared with reference latches, the proposed latch is the most robust with the lowest power consumption and power-delay-product. In addition, compared with TNU-resilient latches such as DNUHL, LCTNURL, TNURL, HLTNURL and TNUSH, the proposed LP-TNU achieves a 62.68 % reduction on average in power consumption, 9.54 % reduction on average in delay, 20.75 % reduction on average in area overhead, 69.98 % reduction on average in the area-power-delay product. At the same time, the proposed latch is insensitive to variations of the process, supply voltage, and working temperature.</p></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"157 ","pages":"Article 115417"},"PeriodicalIF":1.6,"publicationDate":"2024-05-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140880652","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Techniques for detecting and masking faults in semantic segmentation applications","authors":"Stéphane Burel ,&nbsp;Adrian Evans ,&nbsp;Lorena Anghel","doi":"10.1016/j.microrel.2024.115397","DOIUrl":"https://doi.org/10.1016/j.microrel.2024.115397","url":null,"abstract":"<div><p>Semantic segmentation of images is essential for many applications including autonomous driving and modern DNNs now achieve high accuracy. Automotive systems are safety critical systems and in turn they must comply with safety standards, requiring at least hardware fault detection capability. Small embedded applications also require some level of fault tolerance, while operating with a tight power budget. In this paper, we first present a detailed analysis of the effects of faults using Google’s DeepLabV3+ network processing an industrial data-set. Further to that, two techniques to mitigate hardware faults are proposed. The first one is a symptom-based fault detection algorithm shown to detect <span><math><mo>&gt;</mo></math></span>99% of critical faults with zero false positives and a compute overhead of 0.2%. The second one is a simpler technique, using a clipped ReLU activation function, to quickly mask over 99% of the critical faults in the activation values.</p></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"157 ","pages":"Article 115397"},"PeriodicalIF":1.6,"publicationDate":"2024-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://www.sciencedirect.com/science/article/pii/S0026271424000775/pdfft?md5=ab7f5a1dc7df4567e359a7d1675b14ad&pid=1-s2.0-S0026271424000775-main.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140843308","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Effect of Creep, Fatigue and Random Vibration on the Integrity of Solder Joints in BGA Package","authors":"Joshua A. Depiver ,&nbsp;Sabuj Mallik ,&nbsp;Emeka H. Amalu","doi":"10.1016/j.microrel.2024.115415","DOIUrl":"https://doi.org/10.1016/j.microrel.2024.115415","url":null,"abstract":"<div><p>This study employs Finite Element Analysis (FEA) to investigate the effects of creep, fatigue, and random vibration on the integrity of solder joints in BGA packages in electronic modules. Evaluating the response of lead-based Sn63Pb37 and lead-free SnAgCu alloy solders (SAC305, SAC387, SAC396, and SAC405) to induced loads - stress, strain, strain energy density, and displacement in the joints is obtained and studied better to understand the mechanism of the joints' degradation. SAC305 and SAC405 are modelled with linear stress-temperature relationships σ = 3.152T–68.167 and σ = 1.543T–34.983, respectively. The magnitude of the strain energy density in the joints is a key failure driver. SAC387 and SAC396 solder joints display lower values of strain energy density and thus have higher durability. Displacement analysis indicates that SAC305 and Sn63Pb37 are prone to deformation-induced failure. SAC387 exhibits the highest fatigue yield stress at 58 MPa, while SAC405 displays the lowest stress at 22 MPa. Analysis of the results of random vibration shows that Sn63Pb37 developed the highest stress at 34.62 MPa and is thus susceptible to stress-induced failure. The robust stress, strain, and strain energy responses of SAC405 and SAC396 provide key insights into improving the mechanical reliability of future electronic devices towards better sustainability.</p></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"157 ","pages":"Article 115415"},"PeriodicalIF":1.6,"publicationDate":"2024-05-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://www.sciencedirect.com/science/article/pii/S0026271424000957/pdfft?md5=1e342a648621bd86b2ae1daf4abb2915&pid=1-s2.0-S0026271424000957-main.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140823929","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"An investigation into the thermal surface contact resistance, fin width and temperature on negative bias temperature instability during self-heating","authors":"Yan Liu ,&nbsp;Yanhua Ma ,&nbsp;Chong Pan","doi":"10.1016/j.microrel.2024.115414","DOIUrl":"https://doi.org/10.1016/j.microrel.2024.115414","url":null,"abstract":"<div><p>This work investigates the impacts of the thermal surface contact resistance (SR), fin width and temperature on the negative bias temperature instability (NBTI) during self-heating based on 14 nm p-FinFET through technology computer-aided design (TCAD) tool. In order to promote the accuracy of simulation, the experimental data are used to calibrate the TCAD results. The simulation results reveal that as SR increases, the lattice temperature rises by 20.07 %, which leads to a 15.84 % decrease of the carrier mobility and finally a reduction of the saturation current by 5.07 %. Moreover, as W_Fin decreases from 8 nm to 2 nm, the device threshold voltage increases by 15.41 %, resulting in that the saturation current reduces by 19.06 %. Besides, with an increase of the ambient temperature from 300 K to 500 K, the lattice temperature and trapped charge rise by 60.48 % and 12.53 %, respectively, which eventually leads to an 18.13 % decrease of the saturation current.</p></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"157 ","pages":"Article 115414"},"PeriodicalIF":1.6,"publicationDate":"2024-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140823928","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Numerical simulation approach for consideration of ageing effects in PCB substrates by modifying viscoelastic materials properties","authors":"Marius van Dijk ,&nbsp;Olaf Wittler ,&nbsp;Stefan Wagner ,&nbsp;Martin Schneider-Ramelow","doi":"10.1016/j.microrel.2024.115403","DOIUrl":"https://doi.org/10.1016/j.microrel.2024.115403","url":null,"abstract":"<div><p>During operating time of electronic systems, the used materials in such devices are potentially subjected to ageing effects, which might limit the lifetime. Therefore, knowledge about the used materials and the way the materials are affected by ageing effects is of key importance to develop reliable products.</p><p>In this study, a simulation approach is discussed that is able to consider ageing effects caused by oxidation at elevated temperature of a printed circuit board material, typically used for high frequency applications. The material was characterized for its thermomechanical properties with state-of-the-art techniques for different ageing durations. Ageing was accelerated by storing the samples in an oven at 175 °C for up to 1000 h.</p><p>Within the simulation workflow, the thermomechanical properties of the different aged states are defined by modifying the pristine viscoelastic properties. Four exponential functions are derived modifying the initial modulus, the characteristic time constants, the shift function and the coefficient of thermal expansion, all in dependency of ageing time.</p><p>To demonstrate the approach, the soldered interconnection lifetime of a theoretical chip-size-package on a printed circuit board is studied. State-of-the-art lifetime predictions of such interconnections only include thermomechanical ageing effects, for example by creep effects of the solder. By additionally considering the ageing of the printed circuit board, thermal ageing is combined with thermomechanical ageing.</p><p>Results in the soldered interconnection are compared between either considering additional ageing effects of the printed circuit board or neglecting this behavior. Thus it is shown that thermal ageing plays a significant role in the development of accumulated creep strain which becomes increasingly important with increasing expected lifetime.</p></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"157 ","pages":"Article 115403"},"PeriodicalIF":1.6,"publicationDate":"2024-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://www.sciencedirect.com/science/article/pii/S0026271424000830/pdfft?md5=6d9e3c765ccd7c64813fbc9720ff80b0&pid=1-s2.0-S0026271424000830-main.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140649360","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A highly reliable and low-overhead quadruple-node-upset tolerant latch design","authors":"Hui Xu ,&nbsp;Xiaodong Ai ,&nbsp;Ruijun Ma ,&nbsp;Huaguo Liang ,&nbsp;Zhengfeng Huang ,&nbsp;Jiuqi Li ,&nbsp;Lin Tang","doi":"10.1016/j.microrel.2024.115413","DOIUrl":"https://doi.org/10.1016/j.microrel.2024.115413","url":null,"abstract":"<div><p>With the advancement of semiconductor technology and the continual reduction in the feature size of transistors within integrated circuits (ICs), ICs are becoming more and more vulnerable to soft errors induced by energetic particles in harsh radiation environments. To mitigate the impact of soft error on ICs. This paper proposes a quadruple-node-upset tolerant latch (LCQNUT), which consists of two parts: a storage module and a three-stage interception module. The storage module is composed of 12 dual-input inverters. The three-stage interception module is composed of 6 dual-input C-elements (CEs). Based on the CEs and dual-input inverters' blocking capability, the proposed LCQNUT latch can efficiently tolerate the simultaneous upset of any four internal node combinations. Simulation results indicate the proposed LCQNUT latch has the smallest power consumption, area overhead, and area-power-delay product (APDP) compared to the latches with the same soft tolerance ability (D-LATCH, HS-QNU, QNUTL). It has moderate sensitivity to process, voltage, and temperature (PVT).</p></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"157 ","pages":"Article 115413"},"PeriodicalIF":1.6,"publicationDate":"2024-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140645205","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Effect of Co on microstructure evolution and thermal fatigue stability of lead-free solder alloys of SACBSN series","authors":"Zhendong Wang ,&nbsp;Jiaojiao Yang ,&nbsp;Jikang Yan ,&nbsp;Biao Wang ,&nbsp;Chongyan Leng ,&nbsp;Linyan Zhao","doi":"10.1016/j.microrel.2024.115395","DOIUrl":"https://doi.org/10.1016/j.microrel.2024.115395","url":null,"abstract":"<div><p>The majority of studies on high-reliability solder alloys have focused on the six-element system of Sn, Ag, Cu, Bi, Sb, and Ni. However, there is limited research on the influence of Co element within this system. In this study, a Sn<img>3.0Ag<img>0.5Cu<img>Bi<img>Sb<img>Ni<img>xCo (x = 0 wt%, 0.02 wt%, 0.05 wt%, 0.08 wt%, 0.1 wt%) alloy (referred to as SACBSN-xCo alloy) was prepared using a melting method. The mechanical properties of SACBSN-xCo alloy solder joints were evaluated through ultimate shear strength testing. The composition analysis of the alloy, phase composition examination, intermetallic compound (IMC) investigation and interfacial layer morphology analysis were conducted using ICP, XRD, SEM and EDS techniques respectively. Furthermore, the evolution process of solder structure and solder joint interface layer under different aging times was observed in detail. Results indicate that with the addition of Co element in the alloy solder system two heat release peaks appear during the solidification process; specifically when adding 0.05 wt% Co element content to the mixture it reduces supercooling degree by 15.17 °C to only 1.03 °C; Moreover wettability improvement can be achieved to some extent when adding either 0.02 wt% or 0.05 wt% Co content. The addition of trace Co can inhibit the excessive growth of IMC in the solder alloy matrix and refine the alloy structure. It can promote the growth of Cu₆Sn₅-based IMCs and inhibit the growth of Cu₃Sn layer in intermetallic compound layer (IMCs). In addition, the mechanical properties and thermal fatigue stability of the solder joints are steadily improved by Co element. After adding Co element, the shear strength of the alloy solder joint is increased by about 14.84 %. After aging at 150 °C for 25 days, the shear strength of SACBSN-xCo alloy solder joints is increased by about 20.4 %, which significantly improves the thermal fatigue stability of the solder joints after high temperature aging treatment. The results show that when Co content is 0.05 wt%, the alloy solder has better comprehensive properties.</p></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"157 ","pages":"Article 115395"},"PeriodicalIF":1.6,"publicationDate":"2024-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140645204","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Development of eutectic gallium-indium-based transparent conductive electrodes on flexible substrates for touch sensor integration","authors":"Hongseok Kim ,&nbsp;Youngjun Song ,&nbsp;Sung-pil Chang","doi":"10.1016/j.microrel.2024.115402","DOIUrl":"https://doi.org/10.1016/j.microrel.2024.115402","url":null,"abstract":"<div><p>In this study, the adaptability of liquid metal (LM)-based transparent conductive electrodes (TCEs) to flexible substrates and their potential applications in various electronics fields were investigated. To achieve this, conventional microfabrication techniques were employed to pattern polydimethylsiloxane (PDMS) channels and introduce an Eutectic Gallium-Indium (EGaIn) LM with the aim of enhancing transmittance and reducing sheet resistance. Microfluidic channel structures with varying pitch lengths and widths were fabricated in the types of grid patterns, labeled Pattern A (2000 μm pitch, 40 μm width), Pattern B (2000 μm pitch, 80 μm width), Pattern C (200 μm pitch, 40 μm width), and Pattern D (200 μm pitch, 80 μm width. The corresponding average transmittance values for the EGaIn LM-based TCE were 90 %, 71.8 %, 61.8 %, and 43.2 % for Patterns A, B, C, and D, respectively. To illustrate the potential in touch sensor applications, resistance changes in Patterns A, B, C, and D were assessed under applied forces ranging from 0 N to 150 N, revealing resistance changes of 0.0265 Ω, 0.03617 Ω, 0.03977 Ω, and 0.11629 Ω, respectively.</p></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"157 ","pages":"Article 115402"},"PeriodicalIF":1.6,"publicationDate":"2024-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140631857","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}