Nils Zöllner , Oliver Schilling , David Übelacker , Tobias Heise , Hans-Günter Eckel , University of Rostock
{"title":"Lifetime prediction for power modules in wind-energy converters based on temperature variations in a large area substrate solder connection","authors":"Nils Zöllner , Oliver Schilling , David Übelacker , Tobias Heise , Hans-Günter Eckel , University of Rostock","doi":"10.1016/j.microrel.2025.115665","DOIUrl":"10.1016/j.microrel.2025.115665","url":null,"abstract":"<div><div>Accurately modelling the lifetime of a power module is a major concern in wind power applications. Their lifetime is typically modelled via empirical laws fitted to data, e.g. from power cycling tests. Often, those models are parametrized with respect to junction temperatures due to its measurability and failure mechanisms occurring close to the chip. Nevertheless, some module types are limited by their large area substrate solder between the baseplate and substrate metallization. They motivate to choose the substrate solder temperatures for a lifetime model instead. Furthermore, transient effects are conceivable which lead to an ambiguous relation between substrate solder and junction temperatures. Thus, for such a model, a substitution of junction temperatures with substrate solder temperatures is carried out to derive a model based on substrate solder temperatures. Afterwards, the influence on lifetime estimation is investigated. For this purpose, the thermal behavior of a PrimePack™2.XT during power cycling is studied, utilizing reduced order models. Lifetime calculations with a junction and a substrate solder temperature-based model on a mission profile from a wind application show that the latter yields a significantly higher lifetime. A shift in the ratio between substrate solder temperature and junction temperature during operation towards a lower regime compared to the power cycling test is identified as the root cause for this. It is shown that from a physical perspective, this result is realistic and a lifetime modelling with respect to substrate solder temperatures increases the accuracy of lifetime prediction in this case.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"168 ","pages":"Article 115665"},"PeriodicalIF":1.6,"publicationDate":"2025-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143561560","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Fanpeng Zeng , Xinyu Wang , Tianlu Wang , Yingxin Cui , Kuan Yew Cheong , Handoko Linewih , Jisheng Han
{"title":"A failure mechanism of 1.2 kV/20 A 4H-SiC Schottky barrier diodes under humidity and high reverse bias voltage","authors":"Fanpeng Zeng , Xinyu Wang , Tianlu Wang , Yingxin Cui , Kuan Yew Cheong , Handoko Linewih , Jisheng Han","doi":"10.1016/j.microrel.2025.115674","DOIUrl":"10.1016/j.microrel.2025.115674","url":null,"abstract":"<div><div>SiC power devices have higher blocking voltage, lower on-resistance, and higher operating temperature than Si-based devices, which can be widely used in electric vehicles, rail transit, and high-voltage power transmission. However, the more severe application environments put higher demands on their reliability. In this paper, 1.2 kV/20 A SiC Schottky Barrier Diodes (SBDs) were evaluated after subjected to a series of reliability tests, including high-temperature storage (HTS), low-temperature storage (LTS), high-temperature reverse bias (HTRB) and high voltage, high humidity, high temperature reverse biased (HV-H<sup>3</sup>TRB) test. All devices passed the HTS, LTS and HTRB tests, but only 80 % of the devices passed the HV-H<sup>3</sup>TRB, which was mainly caused by pre-breakdown before 1200 V. Failure analysis showed that the breakdown point was located at the edge of the termination with cracks and delamination of the passivation layer were observed. Of 80 % of the failed devices after HV- H<sup>3</sup>TRB, almost all showed failure mode of passivation layer damage. With the root cause, the failure mechanism has been identified. This indicates that the passivation layer plays a critical role to determine the reliability of a SiC SBD device.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"168 ","pages":"Article 115674"},"PeriodicalIF":1.6,"publicationDate":"2025-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143552903","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Evidence of resistive switching in SiNx thin films for MEMS capacitors: The role of metal contacts","authors":"J. Theocharis, S. Gardelis, G. Papaioannou","doi":"10.1016/j.microrel.2025.115661","DOIUrl":"10.1016/j.microrel.2025.115661","url":null,"abstract":"<div><div>The impact of metal contacts on the electrical properties of SiN dielectric film in MEMS capacitors is investigated. The investigation is performed employing MIM and MEMS capacitors with Au and Ni contacts. A resistive switching like behaviour is monitored in the case of Ni contacts. This behaviour is attributed to the presence of deep traps in SiN and the effect of different metal contacts as revealed from Thermally Stimulated Depolarization Current (TSDC) assessment. Specifically, TSDC showed that the resistive switching is a contact/interface dominated effect.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"168 ","pages":"Article 115661"},"PeriodicalIF":1.6,"publicationDate":"2025-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143562345","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"System in package: Advanced FA techniques to minimize analysis time and cost","authors":"K. Szász, D. Luca","doi":"10.1016/j.microrel.2025.115675","DOIUrl":"10.1016/j.microrel.2025.115675","url":null,"abstract":"<div><div>Over the years packaging types of semiconductor devices have continued to evolve. One of the more complex package types in the Renesas portfolio is the System in Package or SIP. The SIP package presented in this paper features copper pillars, a three Cu layer substrate, passive components, it is overmolded and has a thin, exposed die. The large number of interfaces and components can lead to numerous potential failure locations. The failures addressed in this study are a result of humidity-related qualification processes. Due to the intricacies of the SIP package, following the failure analysis (FA) procedure of standard integrated circuit packages the analysis was fully destructive. These investigations were not only labour-intensive but also costly and could last up to a period of 2–3 weeks. As a result, an altogether new failure analysis approach, adjusted to the complexities of SiP packages was necessary to improve efficiency and accuracy.</div><div>In this case study, an innovative FA workflow is proposed, that includes advanced techniques including Lock-In Thermography and Computed Tomography scans. With the implementation of these methods, the analysis duration and cost were significantly reduced without compromising diagnostic accuracy. This work demonstrates the necessity of adapting FA methodologies to address the unique challenges of advanced packaging systems.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"168 ","pages":"Article 115675"},"PeriodicalIF":1.6,"publicationDate":"2025-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143562346","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Vertical scale-down of Cu/low-k interconnect development for BEOL reliability improvement of 12nm DRAM","authors":"J.H. Lee, B.W. Woo, Y.M. Lee, N.H. Lee, Y.Y. Lee, Y.S. Lee, S.B. Ko, S. Pae","doi":"10.1016/j.microrel.2025.115650","DOIUrl":"10.1016/j.microrel.2025.115650","url":null,"abstract":"<div><div>The effect of vertical scale-down of Cu interconnects on power consumption efficiency and back-end of the line (BEOL) reliability was investigated in 12nm DDR5 DRAM with four metal layers. The hydrostatic stress gradient, which drives stress migration (SM) failure was calculated using the finite element method, and it decreased in the scaled interconnect, thus leading to an improvement in the SM reliability. The time-dependent dielectric breakdown (TDDB) lifetime was also enhanced by the decrease in electric field between scaled Cu interconnects, which was demonstrated by both of the simulation and measurement. Although scaled interconnect could deteriorate the EM lifetime due to the increase in grain boundary, controlling the barrier metal thickness and utilizing advanced capping layer have compensated for the electro-migration (EM) deterioration. As a result, 12nm DDR5 DRAM meets 125°C BEOL reliability criteria while implementing low power through vertical scale-down of Cu interconnect.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"168 ","pages":"Article 115650"},"PeriodicalIF":1.6,"publicationDate":"2025-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143552901","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Cioni , G. Giorgino , A. Chini , N. Zagni , G. Cappellini , S. Principato , C. Miccoli , T. Wakrim , M.E. Castagna , A. Constant , F. Iucolano
{"title":"Effect of 2DEG density and Drain/Source Field Plate design on dynamic-RON of 650 V AlGaN/GaN HEMTs","authors":"M. Cioni , G. Giorgino , A. Chini , N. Zagni , G. Cappellini , S. Principato , C. Miccoli , T. Wakrim , M.E. Castagna , A. Constant , F. Iucolano","doi":"10.1016/j.microrel.2025.115666","DOIUrl":"10.1016/j.microrel.2025.115666","url":null,"abstract":"<div><div>The effect of 2DEG density and Drain/Source Field Plate design on dynamic-R<sub>ON</sub> of 650 V p-GaN gate AlGaN/GaN HEMTs is investigated in this work. Devices presenting three different AlGaN barrier and p-GaN layer design have been tested by means of Capacitance-Voltage measurements, Static V<sub>DS</sub> stress and Pulsed I-V characterization. C<img>V measurements allowed the extraction of 2DEG density, while Static V<sub>DS</sub> stress and Pulsed I-V put in evidence the partial recovery of the dynamic-R<sub>ON</sub> at high V<sub>DS,stress</sub>, potentially explained by a field-driven hole generation mechanism that partially compensates negatively ionized Carbon acceptors in the GaN Buffer. This hypothesis is in line with the trends observed for different 2DEG density and different drain field-plate designs, suggesting that a higher electric field under the drain terminal can significantly reduce R<sub>ON</sub>-degradation at high voltages, due to an easier holes generation. Furthermore, Pulsed I-V tests under resistive load switching mode have been addressed, highlighting the impact of the distance between source field plate and drain field plate on the dynamic-R<sub>ON</sub> degradation in conventional switch mode operations.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"168 ","pages":"Article 115666"},"PeriodicalIF":1.6,"publicationDate":"2025-03-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143552894","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Sorption getter characterization under wafer-level packaging (WLP) conditions","authors":"H. Duchemin, D. Bouchu","doi":"10.1016/j.microrel.2025.115677","DOIUrl":"10.1016/j.microrel.2025.115677","url":null,"abstract":"<div><div>Combination of Wafer Level Packaging (WLP) process with Non-Evaporated Getter (NEG) integration ensures the high-level vacuum hermetic packaging required for resonator based micro-electro-mechanical systems (MEMS) such as accelerometers or gyroscopes. In this article, we report a new characterization method to measure the NEG sorption efficiency under the replicated WLP process conditions, so as to ensure that the integration of NEG is well adapted to the overall MEMS fabrication process. We integrated this characterization protocol as a step in the MEMS process flow in order to ensure that the sealed getter remain fully functional through the WLP. Our approach is validated on hermetic packaged resonators, demonstrating an 80-fold quality factor (Q-factor) increase through NEG integration.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"168 ","pages":"Article 115677"},"PeriodicalIF":1.6,"publicationDate":"2025-03-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143552899","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A screening test of GaN-HEMTs for improvement of breakdown voltage uniformity","authors":"Wataru Saito, Shin-ichi Nishizawa","doi":"10.1016/j.microrel.2025.115643","DOIUrl":"10.1016/j.microrel.2025.115643","url":null,"abstract":"<div><div>As a screening test recipe, burst unclamped inductive switching (UIS) test is proposed to improve breakdown voltage uniformity. One of the critical disadvantages of GaN-HEMTs is its lack of the UIS withstanding capability, because there is no removal structure of holes, which generated by the avalanche breakdown. Hence, at the screening in the mass-production, measurement of the avalanche breakdown voltage cannot be employed to reject low breakdown voltage devices due to catastrophic failure, and conventional static drain leakage current measurements are insufficient. This paper reports a screening test of GaN-HEMTs by repetitive overvoltage stress using burst UIS test. The experimental results show the repetitive overvoltage stress was needed to reject outliers with low breakdown voltage and optimum test current avoided to generate new outliers.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"168 ","pages":"Article 115643"},"PeriodicalIF":1.6,"publicationDate":"2025-03-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143552898","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Bernardoni, R. Illing, M. Tripolt, C. Djelassi-Tscheck
{"title":"SMART protection design of automotive power distribution systems with temperature-based electronic fuses: Mathematical background, design guidelines and drawbacks of energy-based methods","authors":"M. Bernardoni, R. Illing, M. Tripolt, C. Djelassi-Tscheck","doi":"10.1016/j.microrel.2025.115635","DOIUrl":"10.1016/j.microrel.2025.115635","url":null,"abstract":"<div><div>This work presents an overview on the power distribution design requirements in automotive power distribution systems, with focus on wire harness protections. While standard melting fuses are still widely used in automotive power distribution systems, the complexity of the future automotive platforms can be enabled only by replacing melting fuses with electronic protections. This paper will analyze the typical design requirements in terms of wire protection, which electronic protections concepts are available and how a safe wire protection can be ensured. Moreover, we introduce a correct mathematical transformation that describes the effect of a given load current onto the considered thermal system (wire or eFuse), allowing the correct representation of load, eFuse, and wire, in the isothermal domain.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"168 ","pages":"Article 115635"},"PeriodicalIF":1.6,"publicationDate":"2025-03-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143552900","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Selective hardening of RISCV soft-processors for space applications","authors":"G. Cora, C. De Sio, S. Azimi, L. Sterpone","doi":"10.1016/j.microrel.2025.115667","DOIUrl":"10.1016/j.microrel.2025.115667","url":null,"abstract":"<div><div>RISC-V soft processors are becoming popular in various fields, including safety-critical ones, thanks to their open-source nature and flexibility. Despite the rapid progress in the reliability analysis of these devices, all the mitigation techniques are usually adopted to the whole soft-processor architecture.</div><div>In this study, we aim to identify the internal components of the RISC-V architecture that are particularly prone to errors, and accordingly investigate how the reliability of the design is affected when mitigation strategies, such as Triple Modular Redundancy (TMR), are applied selectively just to them.</div><div>The proposed approach has been applied to RISC-V architecture, NEORV32 which is implemented on Zynq 7020 SoC on a PYNQ-Z2 board. While more vulnerable modules of NEORV32 were identified through accurate reliability analysis, implementing selective TMR in these modules shows achieving satisfactory reliability levels while reducing the overall space requirements compared to a complete TMR design.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"167 ","pages":"Article 115667"},"PeriodicalIF":1.6,"publicationDate":"2025-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143534754","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}