Microelectronics Reliability最新文献_第9页

Influences of deformation defects on etching behaviors of high-strength and high-conductivity Cu alloy for lead frame 变形缺陷对铅框用高强度、高导电率铜合金蚀刻行为的影响

IF 1.6 4区工程技术

Microelectronics Reliability Pub Date : 2024-06-20 DOI: 10.1016/j.microrel.2024.115448

Jinyang Fang , Qingke Zhang , Jing Li , Feng Liu , Chaofeng Li , Lijing Yang , Cheng Xu , Zhenlun Song

{"title":"Influences of deformation defects on etching behaviors of high-strength and high-conductivity Cu alloy for lead frame","authors":"Jinyang Fang , Qingke Zhang , Jing Li , Feng Liu , Chaofeng Li , Lijing Yang , Cheng Xu , Zhenlun Song","doi":"10.1016/j.microrel.2024.115448","DOIUrl":"https://doi.org/10.1016/j.microrel.2024.115448","url":null,"abstract":"<div><p>With increasing integration of the semiconductor devices, the requirements on size accuracy and surface quality of the lead frame are higher. Cold-rolling and low-temperature aging are usually used in processing of the Cu alloy for lead frame, which generate/eliminate the deformation defects that affect the etched surface morphology and roughness, while the influence mechanisms have not been well revealed. In this study, the CuCrSn alloy was used as the experimental material, which was cold-rolled to different degree and then aged at 450 °C for different time, and the microstructures and etched surfaces of the specimens were characterized. The results show that etched surface morphologies of grains with different orientations in the coarse-grained Cu alloy are different. With increasing cold-rolling deformation, the influences of grain orientation become less obvious, and the dislocation groups on the slip planes result in grooves approximately parallel to the rolling direction, meanwhile the surface uniformity are improved and the surface roughness decreases. For the 80 % cold-rolled Cu alloy, the density of grooves decreases with increasing aging time and elimination of the dislocations, and the etched surface roughness decreases firstly and then tends to be stable. The etched surface changes significantly and the surface roughness increase obviously after recrystallization of the specimen.</p></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"159 ","pages":"Article 115448"},"PeriodicalIF":1.6,"publicationDate":"2024-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141433811","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Design and power optimization of a QCA-based universal reversible logic gate architecture using cell interaction approach 利用单元交互方法设计基于 QCA 的通用可逆逻辑门架构并优化其功耗

IF 1.6 4区工程技术

Microelectronics Reliability Pub Date : 2024-06-20 DOI: 10.1016/j.microrel.2024.115446

Aamir Suhail Taray , Satyendra Kumar Singh , Yogesh Singh , Farah Naaz , Purnima Hazra

{"title":"Design and power optimization of a QCA-based universal reversible logic gate architecture using cell interaction approach","authors":"Aamir Suhail Taray , Satyendra Kumar Singh , Yogesh Singh , Farah Naaz , Purnima Hazra","doi":"10.1016/j.microrel.2024.115446","DOIUrl":"https://doi.org/10.1016/j.microrel.2024.115446","url":null,"abstract":"<div><p>This paper introduces a new design for 3 <strong>×</strong> 3 universal and reversible Logic Gate, namely RLG-QCA (reversible logic gate-quantum dot cellular automata) which is implemented using QCA technology. The basic concept of our design is based on the majority voter gate approach (MVA). The suggested gate is designed, simulated and optimized using an accurate QCA cell interaction approach. The proposed gate has no crossover. It has a total area of 0.0311 μm<sup>2</sup> and a latency of 0.5 time period only. To validate its universality, all seven primary logic gates and thirteen Boolean algorithms are realized using the proposed RLG-QCA logic gate. Then a one-bit full adder circuit is constructed with only two numbers of proposed universal logic gates and one coplanar cell crossover. The proposed architecture seems to be an ultra-efficient and stable one with a total cell count of 53 and total cell area of 0.0175 μm<sup>2</sup> and only. Finally, the energy dissipation analysis is also performed on the proposed RLG-QCA gate as well as full adder circuit at different energy levels to confirm the sustainability and suitability of the proposed gate in ultra-low power design applications. The results exhibit extremely low energy dissipation which is an added advantage of the proposed design in implementation of digital circuits with low power dissipation.</p></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"159 ","pages":"Article 115446"},"PeriodicalIF":1.6,"publicationDate":"2024-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141433812","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Numerical investigation of printed circuit board response during solder float test: Influence of thermal boundary conditions 浮焊测试期间印刷电路板响应的数值研究：热边界条件的影响

IF 1.6 4区工程技术

Microelectronics Reliability Pub Date : 2024-06-20 DOI: 10.1016/j.microrel.2024.115441

Paul Perin, Gautier Girard, Marion Martiny, Sébastien Mercier

{"title":"Numerical investigation of printed circuit board response during solder float test: Influence of thermal boundary conditions","authors":"Paul Perin, Gautier Girard, Marion Martiny, Sébastien Mercier","doi":"10.1016/j.microrel.2024.115441","DOIUrl":"https://doi.org/10.1016/j.microrel.2024.115441","url":null,"abstract":"<div><p>During qualification, a Printed Circuit Board (PCB) must pass several electrical and thermomechanical tests. Among the tests required by the European Cooperation for Space Standardization (ECSS), the solder float test consists in resting a sample on a 288 °C solder bath. In order to simulate and better understand the latter, the heat transfer coefficient (HTC) of the PCB/solder bath interface has to be characterized.</p><p>In this work, an experimental setup has been developed to measure the HTC of the interface between SnPb and a horizontal surface. In addition, a finite element model of the solder float test has been developed in order to study the temperature and stress fields inside the PCB. The temperature field is highly heterogeneous at the beginning of the heating. A direct consequence of this early temperature heterogeneity is the development of stress fields that can be correlated to the observed failure modes. A parametric study revealed the sensitivity of the stress and strain development to changes in the HTC value. The difference observed in finite element simulations between isothermal assumptions and transient regime holds true for any maximum temperature in the range of 100 °C to 288 °C. The present work highlights the importance of considering exact thermal boundary conditions when studying the reliability of PCBs under thermal loading (especially with fast changes).</p></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"159 ","pages":"Article 115441"},"PeriodicalIF":1.6,"publicationDate":"2024-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141433859","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

The collector current model of the IGBT based on the gate charge 基于栅极电荷的 IGBT 集电极电流模型

IF 1.6 4区工程技术

Microelectronics Reliability Pub Date : 2024-06-19 DOI: 10.1016/j.microrel.2024.115432

Li Guan , Peng Zeng , Xin Zhang , Qi Li , Yonghe Chen , Jianghui Zhai , Feng Zhang , Baozheng Yang , Xianwen Cui , Jian Ye , Shi Cheng

{"title":"The collector current model of the IGBT based on the gate charge","authors":"Li Guan , Peng Zeng , Xin Zhang , Qi Li , Yonghe Chen , Jianghui Zhai , Feng Zhang , Baozheng Yang , Xianwen Cui , Jian Ye , Shi Cheng","doi":"10.1016/j.microrel.2024.115432","DOIUrl":"https://doi.org/10.1016/j.microrel.2024.115432","url":null,"abstract":"<div><p>In this study, a dynamic and static collector current (I<sub>C</sub>) model of the IGBT based on the gate charge is proposed. The gate charge could be easily obtained by measuring the voltage across the gate mirror circuit capacitance, and the transconductance obtained from the I<sub>C</sub>–V<sub>GE</sub> curve is mainly used. This model does not need the device structure parameters such as doping concentration, length, and thickness, thus is low cost and highly convenient. First, the gate charge is derived by integrating the currents of the variable capacitors C<sub>GE</sub> and C<sub>GC</sub> during the turn-on and turn-off transients, and an analytical relationship between the dynamic I<sub>C</sub> and Q<sub>G</sub> is researched. Second, a static collector current I<sub>C</sub> is established, and the gate charge is obtained through current integration during the period of the Miller capacitance plateau. The influence of the temperature on the static transconductance is studied, and the accuracy of the static current model is improved. Finally, the performance of the model is optimized with various voltages, temperatures, and currents. The experimental results reveal that the proposed model achieves a collector current error of less than 5.6 % under various operating conditions, which verifies the accuracy of the proposed model.</p></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"159 ","pages":"Article 115432"},"PeriodicalIF":1.6,"publicationDate":"2024-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141429162","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Effects of co-60 gamma-ray irradiation on the DC and RF characteristics of SiGe HBTs 共 60 伽玛射线辐照对 SiGe HBT 直流和射频特性的影响

IF 1.6 4区工程技术

Microelectronics Reliability Pub Date : 2024-06-17 DOI: 10.1016/j.microrel.2024.115443

Guofang Yu, Jie Cui, Yue Zhao, Wenpu Cui, Jun Fu

{"title":"Effects of co-60 gamma-ray irradiation on the DC and RF characteristics of SiGe HBTs","authors":"Guofang Yu, Jie Cui, Yue Zhao, Wenpu Cui, Jun Fu","doi":"10.1016/j.microrel.2024.115443","DOIUrl":"https://doi.org/10.1016/j.microrel.2024.115443","url":null,"abstract":"<div><p>This study investigates the effects of Co-60 gamma-ray irradiation on the DC and RF characteristics of the SiGe HBTs, with a total dose of up to 4000 krad(Si). The degradation of the forward base current is primarily attributed to surface recombination due to the induced interface traps. The ideality factor of the forward excess base current is affected by the positive oxide-trapped charges at the interface of the emitter-base spacer oxide. TCAD simulation results indicate that the effective integral region of the surface recombination rate is associated with the positive oxide-trapped charge density. The accumulation of positive oxide-trapped charges in the shallow trench isolation oxide has an impact on the potentials of the interface and epi-collector region, subsequently affecting the base diffusion current. Therefore, the ideality factor of the reverse excess base current depends on the device geometry. The RF characterization suggests that the depletion capacitance of the base-emitter junction is more susceptible to gamma-ray irradiation compared to the base-collector junction. And the cut-off frequency experiences a slight degradation as the total dose increases.</p></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"159 ","pages":"Article 115443"},"PeriodicalIF":1.6,"publicationDate":"2024-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141424487","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A diagnostic strategy for IGBT open-circuit faults in modular multilevel converters based on improved diagnostic indices 基于改进诊断指数的模块化多电平转换器 IGBT 开路故障诊断策略

IF 1.6 4区工程技术

Microelectronics Reliability Pub Date : 2024-06-15 DOI: 10.1016/j.microrel.2024.115444

Hong Wu , Yue Wang , Yi Liu , Xuan Li , Runtian Li , Yufei Li

{"title":"A diagnostic strategy for IGBT open-circuit faults in modular multilevel converters based on improved diagnostic indices","authors":"Hong Wu , Yue Wang , Yi Liu , Xuan Li , Runtian Li , Yufei Li","doi":"10.1016/j.microrel.2024.115444","DOIUrl":"https://doi.org/10.1016/j.microrel.2024.115444","url":null,"abstract":"<div><p>Capacitor voltage deviations between two submodules (SMs) are always used as the diagnostic index for the insulated gate bipolar transistor (IGBT) open-circuit fault diagnosis in modular multilevel converters (MMCs). However, it is difficult to determine when MMCs operate in different conditions. To solve this issue, this article proposes a diagnostic strategy for IGBT open-circuit faults in MMCs based on improved diagnostic indices. First, two diagnostic indices, i.e., the concept of the count of periods during which the switching function is fixed (CSF) and capacitor voltage sorting sequence number (CSN) are proposed. On this basis, fault detection is implemented by judging the changing trend of the CSN in the SM whose CSF is the highest. The remaining malfunctioning SMs are located in turns by a similar process to fault detection. The proposed diagnostic indices show consistent faulty characteristics under different operating conditions, thus avoiding readjusting the threshold according to different operating conditions. In this sense, the proposed strategy can be easily used and promoted in different operating scenarios. Experimental results in a hardware-in-the-loop (HIL) platform verify the effectiveness of the proposed strategy.</p></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"159 ","pages":"Article 115444"},"PeriodicalIF":1.6,"publicationDate":"2024-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141328827","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Transient thermal 2D FEM analysis of SiC MOSFET in short-circuit operation including high-temperature material laws and phase transition of aluminum source electrode 碳化硅 MOSFET 短路工作时的瞬态热 2D FEM 分析，包括高温材料定律和铝源电极的相变

IF 1.6 4区工程技术

Microelectronics Reliability Pub Date : 2024-06-14 DOI: 10.1016/j.microrel.2024.115440

Mustafa Shqair, Emmanuel Sarraute, Thibauld Cazimajou, Frédéric Richardeau

{"title":"Transient thermal 2D FEM analysis of SiC MOSFET in short-circuit operation including high-temperature material laws and phase transition of aluminum source electrode","authors":"Mustafa Shqair, Emmanuel Sarraute, Thibauld Cazimajou, Frédéric Richardeau","doi":"10.1016/j.microrel.2024.115440","DOIUrl":"https://doi.org/10.1016/j.microrel.2024.115440","url":null,"abstract":"<div><p>Understanding the electrothermal behavior of SiC MOSFET power devices under extreme operation conditions, such as short circuits, is crucial for their application certification. However, simulating short circuits in electronic components is challenging due to the necessity of a comprehensive thermal and electrical Multiphysics model that incorporates material laws and respects elevated temperatures with broad ranges. It is also needed to model the melting of the topside Al electrode. The paper presents for the first time a 2D electrothermal FEM that simulates the thermodynamic behavior of SiC MOSFET at high temperatures transistors under short-circuit conditions, including wide-range temperature-dependent material property laws. This work models the Al phase transition by considering the apparent heat capacity method and including the latent heat absorbed during the Al solid-liquid phase change (PC). The geometric accuracy of this study provides significant added values compared to existing 1D models. It was deduced that including the temperature-dependent material laws highly impacted the results. The rise in SiC junction temperature led to a delay in the onset of Al melting. It also impacted the progression manner of the Al melting process after the formation of new melting fronts.</p></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"159 ","pages":"Article 115440"},"PeriodicalIF":1.6,"publicationDate":"2024-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141328826","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Optical, electrical, and mechanical reliability of 1700 PPI Micro-LED device 1700 PPI Micro-LED 器件的光学、电气和机械可靠性

IF 1.6 4区工程技术

Microelectronics Reliability Pub Date : 2024-06-03 DOI: 10.1016/j.microrel.2024.115431

Kefeng Wang , Zehua Chen , Haojie Zhou , Xiaoxiao Ji , Xiuzhen Lu , Luqiao Yin , Jianhua Zhang

{"title":"Optical, electrical, and mechanical reliability of 1700 PPI Micro-LED device","authors":"Kefeng Wang , Zehua Chen , Haojie Zhou , Xiaoxiao Ji , Xiuzhen Lu , Luqiao Yin , Jianhua Zhang","doi":"10.1016/j.microrel.2024.115431","DOIUrl":"https://doi.org/10.1016/j.microrel.2024.115431","url":null,"abstract":"<div><p>With the Micro-LED display device being widely used in the advanced display fields, the high reliability of device had become one of the key issues for applications of Micro-LED in many display fields such as VR/AR, portable displays, and flexible displays. The 512 × 384 green Micro-LEDs 0.39 in. array with 1700 PPI featuring a pixel pitch of 15 μm was integrated with the substrate by the Au<img>In flip-chip bonding. The average brightness, electroluminescence (EL) spectra, and I-V characteristics of the Micro-LED device aged at 85 °C/85 % RH for different time were measured to evaluate the optical and electrical reliability of the Micro-LED device. The mechanical reliability of the Micro-LED device after 336 h of aging was evaluated by shear test. The average brightness of the Micro-LED device decreased from 2.08 × 10<sup>4</sup> nit to 1.64 × 10<sup>4</sup> nit and the on-resistance of the Micro-LED device increased from 2.30 Ω to 2.82 Ω with the aging time increased to 336 h. The Micro-LED device was broken up with the shear strength value of 12.06 MPa, and the shear strength was only reduced by 8.25 % compared with that measured before aging.</p></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"158 ","pages":"Article 115431"},"PeriodicalIF":1.6,"publicationDate":"2024-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141243326","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Fault and self-repair for high reliability in die-to-die interconnection of 2.5D/3D IC 通过故障和自我修复实现 2.5D/3D 集成电路芯片间互连的高可靠性

IF 1.6 4区工程技术

Microelectronics Reliability Pub Date : 2024-06-03 DOI: 10.1016/j.microrel.2024.115429

Renhao Song, Junqin Zhang, Zhanqi Zhu, Guangbao Shan, Yintang Yang

{"title":"Fault and self-repair for high reliability in die-to-die interconnection of 2.5D/3D IC","authors":"Renhao Song, Junqin Zhang, Zhanqi Zhu, Guangbao Shan, Yintang Yang","doi":"10.1016/j.microrel.2024.115429","DOIUrl":"https://doi.org/10.1016/j.microrel.2024.115429","url":null,"abstract":"<div><p>Bringing dies closer by die-to-die interconnection is a way that reduces latency and energy per bit transmitted, while increasing bandwidth per mm of chip. Heterogeneous integration using 2.5D/3D architectures enables disaggregation of package into various components such as input/output (IO), memory, process, and accelerator. These different functional components may be dies designed and manufactured by different companies, and multiple dies are integrated and interconnected in a package to form a multi-die system. In a multi-die package, these dies are connected using through silicon via (TSV) stacking or re-distribution layer (RDL) and TSV in the interposer according to communication protocols. However, it makes the electrical failure of its interconnection have a greater impact on reliability. Unlike interconnection of traditional integrated circuit (IC), it will bring many new challenges for fault detection and self-repair in 2.5D/3D IC. In this paper, according to unique characteristics of the die-to-die interconnection, we analyze it in top-down approach. The relevant researches on architecture, fabrication, the defect introduced, fault detection, re-routing and functional post-repair are introduced. At the end of this paper, the challenges and solutions in every stage are concluded, and the future perspectives of high reliability in die-to-die interconnection of the 2.5D/3D IC are presented.</p></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"158 ","pages":"Article 115429"},"PeriodicalIF":1.6,"publicationDate":"2024-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141243327","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Study of the high-k/SiO2 stacked gate micro-pattern trench CSTBT 高 k/SiO2 叠层栅极微图案沟槽 CSTBT 研究

IF 1.6 4区工程技术

Microelectronics Reliability Pub Date : 2024-05-27 DOI: 10.1016/j.microrel.2024.115428

Ang Li, Xiaoliang Mo

{"title":"Study of the high-k/SiO2 stacked gate micro-pattern trench CSTBT","authors":"Ang Li, Xiaoliang Mo","doi":"10.1016/j.microrel.2024.115428","DOIUrl":"https://doi.org/10.1016/j.microrel.2024.115428","url":null,"abstract":"<div><p>To alleviate the challenge of threshold voltage (<em>V</em><sub>TH</sub>) variations in carrier stored trench-gate bipolar transistor (CSTBT) induced by the CS layer and to prevent erroneous turn-on of CSTBT at elevated temperatures, we propose a high-<em>k</em>/SiO<sub>2</sub> stacked gate dielectric layer structure for CSTBT, termed HKO-CSTBT. Due to the effect of the high-<em>k</em> material reducing the <em>V</em><sub>TH</sub>, HKO-CSTBT enables the adoption of a higher P-body doping concentration. While keeping the <em>V</em><sub>TH</sub> unchanged, HKO-CSTBT increase the doping concentration difference between the CS layer and the P-body, and diminishes the influence of the CS layer on the channel region. This leads to a more uniform <em>V</em><sub>TH</sub> across different cells or devices under specific ion implantation errors, reducing <em>V</em><sub>TH</sub> deviation by over 65 %. This consistency is advantageous for the parallel configuration of devices. Employing a high-<em>k</em> material as the dielectric layer also decreases the absolute value of the device's <em>V</em><sub>TH</sub> temperature coefficient. At a temperature of 450 K, the <em>V</em><sub>TH</sub> of the HKO-CSTBT is 0.237 V higher than its conventional counterpart, favoring its operation under elevated temperature. Furthermore, at elevated temperatures, when a high voltage is applied to the collector-emitter, the excellent dielectric properties of the high-k material results in a reduced electric field peak at the bottom of the gate. The HKO-CSTBT also allows a higher CS layer ion implantation dose, subsequently decreasing the on-state saturation voltage (<em>V</em><sub>CE(sat)</sub>). In short, unlike the previous high-<em>k</em> materials used in power devices only to improve the super-junction technology, this paper presents a new application and function of high-<em>k</em> materials in power devices.</p></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"158 ","pages":"Article 115428"},"PeriodicalIF":1.6,"publicationDate":"2024-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141156407","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0