Microelectronics Reliability最新文献

{"title":"Study on electron and gamma irradiation effects and damage mechanism of GaN HEMT","authors":"Hongxia Li ,&nbsp;Hongping Guo ,&nbsp;Rongxing Cao ,&nbsp;Hui Tu ,&nbsp;Xin Huang ,&nbsp;Yuxiong Xue ,&nbsp;Xianghua Zeng","doi":"10.1016/j.microrel.2025.115616","DOIUrl":"10.1016/j.microrel.2025.115616","url":null,"abstract":"<div><div>Electron and gamma irradiation experiments were carried out on GaN HEMT(High Electron Mobility Transistor) devices, the total dose effect of different irradiation sources was studied, and the difference of radiation damage to the device was analyzed. The test results show that the threshold voltage of the device has negative drift after electron irradiation, the drain current increases obviously, and the threshold voltage deviation increases with the increase of irradiation dose. The trends observed in gamma and electron irradiation are analogous; however, at an identical irradiation dose, the total dose effect elicited by gamma irradiation is more prominent. In order to compare the effects of electron and gamma irradiation on the device, the annealing effects of different irradiation sources at the same time were compared and analyzed. It is found that the annealing effect of gamma irradiation devices is more obvious than that of electron irradiation devices under the same irradiation dose and annealing time. The simulation results show that the electric field intensity, electron and hole concentration in the device after gamma irradiation were greater than that generated by electron irradiation under the same condition.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"167 ","pages":"Article 115616"},"PeriodicalIF":1.6,"publicationDate":"2025-02-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143464508","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Assessment of the solidification behavior and microhardness of Sb-modified Sn-Ag alloys","authors":"Pâmella Raffaela Dantas de Freitas ,&nbsp;Bruno Silva Sobral ,&nbsp;Raí Batista de Sousa ,&nbsp;Jeverton Laureano Paixão ,&nbsp;Zulmara Virginia de Carvalho ,&nbsp;José Eduardo Spinelli ,&nbsp;Bismarck Luiz Silva","doi":"10.1016/j.microrel.2025.115624","DOIUrl":"10.1016/j.microrel.2025.115624","url":null,"abstract":"<div><div>The present study aims to analyze the effect of antimony (Sb) additions (0.2 % and 2.0 % in wt.%) on the microstructure solidification parameters (cooling rate and growth rate), temperatures related to phase transformation, macrosegregation and microhardness of the Sn-2.0 wt% Ag alloy. The samples have been characterized using techniques such as Optical Microscopy (OM), Scanning Electron Microscopy (SEM), X-ray Fluorescence (XRF), X-ray Diffraction (XRD) and Vickers microhardness. Thermodynamic calculations were also performed in order to study the evolution of the solidification and the phase fractions. The microstructures of the Sn-Ag-Sb alloys are completely dendritic with a Sn-rich matrix (β-Sn) surrounded by a eutectic mixture, β-Sn + Ag₃Sn. The additions of Sb promoted a slight microstructural refinement and a slight increase in <em>liquidus</em> and <em>solidus</em> temperatures, when compared to the binary alloy. Ag₃Sn intermetallics showed fibrous and spherical morphologies, with spherical dominating at cooling rate Ṫ_L &gt; 5.1 °C/s and Ṫ_L &gt; 2.9 °C/s for 0.2 wt.% Sb and 2.0 wt.% Sb, respectively. The Sb increased Vickers microhardness, particularly in the Sn-Ag-2wt.%Sb alloy due to solid-solution and dendritic refinement strengthening.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"167 ","pages":"Article 115624"},"PeriodicalIF":1.6,"publicationDate":"2025-02-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143454225","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Numerical evaluation of radiation degradation for P-MOSFET power devices under total ionizing dose effect","authors":"Na-Yeon Choi,&nbsp;Sung-Uk Zhang","doi":"10.1016/j.microrel.2025.115627","DOIUrl":"10.1016/j.microrel.2025.115627","url":null,"abstract":"<div><div>In this study, the degradation of electrical and thermal properties of a packaged power semiconductor device due to cumulative radiation dose was numerically evaluated using electrical-thermal simulations. Si P-channel MOSFET devices were irradiated stepwise using a cobalt-60 gamma source. The changes in the electrical performance of the irradiated devices and the changes in the thermal conductivity of the encapsulation were identified. In addition, the changes in the thermal and electric properties of equivalent chips with changes in drain current and encapsulation surface temperature were numerically analyzed using electric-thermal multi-physics analysis. The results revealed that with the cumulative radiation dose rising from zero to 3000 krad, the chip's equivalent resistance increased significantly by 442.66 %, from 1.301 to 7.06 Ω∙mm. Concurrently, thermal conductivity decreased by 88.53 %, from 24.27 to 2.96 W/m∙K, and thermal resistance increased by 391 %, from 4.14 °C/W to 20.33 °C/W. These results quantitatively establish the degradation of electrical and thermal behavior of packaged P-channel Si MOSFETs due to radiation, as calculated by finite element analysis.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"167 ","pages":"Article 115627"},"PeriodicalIF":1.6,"publicationDate":"2025-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143454891","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Solving bump bonding issues with 2.0 mil copper wire: A study on FSM integration and workability improvements","authors":"Hao-Lin Yen,&nbsp;Fang-I Lai","doi":"10.1016/j.microrel.2025.115628","DOIUrl":"10.1016/j.microrel.2025.115628","url":null,"abstract":"<div><div>Bump bonding with 2.0 mil copper (Cu) wire presents significant workability challenges when using aluminum (Al) pads alone, regardless of thickness. To address these issues, this study evaluates the integration of Front-Side Metal (FSM) layers (Ti/NiV/Ag) and their impact on process performance. Two Al pad thicknesses (0.8 μm and 3.0 μm) were tested in combination with two FSM configurations (1 k/3 k/1.5 k Å and 1 k/3 k/6 k Å) to assess process windows, defect rates, and reliability metrics. The results confirm that FSM layers are essential for enabling successful bump bonding with 2.0 mil Cu wire. The 0.8 μm Al pad with 1 k/3 k/6 k FSM demonstrated superior workability, achieving a ± 15 % process window, compared to the ≤ ±5–10 % range observed in other configurations. Defect rates were also significantly lower (&lt;3 %) compared to 13–36 % in alternative configurations. A key factor influencing workability was the non-stick on pad (NSOP) rate, which was significantly reduced in the 0.8 μm Al pad with 1 k/3 k/6 k FSM configuration. The thicker Ag layer in this combination improved bond formation by enhancing energy transfer and stress distribution, minimizing bond pad contamination and adhesion failures. Other configurations, particularly those with thinner Ag layers or thicker Al pads, exhibited higher NSOP rates, leading to narrower process windows and increased defect rates. Reliability assessments, including Moisture Sensitivity Level (MSL) tests and Scanning Acoustic Tomography (SAT) analysis, confirmed that all configurations exhibited no delamination or structural failures. Final test results showed yield rates of 99–100 % for the 0.8 μm Al pad with 1 k/3 k/6 k FSM, while other configurations had slightly lower yields (97–100 %). Additionally, all configurations passed cratering tests, further validating the robustness of the FSM-integrated process. This study demonstrates that FSM layers are critical in overcoming workability limitations in 2.0 mil Cu wire bump bonding. The findings emphasize the importance of optimizing both Al pad thickness and FSM layer composition to enhance manufacturability and reliability in advanced copper wire bonding applications.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"167 ","pages":"Article 115628"},"PeriodicalIF":1.6,"publicationDate":"2025-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143444887","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Application of IGBT junction temperature estimation in hybrid electric vehicles","authors":"Tianyu Ma,&nbsp;Bowen Yan,&nbsp;Bin Liu,&nbsp;Jun Liu","doi":"10.1016/j.microrel.2025.115629","DOIUrl":"10.1016/j.microrel.2025.115629","url":null,"abstract":"<div><div>The Insulated Gate Bipolar Transistor (IGBT) is a crucial component in hybrid electric vehicle electric drive systems. Estimating the IGBT junction temperature is essential for forecasting its lifespan and managing the heat within the power module. This paper presents and applies two methods for predicting IGBT junction temperature: the thermal network model and the empirical relationship method. Among them, the thermal impedance method is analyzed and extended to engine application by introducing a coefficient <em>β</em> = f (speed, coolant boundary). The empirical relationship is first proposed considering the effect of thermal boundary. Both methods are applied in CHANGAN Plug-in Hybrid Electric Vehicles (PHEV). Experimental results indicate that the thermal network method provides fast and accurate temperature estimates with the absolute error remaining below ±5 % under over 99 % operating conditions. In contrast, the empirical relationship method offers lower frequency but solid predictions under separate working conditions. Both methods were evaluated through road tests and demonstrated the capability to provide reasonable temperature variations of the power module.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"167 ","pages":"Article 115629"},"PeriodicalIF":1.6,"publicationDate":"2025-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143454892","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Influence of top-side metal layers on the performance of gold, silver, and copper wire bonds on aluminum pads","authors":"Hao-Lin Yen,&nbsp;Fang-I Lai","doi":"10.1016/j.microrel.2025.115615","DOIUrl":"10.1016/j.microrel.2025.115615","url":null,"abstract":"<div><div>This study analyzed the reliability of gold (Au), silver (Ag), and copper (Cu) wire bonds on aluminum (Al) pads coated with a multilayer Top-side metal (TSM) structure. The TSM structure was created by sequentially plating titanium (Ti), nickel–vanadium (NiV), and Ag on an Al pad, with Ag used as the surface contact layer for connection. The corrosion resistance of TSM -coated Al pads with Au, Ag, and Cu wire bonds was then examined through humidity testing, which involved pretreatment under moisture sensitivity level 3, and thermal aging at 200 °C for 5 h. The bonding interfaces of the pads were then investigated through scanning acoustic tomography, which indicated that all pads exhibited no wire bonding delamination. Testing results obtained for wire pull strength and ball shear strength indicated that the process capability index (CPK) values of the Cu wire bonds increased after thermal aging, which indicated the high thermal stability of these bonds; however, the CPK values of the Au and Ag bonds decreased marginally after thermal aging. Further analysis indicated that Au, Ag, and Cu formed solid solutions with the Ag layer of the TSM structure, and no intermetallic compound was generated; thus, the Au, Ag, and Cu wire bonds exhibited high stability and reliability even under high temperature and humidity. This study aids efforts to improve chip reliability and service life through appropriate wire material selection and TSM structure design.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"166 ","pages":"Article 115615"},"PeriodicalIF":1.6,"publicationDate":"2025-02-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143387071","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Investigation on FCBGA package with vertical-aligned carbon fiber thermal pad as thermal interface material","authors":"Mingming Yi,&nbsp;Yiou Qiu,&nbsp;Ping Wu,&nbsp;Guoliao Sun,&nbsp;Wenhui Zhu,&nbsp;Liancheng Wang","doi":"10.1016/j.microrel.2025.115607","DOIUrl":"10.1016/j.microrel.2025.115607","url":null,"abstract":"<div><div>Flip chip ball grid array (FCBGA) is the current main packaging form of CPU and GPU. With the miniaturization and intelligence of artificial intelligence chips, chip power consumption of FCBGA continues to increase (the power consumption of H100 has exceeded 800 W) and the heat dissipation problem has become increasingly serious. In the heat dissipation system of the entire chip, the thermal conductivity of thermal interface material (TIM) is a key bottleneck that limits the improvement of FCBGA package heat dissipation capability. Currently commercial TIMs such as X-23 have a thermal conductivity of 3.8–6 W/MK, which is not enough to cope with the high heat dissipation needs of existing FCBGAs. In this article, we introduced oriented carbon fibers into a silicone oil matrix to prepare a thermal pad with a thermal conductivity of 21.0 W/mK, and used it as TIM1 in FCBGA package. By optimization the key process including lid attach, dicing saw and package structure design, coverage rate reached 88.22 % after packaged. Thermal simulation shows that replace TIM in FCBGA from X-23 to homemade thermal pad, junction temperature (Tj) is reduced from 69.9 to 66.8 °C. In addition, reliability test was used carried out on FCBGA packaged incorporating carbon fiber thermal pad as TIM.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"166 ","pages":"Article 115607"},"PeriodicalIF":1.6,"publicationDate":"2025-02-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143379402","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Improved short circuit performance of silicon carbide VD-MOSFETs using a P+ implant","authors":"Prashant Singh ,&nbsp;Shreepad Karmalkar ,&nbsp;K. Akshay","doi":"10.1016/j.microrel.2025.115614","DOIUrl":"10.1016/j.microrel.2025.115614","url":null,"abstract":"<div><div>We show that the short circuit withstand time, <em>t</em>_<em>SC</em>, of a silicon carbide (SiC) Vertically Double-diffused Metal Oxide Semiconductor Field Effect Transistor (VD-MOSFET) can be raised using a P⁺ implant near the p-base corner of the device. Under short circuit conditions, this implant depletes the JFET region thereby reducing the peak short circuit current, <em>I</em>_<em>SC</em>, and consequently the lattice temperature. Hence, it takes a longer time for the peak device temperature to reach the failure threshold of ~1500 K. On the other hand, under normal on-state operation (when the drain to source voltage, <em>V</em>_<em>DS</em>, is low, ⁓20 V, <em>V</em>_<em>GS</em> = 20 V), P⁺ implant must deplete only an acceptably low fraction of the JFET width so that the on-state current remains unaffected. The window size, depth and dose of the implant can be optimized to yield the highest <em>t</em>_<em>SC</em> while simultaneously limiting the specific on-resistance, <em>R</em>_{<em>onsp</em>}. With the help of TCAD simulations calibrated with experiments, we show that the <em>t</em>_<em>SC</em> of a 0.6 kV device can be raised from 2.74 μs to 19 μs while restraining the rise in <em>R</em>_{<em>onsp</em>} within 12 % using a technologically feasible P⁺ double implant. SiC devices with the proposed implant can be switched using available gate drivers of Si IGBT and thus adopted in the industry readily.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"166 ","pages":"Article 115614"},"PeriodicalIF":1.6,"publicationDate":"2025-02-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143379403","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Increased high-temperature stiffness of an epoxy-based molding compound through high-temperature storage","authors":"Masaya Ukita,&nbsp;Keisuke Wakamoto,&nbsp;Ken Nakahara","doi":"10.1016/j.microrel.2025.115605","DOIUrl":"10.1016/j.microrel.2025.115605","url":null,"abstract":"<div><div>This paper investigates the tensile mechanical properties of epoxy-based molding compound (EMC) films containing 88 % silica filler. The EMC material was molded under 175 °C at 13.8 MPa pressure for 2 min and cured at 175 °C for 5 h to form 200 μm films. The films were cut into a dog-bone shape, whose stress–strain (<em>S</em><img><em>S</em>) curves were measured by quasi-static tensile test at a test temperature (<em>T</em>_te) of room temperature (RT), 100 °C, and 150 °C. As <em>T</em>_te increased, all the initial curves changed from brittle-like to ductile-like. Next, the films were subjected to storage at a temperature of 150 °C (<em>T</em>_st⁰) for 24, 168, and 500 h. With increasing storage time, the stiffness of the films at <em>T</em>_te = 150 °C increased, while their RT counterpart did not show significant changes. This <em>T</em>_te-dependent difference in mechanical property was likely caused by oxidation as revealed by Fourier transform infrared spectroscopy analysis, and consequently resulted in a difference in stress distribution between 150 °C and RT in an EMC-on-metal assembly, which was confirmed by finite element method stress simulation.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"166 ","pages":"Article 115605"},"PeriodicalIF":1.6,"publicationDate":"2025-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143372643","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Simulation-based FMEA for the reliability assessment of printed circuit boards","authors":"Hendrik Schmidt ,&nbsp;Markus Käß ,&nbsp;Roland Lichtinger ,&nbsp;Moritz Hülsebrock","doi":"10.1016/j.microrel.2025.115613","DOIUrl":"10.1016/j.microrel.2025.115613","url":null,"abstract":"<div><div>Simulation-based FMEA is presented as a method to estimate the reliability of printed circuit boards at the system level. A numerical simulation of relevant stress variables is combined with fatigue models and a probabilistic FMEA to determine probabilities for system level failure modes. Uncertainties of model parameters are estimated and included in the simulation to provide a comprehensive analysis of system level failure probabilities. A parametric reduced order model is used for the numerical simulation to efficiently perform the calculations with uncertain parameters. The simulation-based FMEA workflow is applied to a test printed circuit board excited by harmonic vibrations.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"166 ","pages":"Article 115613"},"PeriodicalIF":1.6,"publicationDate":"2025-02-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143208166","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}