Xiaohui Zhao , Hao Zheng , Zhiyan Zhao , Mengxuan Cheng , Wenqian Li , Guoshun Wan , Yuxi Jia
{"title":"基于深度学习和有限元模拟的扇形圆片级封装翘曲预测","authors":"Xiaohui Zhao , Hao Zheng , Zhiyan Zhao , Mengxuan Cheng , Wenqian Li , Guoshun Wan , Yuxi Jia","doi":"10.1016/j.microrel.2025.115759","DOIUrl":null,"url":null,"abstract":"<div><div>In recent years, fan-out wafer-level package (FOWLP) has gained widespread attention in integrated circuit industry due to its significant potential in enhancing packaging performance, reducing costs and minimizing size. However, accurate prediction of warpage in FOWLP remains a formidable challenge, as conventional prediction methods often suffer from prolonged iterative cycles and high computational costs. This study integrates the finite element method (FEM) with artificial intelligence (AI) techniques to develop highly accurate and efficient warpage prediction model for FOWLP based on varying chip sizes and spacings. Automated modeling and data generation were performed using simulation technique and python scripts, resulting in the creation of two datasets of different scales for regression training and optimization. Prediction results indicate that Residual Network-152 (ResNet-152) performs best on smaller datasets, while Global Context Vision Transformer-Tiny (GCViT-Tiny) exhibits greater stability on larger datasets. The Huber loss function was employed to optimize the deep learning (DL) model weights through backpropagation, significantly improving both training efficiency and prediction accuracy. Additionally, the reliability and practicality of the DL model were validated by performing simulations and AI predictions on structures not included in the dataset. Finally, the trained DL model provided brief technical guidance for optimizing warpage in wafers for the integrated circuit industry. In terms of efficiency, DL models offer a clear advantage in industrial applications. The research results provide effective theoretical support and practical guidance for FOWLP optimum design and reliability assessment, demonstrating significant application potential.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"170 ","pages":"Article 115759"},"PeriodicalIF":1.6000,"publicationDate":"2025-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Warpage prediction of fan-out wafer-level package based on coupled deep learning and finite element simulation\",\"authors\":\"Xiaohui Zhao , Hao Zheng , Zhiyan Zhao , Mengxuan Cheng , Wenqian Li , Guoshun Wan , Yuxi Jia\",\"doi\":\"10.1016/j.microrel.2025.115759\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"<div><div>In recent years, fan-out wafer-level package (FOWLP) has gained widespread attention in integrated circuit industry due to its significant potential in enhancing packaging performance, reducing costs and minimizing size. However, accurate prediction of warpage in FOWLP remains a formidable challenge, as conventional prediction methods often suffer from prolonged iterative cycles and high computational costs. This study integrates the finite element method (FEM) with artificial intelligence (AI) techniques to develop highly accurate and efficient warpage prediction model for FOWLP based on varying chip sizes and spacings. Automated modeling and data generation were performed using simulation technique and python scripts, resulting in the creation of two datasets of different scales for regression training and optimization. Prediction results indicate that Residual Network-152 (ResNet-152) performs best on smaller datasets, while Global Context Vision Transformer-Tiny (GCViT-Tiny) exhibits greater stability on larger datasets. The Huber loss function was employed to optimize the deep learning (DL) model weights through backpropagation, significantly improving both training efficiency and prediction accuracy. Additionally, the reliability and practicality of the DL model were validated by performing simulations and AI predictions on structures not included in the dataset. Finally, the trained DL model provided brief technical guidance for optimizing warpage in wafers for the integrated circuit industry. In terms of efficiency, DL models offer a clear advantage in industrial applications. The research results provide effective theoretical support and practical guidance for FOWLP optimum design and reliability assessment, demonstrating significant application potential.</div></div>\",\"PeriodicalId\":51131,\"journal\":{\"name\":\"Microelectronics Reliability\",\"volume\":\"170 \",\"pages\":\"Article 115759\"},\"PeriodicalIF\":1.6000,\"publicationDate\":\"2025-04-28\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Microelectronics Reliability\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://www.sciencedirect.com/science/article/pii/S0026271425001726\",\"RegionNum\":4,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q3\",\"JCRName\":\"ENGINEERING, ELECTRICAL & ELECTRONIC\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Microelectronics Reliability","FirstCategoryId":"5","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S0026271425001726","RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
Warpage prediction of fan-out wafer-level package based on coupled deep learning and finite element simulation
In recent years, fan-out wafer-level package (FOWLP) has gained widespread attention in integrated circuit industry due to its significant potential in enhancing packaging performance, reducing costs and minimizing size. However, accurate prediction of warpage in FOWLP remains a formidable challenge, as conventional prediction methods often suffer from prolonged iterative cycles and high computational costs. This study integrates the finite element method (FEM) with artificial intelligence (AI) techniques to develop highly accurate and efficient warpage prediction model for FOWLP based on varying chip sizes and spacings. Automated modeling and data generation were performed using simulation technique and python scripts, resulting in the creation of two datasets of different scales for regression training and optimization. Prediction results indicate that Residual Network-152 (ResNet-152) performs best on smaller datasets, while Global Context Vision Transformer-Tiny (GCViT-Tiny) exhibits greater stability on larger datasets. The Huber loss function was employed to optimize the deep learning (DL) model weights through backpropagation, significantly improving both training efficiency and prediction accuracy. Additionally, the reliability and practicality of the DL model were validated by performing simulations and AI predictions on structures not included in the dataset. Finally, the trained DL model provided brief technical guidance for optimizing warpage in wafers for the integrated circuit industry. In terms of efficiency, DL models offer a clear advantage in industrial applications. The research results provide effective theoretical support and practical guidance for FOWLP optimum design and reliability assessment, demonstrating significant application potential.
期刊介绍:
Microelectronics Reliability, is dedicated to disseminating the latest research results and related information on the reliability of microelectronic devices, circuits and systems, from materials, process and manufacturing, to design, testing and operation. The coverage of the journal includes the following topics: measurement, understanding and analysis; evaluation and prediction; modelling and simulation; methodologies and mitigation. Papers which combine reliability with other important areas of microelectronics engineering, such as design, fabrication, integration, testing, and field operation will also be welcome, and practical papers reporting case studies in the field and specific application domains are particularly encouraged.
Most accepted papers will be published as Research Papers, describing significant advances and completed work. Papers reviewing important developing topics of general interest may be accepted for publication as Review Papers. Urgent communications of a more preliminary nature and short reports on completed practical work of current interest may be considered for publication as Research Notes. All contributions are subject to peer review by leading experts in the field.