基于深度学习和有限元模拟的扇形圆片级封装翘曲预测

IF 1.6 4区 工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC
Xiaohui Zhao , Hao Zheng , Zhiyan Zhao , Mengxuan Cheng , Wenqian Li , Guoshun Wan , Yuxi Jia
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引用次数: 0

摘要

近年来,扇形圆片级封装(FOWLP)因其在提高封装性能、降低成本和减小尺寸方面的巨大潜力而受到集成电路行业的广泛关注。然而,由于传统的预测方法迭代周期长,计算成本高,对FOWLP翘曲的准确预测仍然是一个巨大的挑战。本研究将有限元法(FEM)与人工智能(AI)技术相结合,建立了基于不同芯片尺寸和间距的FOWLP高精度、高效的翘曲预测模型。使用仿真技术和python脚本进行自动化建模和数据生成,从而创建两个不同规模的数据集用于回归训练和优化。预测结果表明,残差网络-152 (ResNet-152)在较小的数据集上表现最好,而全局上下文视觉转换器- tiny (gcvi - tiny)在较大的数据集上表现出更好的稳定性。采用Huber损失函数通过反向传播优化深度学习(DL)模型权值,显著提高了训练效率和预测精度。此外,通过对数据集中未包含的结构进行模拟和人工智能预测,验证了DL模型的可靠性和实用性。最后,训练后的DL模型为集成电路行业优化晶圆翘曲提供了简要的技术指导。在效率方面,深度学习模型在工业应用中具有明显的优势。研究结果为FOWLP优化设计和可靠性评估提供了有效的理论支持和实践指导,具有重要的应用潜力。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Warpage prediction of fan-out wafer-level package based on coupled deep learning and finite element simulation
In recent years, fan-out wafer-level package (FOWLP) has gained widespread attention in integrated circuit industry due to its significant potential in enhancing packaging performance, reducing costs and minimizing size. However, accurate prediction of warpage in FOWLP remains a formidable challenge, as conventional prediction methods often suffer from prolonged iterative cycles and high computational costs. This study integrates the finite element method (FEM) with artificial intelligence (AI) techniques to develop highly accurate and efficient warpage prediction model for FOWLP based on varying chip sizes and spacings. Automated modeling and data generation were performed using simulation technique and python scripts, resulting in the creation of two datasets of different scales for regression training and optimization. Prediction results indicate that Residual Network-152 (ResNet-152) performs best on smaller datasets, while Global Context Vision Transformer-Tiny (GCViT-Tiny) exhibits greater stability on larger datasets. The Huber loss function was employed to optimize the deep learning (DL) model weights through backpropagation, significantly improving both training efficiency and prediction accuracy. Additionally, the reliability and practicality of the DL model were validated by performing simulations and AI predictions on structures not included in the dataset. Finally, the trained DL model provided brief technical guidance for optimizing warpage in wafers for the integrated circuit industry. In terms of efficiency, DL models offer a clear advantage in industrial applications. The research results provide effective theoretical support and practical guidance for FOWLP optimum design and reliability assessment, demonstrating significant application potential.
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来源期刊
Microelectronics Reliability
Microelectronics Reliability 工程技术-工程:电子与电气
CiteScore
3.30
自引率
12.50%
发文量
342
审稿时长
68 days
期刊介绍: Microelectronics Reliability, is dedicated to disseminating the latest research results and related information on the reliability of microelectronic devices, circuits and systems, from materials, process and manufacturing, to design, testing and operation. The coverage of the journal includes the following topics: measurement, understanding and analysis; evaluation and prediction; modelling and simulation; methodologies and mitigation. Papers which combine reliability with other important areas of microelectronics engineering, such as design, fabrication, integration, testing, and field operation will also be welcome, and practical papers reporting case studies in the field and specific application domains are particularly encouraged. Most accepted papers will be published as Research Papers, describing significant advances and completed work. Papers reviewing important developing topics of general interest may be accepted for publication as Review Papers. Urgent communications of a more preliminary nature and short reports on completed practical work of current interest may be considered for publication as Research Notes. All contributions are subject to peer review by leading experts in the field.
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