Microelectronics Reliability最新文献

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Solder mask as a reliable insulation layer on printed circuit boards–different layouts and materials under humidity and high voltage 阻焊板作为印刷电路板上可靠的绝缘层-在潮湿和高压下,不同的布局和材料
IF 1.6 4区 工程技术
Microelectronics Reliability Pub Date : 2025-04-22 DOI: 10.1016/j.microrel.2025.115743
M. Vogt , A. Brunko , M.R. Meier , H. Schweigart , L. Henneken , M. Schleicher , D. Schucht , N. Kaminski
{"title":"Solder mask as a reliable insulation layer on printed circuit boards–different layouts and materials under humidity and high voltage","authors":"M. Vogt ,&nbsp;A. Brunko ,&nbsp;M.R. Meier ,&nbsp;H. Schweigart ,&nbsp;L. Henneken ,&nbsp;M. Schleicher ,&nbsp;D. Schucht ,&nbsp;N. Kaminski","doi":"10.1016/j.microrel.2025.115743","DOIUrl":"10.1016/j.microrel.2025.115743","url":null,"abstract":"<div><div>After decades of improvement, the reliability of Printed Circuit Boards (PCB) is well known and standardized. However, the standards are based on outdated material properties and old experiments and thus, they contain a large safety margin, when modern insulation materials are applied. This work focuses on the insulation properties and the reliability of solder mask under high humidity and high voltages. It has been demonstrated that significantly more robust systems can be achieved than the standards specify. This leads the way for further volume reductions.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"169 ","pages":"Article 115743"},"PeriodicalIF":1.6,"publicationDate":"2025-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143856010","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Improved device structure for electrical safe operating area in SiC 1700-V VDMOSFET 改进了SiC 1700 v VDMOSFET电气安全工作区的器件结构
IF 1.6 4区 工程技术
Microelectronics Reliability Pub Date : 2025-04-18 DOI: 10.1016/j.microrel.2025.115749
Chao-Yang Ke, Ming-Dou Ker
{"title":"Improved device structure for electrical safe operating area in SiC 1700-V VDMOSFET","authors":"Chao-Yang Ke,&nbsp;Ming-Dou Ker","doi":"10.1016/j.microrel.2025.115749","DOIUrl":"10.1016/j.microrel.2025.115749","url":null,"abstract":"<div><div>This study provides significant advancements in SiC power device technology, improving the balance between high voltage, current handling, and reliability. The improved layout design of a SiC 1700-V vertical double-implanted MOSFET (VDMOSFET) with enhancing the characteristics of electrical safe operating (eSOA) and unclamped inductive switching (UIS) was carefully verified in this study. The experimental results show that the improved structure with an extended P+ region has a wider eSOA boundary. Furthermore, the improved structure can also tolerate higher power supply <em>V</em><sub><em>CC</em></sub>, higher switching current, and higher overshooting <em>V</em><sub><em>DS</em></sub> voltage. While the improved design sacrifices some DC performance, such as a slight increase in threshold voltage and on-resistance, it significantly boosts dynamic-switching reliability. All of the benefits can be attributed to the lower base resistance achieved by the layout design of an extended P+ region. Moreover, the experimental results from the double pulse test demonstrate that the proposed method did not compromise any switching speed or switching loss. Therefore, the improved structure without increasing manufacturing costs is recommended to enhance the robustness of dynamic switching in SiC 1700-V VDMOSFET.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"169 ","pages":"Article 115749"},"PeriodicalIF":1.6,"publicationDate":"2025-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143844254","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Bi, Ni and Ce coaddition improving shear property and interfacial growth of SAC305 solder joint on Cu substrate Bi、Ni和Ce的共添加改善了Cu衬底SAC305焊点的剪切性能和界面生长
IF 1.6 4区 工程技术
Microelectronics Reliability Pub Date : 2025-04-18 DOI: 10.1016/j.microrel.2025.115752
Mi Wu, Li Fu, Lei Li, Peng Gao, Yingde Miao, Qian Zhou, Qiong Lu, Caiju Li
{"title":"Bi, Ni and Ce coaddition improving shear property and interfacial growth of SAC305 solder joint on Cu substrate","authors":"Mi Wu,&nbsp;Li Fu,&nbsp;Lei Li,&nbsp;Peng Gao,&nbsp;Yingde Miao,&nbsp;Qian Zhou,&nbsp;Qiong Lu,&nbsp;Caiju Li","doi":"10.1016/j.microrel.2025.115752","DOIUrl":"10.1016/j.microrel.2025.115752","url":null,"abstract":"<div><div>In this study, the shear property and interfacial growth of Sn-3.0Ag-0.5Cu (SAC305) and Sn-3.0Ag-0.5Cu-3Bi-0.05Ni-0.05Ce (SAC305-BNC) solder joints on Cu substrates during isothermal aging were investigated. The coaddition of Bi, Ni and Ce evidently enhanced shear strength of SAC305 alloy whether after aging or not, and changed the shear fracture from a transgranular failure to an intergranular failure. Cu<sub>6</sub>Sn<sub>5</sub> intermetallic compound (IMC) layer formed in the SAC305/Cu solder joints, (Cu,Ni)<sub>6</sub>Sn<sub>5</sub> and Cu<sub>3</sub>Sn IMC layers formed in the SAC305/Cu solder joints. The growth rates of IMC layers were slowed, and the Cu<sub>6</sub>Sn<sub>5</sub> grain size were refined by Bi, Ni and Ce coaddition during isothermal aging, thereby partly contributing to the increase of shear strength, and simultaneously improving the reliability of solder joints.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"169 ","pages":"Article 115752"},"PeriodicalIF":1.6,"publicationDate":"2025-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143844253","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Nonlinear modeling of AlN/GaN HEMT accounting for self-biasing effect during RF step stress: Analysis and hard-SOA 考虑RF阶跃应力自偏置效应的AlN/GaN HEMT非线性建模:分析与硬soa
IF 1.6 4区 工程技术
Microelectronics Reliability Pub Date : 2025-04-18 DOI: 10.1016/j.microrel.2025.115742
N. Said , D. Saugnon , K. Harrouche , F. Medjdoub , N. Labat , N. Malbert , J.G. Tartarin
{"title":"Nonlinear modeling of AlN/GaN HEMT accounting for self-biasing effect during RF step stress: Analysis and hard-SOA","authors":"N. Said ,&nbsp;D. Saugnon ,&nbsp;K. Harrouche ,&nbsp;F. Medjdoub ,&nbsp;N. Labat ,&nbsp;N. Malbert ,&nbsp;J.G. Tartarin","doi":"10.1016/j.microrel.2025.115742","DOIUrl":"10.1016/j.microrel.2025.115742","url":null,"abstract":"<div><div>In this study, we investigate the non-linear (NL) behavior of AlN/GaN HEMT technologies under gain compression when submitted to 10 GHz single-tone RF-step stress, which is crucial for millimetre-wave power application robustness. We evaluate AlN/GaN transistors, targeting high-power amplifiers with operating frequency above 30 GHz. We present here an original method that includes, in a unique NL expression, the varying self-biasing effect caused by RF step-stress sequences. This methodology can be used as a tool for comparative analysis of technological variants and various transistor geometries post RF stress. The step-stresses are conducted on HEMT in saturated mode and in diode operation alone, to assess the electrical origins of defects and the critical Safe Operating Area (SOA) of these devices. We identify the mechanism of failure as stemming from the degradation of the Schottky gate when subjected to critical RF power levels, due to its constrained capacity to handle power signals exceeding 18 dBm. Furthermore, we highlight the remarkable RF robustness of this technology, achieving gain compression of around 10 dB without degradation.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"169 ","pages":"Article 115742"},"PeriodicalIF":1.6,"publicationDate":"2025-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143844255","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Single-event burnout mechanism and hardening for 1200 V 4H-SiC LDMOS 1200v 4H-SiC LDMOS单事件燃尽机制及硬化
IF 1.6 4区 工程技术
Microelectronics Reliability Pub Date : 2025-04-16 DOI: 10.1016/j.microrel.2025.115712
Liqun Wang, Panpan Tang, Jingchang Nan
{"title":"Single-event burnout mechanism and hardening for 1200 V 4H-SiC LDMOS","authors":"Liqun Wang,&nbsp;Panpan Tang,&nbsp;Jingchang Nan","doi":"10.1016/j.microrel.2025.115712","DOIUrl":"10.1016/j.microrel.2025.115712","url":null,"abstract":"<div><div>In this paper, the Single-Event Burnout (SEB) triggering mechanism of 1200<!--> <!-->V 4H-SiC Lateral Diffused Metal Oxide Semiconductor (LDMOS) is numerically studied based on Sentaurus TCAD electro-thermal coupled simulations. A hardened design of source-extended combined with a triple-buffer layer is proposed. Simulation results show that impact ionization plays an important role in the SEB triggering of SiC LDMOS. With the introduction of a triple-buffer layer that can effectively suppresses and integrates the peak electric field, thereby weakening impact ionization. Meanwhile, the source-extended can extract the holes rapidly and suppress the parasitic BJT positive feedback, thus avoiding the thermal damage caused by excessive current. Under the optimal parameters, the SEB threshold voltage (<span><math><msub><mrow><mi>V</mi></mrow><mrow><mi>S</mi><mi>E</mi><mi>B</mi></mrow></msub></math></span>) of the proposed structure is 259% higher than the conventional structure.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"169 ","pages":"Article 115712"},"PeriodicalIF":1.6,"publicationDate":"2025-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143838362","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Corrigendum to “Electrothermal power cycling of GaN and SiC cascode devices” [Microelectron. Reliab. 150 (November 2023) 115117] “GaN和SiC级联码器件的电热功率循环”的勘误表[微电子]。科学通报,2015(11月23日)
IF 1.6 4区 工程技术
Microelectronics Reliability Pub Date : 2025-04-16 DOI: 10.1016/j.microrel.2025.115748
Y. Gunaydin , S. Jahdi , R. Yu , Xibo Yuan , Olayiwola Alatise , Jose Ortiz Gonzalez
{"title":"Corrigendum to “Electrothermal power cycling of GaN and SiC cascode devices” [Microelectron. Reliab. 150 (November 2023) 115117]","authors":"Y. Gunaydin ,&nbsp;S. Jahdi ,&nbsp;R. Yu ,&nbsp;Xibo Yuan ,&nbsp;Olayiwola Alatise ,&nbsp;Jose Ortiz Gonzalez","doi":"10.1016/j.microrel.2025.115748","DOIUrl":"10.1016/j.microrel.2025.115748","url":null,"abstract":"","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"169 ","pages":"Article 115748"},"PeriodicalIF":1.6,"publicationDate":"2025-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143887764","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Efficient long-term reliability assessment of planar InGaAs/InP avalanche photodiodes using accelerated step-stress test 利用加速阶跃应力试验评估平面InGaAs/InP雪崩光电二极管的长期可靠性
IF 1.6 4区 工程技术
Microelectronics Reliability Pub Date : 2025-04-15 DOI: 10.1016/j.microrel.2025.115739
Yunseok Han , Sunho Kim , Ilgu Yun
{"title":"Efficient long-term reliability assessment of planar InGaAs/InP avalanche photodiodes using accelerated step-stress test","authors":"Yunseok Han ,&nbsp;Sunho Kim ,&nbsp;Ilgu Yun","doi":"10.1016/j.microrel.2025.115739","DOIUrl":"10.1016/j.microrel.2025.115739","url":null,"abstract":"<div><div>This paper presents a novel methodology for the rapid long-term reliability assessment of planar InGaAs/InP avalanche photodiodes. To quickly obtain degradation data of highly reliable avalanche photodiode devices, hybrid stress combining thermal and electrical stresses was applied through the accelerated step-stress test methodology. The details of the structure of tested avalanche photodiodes, experimental setup, and accelerated step-stress test conditions were explained. Based on the results, a significant increase in dark current with applied stress was observed while the breakdown voltage remained almost stable. The expected median time to failure for each stress condition using accelerated step-stress test data was then extracted. Finally, using the modified Eyring model, the activation energy and predicted lifetime under the practical use condition were extrapolated.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"169 ","pages":"Article 115739"},"PeriodicalIF":1.6,"publicationDate":"2025-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143829682","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
OFF-state breakdown and threshold voltage stability of vertical GaN-on-Si trench MOSFETs 垂直GaN-on-Si沟槽mosfet的关断击穿和阈值电压稳定性
IF 1.6 4区 工程技术
Microelectronics Reliability Pub Date : 2025-04-14 DOI: 10.1016/j.microrel.2025.115716
M. Fregolent , F. Bergamin , D. Favero , C. De Santi , Andrea Cester , C. Huber , G. Meneghesso , E. Zanoni , M. Meneghini
{"title":"OFF-state breakdown and threshold voltage stability of vertical GaN-on-Si trench MOSFETs","authors":"M. Fregolent ,&nbsp;F. Bergamin ,&nbsp;D. Favero ,&nbsp;C. De Santi ,&nbsp;Andrea Cester ,&nbsp;C. Huber ,&nbsp;G. Meneghesso ,&nbsp;E. Zanoni ,&nbsp;M. Meneghini","doi":"10.1016/j.microrel.2025.115716","DOIUrl":"10.1016/j.microrel.2025.115716","url":null,"abstract":"<div><div>In this paper we analyze the OFF-state performance of vertical GaN-on-Si Trench MOSFETs in terms of breakdown voltage and stability of the threshold voltage. We proved that the devices fail in OFF-state due to the breakdown of the unprotected gate oxide. Then, by means of a series of fast V<sub>TH</sub> transient experiments, we demonstrate that the OFF-state threshold voltage instability is given by the trapping of electrons at deep levels in the p-GaN body layer, transported by the rather high drain current leakage. The interpretation was supported by deep level spectroscopy measurements, carried out on p-n junctions located on the same wafer.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"169 ","pages":"Article 115716"},"PeriodicalIF":1.6,"publicationDate":"2025-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143825917","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
On the electrical properties of ALD HfO2 dielectric films for MEMS capacitive switches MEMS电容开关用ALD HfO2介电膜电学性能研究
IF 1.6 4区 工程技术
Microelectronics Reliability Pub Date : 2025-04-14 DOI: 10.1016/j.microrel.2025.115737
J. Theocharis , J.P. Martins , A. Mahjoub , E. Eustache , A. Ziaei , G. Papaioannou
{"title":"On the electrical properties of ALD HfO2 dielectric films for MEMS capacitive switches","authors":"J. Theocharis ,&nbsp;J.P. Martins ,&nbsp;A. Mahjoub ,&nbsp;E. Eustache ,&nbsp;A. Ziaei ,&nbsp;G. Papaioannou","doi":"10.1016/j.microrel.2025.115737","DOIUrl":"10.1016/j.microrel.2025.115737","url":null,"abstract":"<div><div>This work investigates the electrical properties of thin HfO<sub>2</sub> dielectric films grown by Atomic Layer Deposition (ALD) for application in RF-MEMS capacitive switches. The motivation arises from the need to optimize dielectric performance in these devices, particularly concerning dielectric charging, breakdown behavior, and conduction mechanisms. A key challenge addressed is the influence of deposition temperature on the structural and electrical behavior of the films, which transitions from amorphous to polycrystalline with temperature. The study utilizes a wide range of techniques including current-voltage measurements, impedance spectroscopy, Kelvin Probe potential decay, and Thermally Stimulated Depolarization Currents (TSDC) on Metal–Insulator-Metal (MIM) devices. The key findings indicate that grain boundary formation in polycrystalline films significantly alters the breakdown voltage, charge transport, and trapping mechanisms. It is worth noting that, films deposited at 100–150 °C exhibit hopping conduction and lower leakage, while those at 200–250 °C demonstrate ohmic or Space Charge Limited Current (SCLC) behavior due to crystallization. These results provide insight for selecting suitable deposition parameters to engineer dielectric materials for reliable MEMS switch operation.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"169 ","pages":"Article 115737"},"PeriodicalIF":1.6,"publicationDate":"2025-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143825915","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Impact of aging on temperature measurements performed using a resistive temperature sensor with sensor-to-microcontroller direct interface 老化对使用具有传感器-微控制器直接接口的电阻式温度传感器进行温度测量的影响
IF 1.6 4区 工程技术
Microelectronics Reliability Pub Date : 2025-04-14 DOI: 10.1016/j.microrel.2025.115729
Marco Grossi, Martin Omaña, Cecilia Metra
{"title":"Impact of aging on temperature measurements performed using a resistive temperature sensor with sensor-to-microcontroller direct interface","authors":"Marco Grossi,&nbsp;Martin Omaña,&nbsp;Cecilia Metra","doi":"10.1016/j.microrel.2025.115729","DOIUrl":"10.1016/j.microrel.2025.115729","url":null,"abstract":"<div><div>Temperature measurements play a critical role in guaranteeing system's reliability, for a widespread variety of applications, such as automotive, avionics, etc. Temperature measurements can be conveniently performed at low cost using resistive temperature sensors connected to a microcontroller using sensor-to-microcontroller direct interface (SMDI). However, temperature measurements performed using SMDI may be affected by aging phenomena, such as Bias Temperature Instability (BTI), which may compromise its operation in the field.</div><div>Based on these considerations, in this paper we address the case of temperature measurements performed by a resistive temperature sensor connected to a microcontroller by SMDI. We analyze the impact of BTI on the accuracy of the temperature measurements performed using SMDI. We will show that BTI can seriously degrade the accuracy of such measurements, with possible consequences for system's reliability. We then describe a possible strategy to compensate such a degraded accuracy in temperature measurements, thus avoiding its impact on system's reliability.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"169 ","pages":"Article 115729"},"PeriodicalIF":1.6,"publicationDate":"2025-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143825916","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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