Microelectronics Reliability最新文献

{"title":"Analyzing false turn-on events with varying gate drive parameters in high voltage GaN devices","authors":"Nishant Kashyap ,&nbsp;Arghyadeep Sarkar","doi":"10.1016/j.microrel.2024.115442","DOIUrl":"https://doi.org/10.1016/j.microrel.2024.115442","url":null,"abstract":"<div><p>In this paper, we address the problem of false turn-on effects in a half-bridge GaN power converter in terms of circuit and device parameters. The model shows that the inherent false turn-on problem is caused by slew rates <span><math><mfrac><mrow><mi>d</mi><msub><mi>v</mi><mi>ds</mi></msub></mrow><mi>dt</mi></mfrac></math></span> and <span><math><mfrac><mrow><mi>d</mi><msub><mi>v</mi><mi>gs</mi></msub></mrow><mi>dt</mi></mfrac><mspace></mspace></math></span>during the switching transients occurring at the turn-on and off phases. A higher slew rate propagates the gate driver voltage to overshoot beyond the threshold voltage causing it to accidentally turn on This study shows that <span><math><mfrac><mrow><mi>d</mi><msub><mi>v</mi><mi>ds</mi></msub></mrow><mi>dt</mi></mfrac></math></span> is dependent on the internal device parameters such as <span><math><msub><mi>g</mi><mi>fs</mi></msub></math></span> (transconductance) and <span><math><msub><mi>C</mi><mi>oss</mi></msub></math></span><em>(</em>output capacitance). From the CV characteristics, it is pretty much evident that the internal capacitances <span><math><msub><mi>C</mi><mi>oss</mi></msub></math></span>and <span><math><msub><mi>C</mi><mi>rss</mi></msub></math></span> (reverse transfer capacitance) are reduced with higher drain voltage enabling higher slew rates which increases the probability of false turn-on problems. Experimental results at numerous operating points at 400 V with the variation in different gate drive parameters support the analysis.</p></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"160 ","pages":"Article 115442"},"PeriodicalIF":1.6,"publicationDate":"2024-07-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141605461","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Solvent-free Cu sintering pastes using acidic activators","authors":"Seong-ju Han ,&nbsp;Gun-woo Park ,&nbsp;Keon-Soo Jang","doi":"10.1016/j.microrel.2024.115454","DOIUrl":"https://doi.org/10.1016/j.microrel.2024.115454","url":null,"abstract":"<div><p>This study delves into the critical evaluation of solvent-free liquid-type acidic additives for their effectiveness in the copper (Cu) sintering process, a crucial method for achieving robust electrical and thermal connections in semiconductor packaging. Sintering is a process of compacting and forming a solid mass of material by heat and/or pressure without melting to the point of liquefaction. It plays an essential role in the manufacturing of electronic components. It creates highly conductive pathways necessary for the reliable performance of semiconductor devices. However, the presence of an oxide layer on Cu surfaces poses a remarkable challenge by impeding thermal and electrical conductivity, thus necessitating the removal of this layer to enhance the performance of sintered components. The study primarily focused on the application of various liquid-type acidic additives, namely, formic acid (FA), acetic acid (AA), hexanoic acid (HA), lactic acid (LA), hydrochloric acid (HcA), and sulfuric acid (SA) to achieve solvent-free sintering and to ascertain their efficiency in oxide layer removal and their impact on the thermal and electrical properties of the sintered Cu chips. Through a series of analytical methods, including thermogravimetric analysis (TGA), X-ray photoelectron spectroscopy (XPS), X-ray diffraction (XRD), scanning electron microscopy (SEM), and lab shear strength tests, the study revealed significant insights into the thermal stability, oxide layer removal efficiency, and connectivity between Cu particles. Our findings demonstrated that FA and LA additives markedly enhanced the sintering quality by effectively removing the Cu oxide layer, thereby facilitating superior particle connectivity and improving the thermal and electrical conductivities of sintered Cu chips. By contrast, HA, HcA, and SA were less effective, largely because of their inability to remove the oxide layer adequately and their tendency to leave organic residues, resulting in lower mechanical integrity of the sintered Cu chips. The superior performance of FA and LA was attributed to their optimal thermal properties and the high concentration of carboxylic groups capable of efficiently reducing the oxide layer on Cu surfaces. This study contributed to the optimization of the Cu sintering process by identifying effective acidic additives that enhanced the mechanical, thermal, and electrical properties of sintered Cu chips. These findings hold significant promise for advancing semiconductor packaging technologies by providing insights into selecting suitable sintering additives for developing high-performance electronic components.</p></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"159 ","pages":"Article 115454"},"PeriodicalIF":1.6,"publicationDate":"2024-07-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141596320","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Double-exponential-probability-distribution-function and it's applications in some critical aerospace safety problems: Perspective and brief review","authors":"E. Suhir","doi":"10.1016/j.microrel.2024.115439","DOIUrl":"https://doi.org/10.1016/j.microrel.2024.115439","url":null,"abstract":"<div><p>Some critical microelectronics and photonics aerospace-safety and reliability-physics problems could be successfully addressed using a flexible and physically meaningful double-exponential-probability-distribution-function (DEPDF). It is the author's belief that a successful outcome of an undertaking of importance cannot be achieved and assured, nor even considerably improved, if the effort is not quantified, and if, because of numerous uncertain-and-inevitable intervening influences, such a quantification is not done on a probabilistic basis. This is particularly true in various “human-in-the-loop” missions and extraordinary situations, when the reliability of the equipment/instrumentation, both its hard- and software, and the performance of the involved human(s) contribute jointly to the outcome of a mission or an off-normal situation. The acceptable never-zero probability of failure cannot be high, of course, but should not be lower than necessary either. It has to be adequate for a particular system, mission and application. Products that “never fail” are most likely more expensive than they could and should be. The general concepts are illustrated by practical examples. It is concluded that while some kind of predictive modeling should always precede any type of accelerated testing, analytical (“mathematical”) modeling, employed in this write-up, should complement, whenever possible, computer simulations: these two major modeling tools are based on different assumptions, use different calculation techniques, and if the results are in agreement, then there is a good reason to believe that the obtained information is sufficiently accurate and, hence, trustworthy. Future work should be focused on the experimental verification of the suggested DEPDF model and on new areas of its possible applications in aerospace safety tasks and problems and beyond.</p></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"159 ","pages":"Article 115439"},"PeriodicalIF":1.6,"publicationDate":"2024-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141583202","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Research on thermal management of 3D-ICs assisted by deep learning","authors":"Sixiang Zhang ,&nbsp;Qiuping Yang ,&nbsp;Zhiyuan Zhu","doi":"10.1016/j.microrel.2024.115455","DOIUrl":"https://doi.org/10.1016/j.microrel.2024.115455","url":null,"abstract":"<div><p>Compared with integrated circuits based on through silicon via (TSV), monolithic inter-tier via (MIV) has been identified as a critical technique to enable three dimensional (3D) integration due to its ultra-small size and relatively superior electrical performance, which allows ultra-high integration density. However, the interconnection of monolithic 3D (M3D) design is more prone to electromigration and stress migration. Severe crosstalk during signal transmission and thermal stress at high temperatures have serious limitations on system performance. In this paper, we focus on the COMSOL Multi-physics software, which can solve multi-field problems, to study the crosstalk problem and its thermal stress problem in MIV structures and analyze the crosstalk effects and temperature stress changes of MIV under different physical coupling conditions. An MIV array based on electrical-thermal-mechanical multi-field coupling was proposed, and the temperature and stress were analyzed by finite element analysis software. Additionally, an artificial neural network scheme is proposed that uses MATLAB to train temperature and stress data to predict the stress values of MIV. Experimental results show that the proposed prediction model using a genetic algorithm to optimize the BP Neural Network (GABP) has a 23.3 % higher prediction accuracy than that of a general BP neural network.</p></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"159 ","pages":"Article 115455"},"PeriodicalIF":1.6,"publicationDate":"2024-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141543394","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Double π-gate AlGaN/GaN HEMT with reduced surface and buffer traps and enhanced reliability","authors":"Rayabarapu Venkateswarlu,&nbsp;Bibhudendra Acharya,&nbsp;Guru Prasad Mishra","doi":"10.1016/j.microrel.2024.115449","DOIUrl":"https://doi.org/10.1016/j.microrel.2024.115449","url":null,"abstract":"<div><p>A double π-gate engineering technique is proposed to analyse the device performance and enhance the reliability by reducing the surface traps and buffer traps using Silvaco TCAD simulator tool. Peak electric field due to V_gs, under the gate can worse the device performance and cause memory effects. The peak electric field destructs the charge carrier density (2-DEG) in the channel, lowers the charge carrier density in the channel and results in current collapse. The peak electric field make the electrons/holes (in n-type/p-type) to get energized (hot electron) and injected into buffer region and other epi-layers by the process trapping/de-trapping. Drain current collapse (∆ I_dmax) and threshold voltage shift (∆V_th) occur due to trapping/de-trapping. Proposed method has T-gate which is spilt into 3-pillars referred to as double-π shaped gate structure. Results obtained from the suggested technique showed that perfect peak current in the channel and uniform electric field distribution is achieved. The dc characteristics pulsed I-V, pulsed C-V, and pulsed S-parameters are analysed to study the trapping effects.</p></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"159 ","pages":"Article 115449"},"PeriodicalIF":1.6,"publicationDate":"2024-07-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141482198","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Compatibility study of no-clean flux residue and conformal coatings using two electrode electrochemical impedance method","authors":"Feng Li,&nbsp;Vadimas Verdingovas,&nbsp;Ioannis Mantis,&nbsp;Morten Stendahl Jellesen,&nbsp;Rajan Ambat","doi":"10.1016/j.microrel.2024.115452","DOIUrl":"https://doi.org/10.1016/j.microrel.2024.115452","url":null,"abstract":"<div><p>Conformal coatings are widely used on electronic assemblies to protect electronic devices from ionic contaminants, humidity, and dust. This study focused on the influence of the process related no-clean flux residue on the protection performance of three conventionally used conformal coatings under cyclic humidity conditions. A test Printed Circuit Board (PCB) with comb-structure surface insulation resistance (SIR) pattern was used as test vehicle. Two-electrode electrochemical impedance spectroscopy (EIS) was used to monitor the water uptake behavior of the coatings under cyclic thermal-humidity exposure in the air, followed by chrono-amperometry to evaluate the effect of penetrated moisture reaching the PCB surface. Failure modes of the SIR include increased leakage current and degradation product such as electrochemical migration (ECM) between the comb-structure electrodes. The surface morphology and adhesion was inspected using scanning electron microscopy and corrosion product analysis was carried out using energy dispersive spectroscopy. Results suggest that the moisture barrier properties of the coating and adhesion of the coating are important parameters affecting the corrosion protection performance and the presence of no-clean flux residue has most significant influence on the adhesion of the coatings. Among the coatings investigated, elastomeric acrylate showed best performance due to unsurpassed adhesion even under aggressive solder flux contaminated conditions. Two electrode EIS method could differentiate the compatibility of flux residue and conformal coating within few hours.</p></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"159 ","pages":"Article 115452"},"PeriodicalIF":1.6,"publicationDate":"2024-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://www.sciencedirect.com/science/article/pii/S002627142400132X/pdfft?md5=9dd6e759e59b884726e475a71e305977&pid=1-s2.0-S002627142400132X-main.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141482197","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Understanding board level vibrations in automotive electronic modules","authors":"V. Thukral ,&nbsp;R. Roucou ,&nbsp;C. Chou ,&nbsp;J.J.M. Zaal ,&nbsp;M. van Soestbergen ,&nbsp;R.T.H. Rongen ,&nbsp;W.D. van Driel ,&nbsp;G.Q. Zhang","doi":"10.1016/j.microrel.2024.115430","DOIUrl":"https://doi.org/10.1016/j.microrel.2024.115430","url":null,"abstract":"<div><p>Board level reliability can be of high interest for automotive electronic components when exposed to vibration-prone environments. However, the absence of an industry standard for board level vibration testing poses several challenges in establishing a well-characterized test setup. One of the challenges is that automotive applications can induce abnormal stresses on components that can lead to early failures in the field. Such loading conditions are not always covered in the current board level vibration test methods. This paper aims to correlate the stresses from automotive modules to board levels by measuring the printed circuit board (PCB) vibration spectrum. Firstly, the study compares and assesses several module board level vibration measurement units, such as LASER Doppler Vibrometer (LDV), strain gauges, and accelerometers. Experiments and simulations show that LDV enables good correlation with Micro-electro Mechanical Systems (MEMS) accelerometers. Secondly, the module-board interaction unveils insights into several module design features that impact the PCB vibration response and solder joint interconnect reliability. These findings underscore the necessity for the user to correctly validate the reliability of packages beyond board level testing, i.e., at the module level. This reliability test approach enables the translation of reliability test results from the lab to the field life of components once built in the final application equipment.</p></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"159 ","pages":"Article 115430"},"PeriodicalIF":1.6,"publicationDate":"2024-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141482190","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Ionizing radiation defects and reliability of Gallium Nitride-based III-V semiconductor devices: A comprehensive review","authors":"V. Sandeep ,&nbsp;J. Charles Pravin ,&nbsp;S. Ashok Kumar","doi":"10.1016/j.microrel.2024.115445","DOIUrl":"https://doi.org/10.1016/j.microrel.2024.115445","url":null,"abstract":"<div><p>The remote sensing and satellite community working for space organizations have expressed interest in building advanced devices with potential choices for Gallium Nitride based transistors. Radar and satellite communication applications employ nitride High Electron Mobility Transistors (HEMTs) due to their high radiation-absorbing and temperature tolerant qualities. However, they also deteriorate simultaneously upon such radiations that cause a drastic fall in their lifetimes. This article carries out reliability studies of GaN-based III-V semiconductor devices, including HEMTs, Schottky and thin film diodes by reviewing the defects induced by radiation. A review of the various kinds of defects induced in these devices upon subject to several radiation beams like proton, neutron, gamma, alpha, and other sources has been discussed here. GaN, when subject to high energy ionizing radiation particles, produce point defects in the material that are more dominated by extended disordered regions. Trap states also occur as a part of radiation damage with forbidden gaps consisting of deep thermal ionization energies, which causes the device’s mobility and electrical conductivity to decrease drastically. A short description on how these defects can be mitigated to a certain extent has been given, eying towards more withstanding capabilities for these devices in radiation-hardened environments.</p></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"159 ","pages":"Article 115445"},"PeriodicalIF":1.6,"publicationDate":"2024-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141482191","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Optimization of novel two-step curing method for die stack epoxy bonding to reduce voids in Ball Grid Array packages for high-density interconnect applications","authors":"Qian Qing Ng ,&nbsp;Chou Yong Tan ,&nbsp;Yew Hoong Wong ,&nbsp;Boon Kar Yap ,&nbsp;Farazila B. Yusof ,&nbsp;Saim Saher","doi":"10.1016/j.microrel.2024.115450","DOIUrl":"https://doi.org/10.1016/j.microrel.2024.115450","url":null,"abstract":"<div><p>This research explores the optimization of epoxy curing parameters to minimize void formation in 3-IC-Chip-MAPBGA packages, a subset of BGA packages, crucial components in high-density interconnect applications. The study utilizes a systematic approach involving design of experiments (DOE) assisted by statistical JMP tool to manipulate curing profiles, aiming to achieve void reduction while preserving adhesion properties. Various analytical techniques, including X-ray imaging, differential scanning calorimetry (DSC), thermogravimetric analysis (TGA), die shear strength tests, and C-Sam analysis for delamination, are employed to analyze void formation, material characteristics, mechanical properties, and structural integrity. The findings demonstrate that the sample with a 2nd step curing profile, identified as sample#3, which includes a ramp time of 15 min, a 1st step curing temperature of 90 °C with a soak time of 20 min, and a 2nd step ramp time of 20 min, exhibits the most favourable outcome in void reduction. This sample shows a notably lower void presence of 3.66 % and the highest die shear strength of 126 MPa. In contrast, the control sample, serving as a reference, displays a void percentage of 7.28 %, nearly twice as high as that of sample#3, and much lower die shear strength of 80 MPa at 25 °C. Adopting the curing profile of sample#3 also leads to a substantial 18.75 % reduction in cycle time compared to the control sample. The study highlights the importance of balancing curing parameters to mitigate void formation and maintain optimal mechanical properties, offering valuable insights for improving the reliability of high-density interconnect applications.</p></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"159 ","pages":"Article 115450"},"PeriodicalIF":1.6,"publicationDate":"2024-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141482193","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Lifetime reliability modeling on EMC performance of digital ICs influenced by the environmental and aging constraints: A case study","authors":"Jaber Al Rashid ,&nbsp;Mohsen Koohestani ,&nbsp;Laurent Saintis ,&nbsp;Mihaela Barreau","doi":"10.1016/j.microrel.2024.115447","DOIUrl":"https://doi.org/10.1016/j.microrel.2024.115447","url":null,"abstract":"<div><p>This paper aims to develop the lifetime reliability model on electromagnetic compatibility (EMC) performance of the Atmel Attiny85 microcontroller integrated circuit (IC) chip samples, depending on the observed variation of the conducted immunity to the electromagnetic interference imposed by the combined influence of various environmental and aging (i.e., thermal and electrical voltage stress) constraints. A constant-stress accelerated degradation tests plan was designed and implemented by applying different constant thermal (i.e., 70 and 110 °C) and electrical voltage (i.e., 4 and 5 V) stress magnitude levels simultaneously in various multiple stress combinations. Direct power injection (DPI) conducted immunity tests were performed in nominal condition on all the programmed device under test (DUT) samples in both the fresh and aged states at various stress time duration. The best-fit EMC degradation paths were generated using regression analysis, followed by evaluating the pseudo time-to-failure (<span><math><mrow><mi>T</mi><mi>T</mi><mi>F</mi></mrow></math></span>) data and estimating the unknown parameters of the developed degradation path model. The performance metrics for lifetime reliability were evaluated by combining the Weibull distribution function with the generalized Eyring accelerated life test model. The maximum likelihood estimation method was utilized to estimate the relevant reliability model parameters. The developed reliability model was found to have the capability to estimate the electromagnetic unreliability against the lifetime <span><math><mrow><mi>T</mi><mi>T</mi><mi>F</mi></mrow></math></span> data of all the selected DUT samples with good precision and acceptable accuracy in both nominal and aging stress conditions. It is demonstrated that the non-failure probability of the DUT samples would remain at 1 for the first 1200 h, and that, under nominal conditions, the prediction of corresponding <span><math><mrow><mi>T</mi><mi>T</mi><mi>F</mi></mrow></math></span> data for all of those IC samples would fluctuate between 1400 and 1600 h.</p></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"159 ","pages":"Article 115447"},"PeriodicalIF":1.6,"publicationDate":"2024-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://www.sciencedirect.com/science/article/pii/S0026271424001276/pdfft?md5=41f33acdbe7dd17c37a70ad807fe5ccd&pid=1-s2.0-S0026271424001276-main.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141482192","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}