Microelectronics Reliability最新文献

{"title":"Long-term positive and negative gate bias stress tests on parallel connected SiC MOSFETs at −40 °C and 175 °C","authors":"A. Deb ,&nbsp;M. Taha ,&nbsp;J. Ortiz Gonzalez ,&nbsp;P. Mawby ,&nbsp;S. Jahdi ,&nbsp;B. Etoz ,&nbsp;O. Alatise","doi":"10.1016/j.microrel.2025.115834","DOIUrl":"10.1016/j.microrel.2025.115834","url":null,"abstract":"<div><div>Bias temperature instability (BTI) is known to adversely impact the performance of parallel connected SiC MOSFETs. The short circuit robustness of SiC modules is known to reduce with increased threshold voltage (<em>V</em>_<em>TH</em>) variation within the parallel devices due to poor current sharing. In this paper, 400-h positive BTI (<em>V</em>_<em>GS</em> = 25 V) and negative BTI (<em>V</em>_<em>GS</em> = −10 V) stress tests at both −40 °C and 175 °C have been performed on 5 parallel connected SiC MOSFETs. Both the individual <em>V</em>_<em>TH</em> shift for each of the 5 devices and the module <em>V</em>_<em>TH</em> shift have been measured alongside the <em>V</em>_<em>TH</em> range (highest <em>V</em>_<em>TH</em> minus lowest <em>V</em>_<em>TH</em>). Bipolar preconditioning has been performed before <em>V</em>_<em>TH</em> measurement to record both the peak <em>V</em>_<em>TH</em> (measured before bipolar preconditioning) and permanent <em>V</em>_<em>TH</em> (measured after bipolar preconditioning). The results show that p-BTI stress yields 21 % higher peak module <em>V</em>_<em>TH</em> shift compared to n-BTI at −40 °C and 29 % higher at 175 °C. The measured <em>V</em>_<em>TH</em> range was unchanged by the BTI tests if permanent <em>V</em>_<em>TH</em> shift is assessed. However, the peak <em>V</em>_<em>TH</em> range was higher after stressing thereby indicating increased variability in the injected temporary charge. The peak <em>V</em>_<em>TH</em> range also exhibits a positive temperature coefficient indicating that temperature increases variability of the injected charge. If <em>V</em>_<em>TH</em> range is taken as an indicator of short circuit robustness in parallel connected devices, the measurements presented show that bipolar preconditioning ensures that the short circuit performance of the module would likely be unaffected by the stress tests since <em>ΔV</em>_<em>TH</em> shift is uniform.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"172 ","pages":"Article 115834"},"PeriodicalIF":1.6,"publicationDate":"2025-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144338743","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Research on high-power high-frequency electrical transmission characteristics of through glass via interconnections","authors":"Luming Chen ,&nbsp;Shitao Wang ,&nbsp;Zhilin Wei ,&nbsp;Zhizhen Wang ,&nbsp;Yihan Xie ,&nbsp;Chunlei Li ,&nbsp;Shenglin Ma ,&nbsp;Shuwei He ,&nbsp;Hai Yuan","doi":"10.1016/j.microrel.2025.115828","DOIUrl":"10.1016/j.microrel.2025.115828","url":null,"abstract":"<div><div>Through Glass Via (TGV) have attracted significant attention as advanced package solutions. Compared to silicon, glass has lower dielectric losses but thermal conductivity two orders of magnitude lower. This may introduce transmission degradation due to self electro-thermal coupling in high-power, high-frequency signal applications such as RadioFrequency (RF) transceiver and high-performance computing chip package. To address the issue, A Microstrip Resonant Ring (MRR) test structure was designed and fabricated for temperature-dependent high-frequency parameter extraction. Coplanar Waveguide (CPW) and Substrate integrated waveguide (SIW) test structures were designed and fabricated for high-frequency transmission tests at various temperatures. A quadruple redundant TGV connected CPW test structure was designed and fabricated for high-frequency high-power self electro-thermal testing, followed with self electro-thermal coupling simulation to verify experimental results. The research reveals that, under high-power, high-frequency signal input, transmission losses in TGV interconnects are primarily dominated by conductor losses. The optimized quadruple redundant TGV connected CPW test structure demonstrated insertion losses of 0.51 dB, 0.94 dB, and 2.04 dB under input conditions of 10 W@6GHz, 7.9 W@12GHz, and 6.3 W@18GHz, respectively. The corresponding maximum temperatures recorded were 36.2 °C, 38.4 °C, and 55 °C for these operating conditions.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"172 ","pages":"Article 115828"},"PeriodicalIF":1.6,"publicationDate":"2025-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144321986","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"High-performance, low-area-overhead, and low-delay triple-node-upset self-recoverable latch design based on stacked transistors","authors":"Hui Xu ,&nbsp;Yue Dai ,&nbsp;Ruijun Ma ,&nbsp;Huaguo Liang ,&nbsp;Zhengfeng Huang ,&nbsp;Tianming Ni ,&nbsp;Chuanjian Zhang ,&nbsp;Xin Chen ,&nbsp;Ye Tang","doi":"10.1016/j.microrel.2025.115830","DOIUrl":"10.1016/j.microrel.2025.115830","url":null,"abstract":"<div><div>Due to the gradual reduction in the feature size of transistors in integrated circuits (ICs), triple-node-upsets (TNUs) caused by the striking of energetic particles in harsh radiation environments have become a considerable reliability concern for ICs. To overcome the limitations of current radiation-hardened designs regarding overhead and reliability, this paper proposes a high-performance, low-area-overhead, and low-delay TNU self-recoverable latch (HLLT) based on N-type stacked transistors for aerospace applications. The proposed HLLT latch comprises three symmetrical modules that protect each other. In addition, high-speed path and clock gating technology are employed to reduce delay overhead and power consumption, respectively. Simulation results show that, compared to five existing TNU-recoverable latches, the proposed HLLT latch achieves average reductions of 29.97 %, 57.12 %, 36.52 %, and 83.00 % in area overhead, power consumption, delay, and area-power-delay-product (APDP), respectively. Furthermore, the proposed HLLT latch has lower sensitivity and better stability to variations in PVT (Process, Voltage, Temperature).</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"172 ","pages":"Article 115830"},"PeriodicalIF":1.6,"publicationDate":"2025-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144321985","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Thermo-electrical reliability of power MOSFETs influenced by packaging architecture in stack-die and single-die configurations","authors":"You-Cheol Jang","doi":"10.1016/j.microrel.2025.115831","DOIUrl":"10.1016/j.microrel.2025.115831","url":null,"abstract":"<div><div>As the demand for high-power semiconductor devices continues to grow, wide bandgap (WBG) MOSFETs are being increasingly adopted across diverse power electronic applications. Compared to conventional Si-based MOSFETs, however, the reliability characteristics of WBG devices, particularly those employing cascode GaN configurations, remain inadequately explored from a packaging standpoint. This study presents a comparative investigation of degradation mechanisms and failure modes in a 650 V vertical Si MOSFET with a single-die package and a cascode GaN FET integrated with a Si MOSFET in a stack-die configuration. A Highly Accelerated Life Test (HALT) combining temperature and power cycling was implemented, with the Coffin-Manson model yielding an acceleration factor of 1.66, thereby reducing the total test time by 14 h. In parallel, gate bias stress was evaluated using Weibull distribution modeling, which identified 30 <em>V</em> as a critical threshold for initiating accelerated degradation without immediate device breakdown.</div><div>The results demonstrate that packaging architecture significantly influences solder joint degradation and overall thermal performance. The findings also confirm the value of the proposed HALT methodology in efficiently identifying failure mechanisms, providing actionable insights into the packaging reliability of 650 <em>V</em> power MOSFETs under harsh operating conditions.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"172 ","pages":"Article 115831"},"PeriodicalIF":1.6,"publicationDate":"2025-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144321984","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Design of an energy-efficient soft error resilient RHBD SRAM cell with high read stability and minimum write errors","authors":"Biby Joseph,&nbsp;R.K. Kavitha","doi":"10.1016/j.microrel.2025.115812","DOIUrl":"10.1016/j.microrel.2025.115812","url":null,"abstract":"<div><div>This article proposes an energy-efficient, soft-error tolerant, read-stability improved SRAM cell with less Write Error Rate (WER). The proposed S8P9N has 8 PMOS and 9 NMOS transistors including access transistors. This SRAM cell has only two sensitive nodes, achieved by surrounding the nodes with the same type of transistors. The proposed cell is immune to all Single Event Upsets (SEUs) at sensitive nodes and shows 83.3% and 50% tolerance to Double Node Upsets (DNUs) and Triple Node Upsets (TNUs) respectively. The four access transistors in the S8P9N cell reduce write delay, and WER. Additionally, the proposed SRAM cell achieves the lowest dynamic power dissipation of 1.25 <span><math><mi>μ</mi></math></span>W, high read stability of 320 mW, and low read and write energy of 0.83 aJ and 0.07 fJ, respectively. All designs are implemented using UMC 65 nm technology, operating at a supply voltage of 1.2 V and at a temperature of 27 °<span><math><mi>C</mi></math></span>. Reliability is analyzed through 5000-point Monte Carlo (MC) simulation under various Process Voltage Temperature (PVT) conditions. The proposed design has a critical charge, Qc of <span><math><mo>&gt;</mo></math></span> 90 fC . The S8P9N RHBD SRAM cell has a minimum soft error occurrence probability (P<span><math><msub><mrow></mrow><mrow><mi>S</mi></mrow></msub></math></span>) of 1.6%. The combination of low power consumption, low energy, high read stability, less write error rate of <span><math><mo>&lt;</mo></math></span> 0.1%, and improved reliability makes the S8P9N design suitable for low-power cache in aerospace applications.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"172 ","pages":"Article 115812"},"PeriodicalIF":1.6,"publicationDate":"2025-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144313800","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Interfacial fracture behavior of polyimide/copper in RDL structures for advanced electronic packaging","authors":"Wenqing Chen ,&nbsp;Yuexing Wang ,&nbsp;Bofeng Li ,&nbsp;Shuai Yao ,&nbsp;Jichao Qiao ,&nbsp;Xiangyu Sun","doi":"10.1016/j.microrel.2025.115829","DOIUrl":"10.1016/j.microrel.2025.115829","url":null,"abstract":"<div><div>Polyimide (PI) is widely used in the fabrication of redistribution layers (RDL) for fan-out packaging due to its excellent mechanical properties. However, the miniaturization of electronic components has posed numerous new challenges to the electronics manufacturing industry. As an important part for signal redistribution and structure support, the evaluation of the structural stability of RDL has become an urgent issue in advanced packaging. In this study, PI/Cu lap joint specimens were used to investigate the mechanical properties and interfacial adhesion performance of PI under different curing conditions. Through lap shear tests, scanning electron microscopy (SEM) analysis, and finite element method (FEM) simulation, the applicability of PI in packaging structures was systematically analyzed. The results show that PI sintered at high temperature exhibits good structural stability and is less prone to crack formation during deformation. But it has relatively low fracture toughness and strength, and tends to delaminate from Cu, making it unsuitable for structures subjected to large deformations. In contrast, PI cured at room temperature demonstrates higher fracture strength and better interfacial adhesion, as well as greater deformability, but is more prone to crack initiation, making it less suitable for structures under long-term loading. This study not only reveals the influence mechanism of curing conditions on the structural properties and adhesion performance of PI, but also provides theoretical support and research guidance for the manufacturing of RDL and the optimization of PI forming processes in advanced packaging.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"172 ","pages":"Article 115829"},"PeriodicalIF":1.6,"publicationDate":"2025-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144297649","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Thermal-mechanical analysis of copper pillar pitch size during reflow soldering assembly process","authors":"Jing Rou Lee ,&nbsp;Mohd Sharizal Abdul Aziz ,&nbsp;Chu Yee Khor ,&nbsp;Mohammad Hafifi Hafiz Ishaik ,&nbsp;Janter Pangaduan Simanjuntak ,&nbsp;Yong Jie Wong","doi":"10.1016/j.microrel.2025.115827","DOIUrl":"10.1016/j.microrel.2025.115827","url":null,"abstract":"<div><div>This study investigates the effect of pitch sizes on the thermal and mechanical performance of the copper (Cu) pillar bumps during the reflow soldering assembly process. The simulated reflow temperature is compared with the experimental result, which is in good agreement. The simulated flow field reveals that radiation is the dominant heat transfer mode in the reflow oven. Moreover, the heat transfer is affected by airflow circulation, leading to uneven temperature distribution and temperature deviations between the bumps. The simulation results demonstrate that overall reflow temperature, the temperature difference between peak temperatures of bumps, deformation, and stress-strain distribution significantly impact Cu pillar bump reliability. Pitch size of 0.40 mm yielded minor total deformation and the lowest stress distribution. Thus, this study provides a comprehensive guide for monitoring the temperature distributions on Cu pillar bumps and their capability to resist deformation and stress strain, which are crucial criteria for achieving high-quality bonding and reliable electronic products during the reflow soldering assembly process.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"172 ","pages":"Article 115827"},"PeriodicalIF":1.6,"publicationDate":"2025-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144297650","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Reading reliability analysis and modeling in 1S1R devices based on Phase-Change Memory and Ovonic Threshold Switching selector integrated in a double-patterned self-aligned structure","authors":"Renzo Antonelli ,&nbsp;C. De Camaret ,&nbsp;G. Bourgeois ,&nbsp;Z. Saghi ,&nbsp;T. Monniez ,&nbsp;S. Martin ,&nbsp;N. Castellani ,&nbsp;M. Bernard ,&nbsp;L. Fellouh ,&nbsp;A. Salvi ,&nbsp;S. Gout ,&nbsp;F. Andrieu ,&nbsp;A. Souifi ,&nbsp;G. Navarro","doi":"10.1016/j.microrel.2025.115801","DOIUrl":"10.1016/j.microrel.2025.115801","url":null,"abstract":"<div><div>This study investigates the impact and the reliability of the reading operation in one-selector one-resistor (1S1R) memory devices based on an Ovonic Threshold Switching (OTS) selector and Phase Change Memory (PCM) co-integrated in a Double-Patterned Self-Aligned (DPSA) structure targeting Crossbar applications. Upon reading, the SET state can face a threshold voltage (V_th) increase of more than 20% depending on the reading current and on the number of reading operations, which can lead to a bit-flip soft failure. We isolate the contributions to this increase coming respectively from the OTS and the PCM, providing an assessment protocol for the reading reliability. We model the evolution of the V_th, which allow us to extract the performance metrics such as the read window margin (RWM), the reading-cycles-to-failure, and the maximum Crossbar array size. Finally, we present the SET and RESET threshold voltage distributions before and after the reading operation.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"172 ","pages":"Article 115801"},"PeriodicalIF":1.6,"publicationDate":"2025-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144279802","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Solder joint reliability predictions using physics-informed machine learning","authors":"S.D.M. de Jong ,&nbsp;A.G. Ghezeljehmeidan ,&nbsp;W.D. van Driel","doi":"10.1016/j.microrel.2025.115797","DOIUrl":"10.1016/j.microrel.2025.115797","url":null,"abstract":"<div><div>The reliability of solder joints plays an increasingly important role in power electronics. The thermal fatigue experienced due to the temperature fluctuations cause catastrophic failures. However, the ability to predict the fatigue for different thermal cycles is lacking. Experimental or simulation based approaches are typically too expensive to be conducted for a wide range of thermal loading conditions. A physics informed Long Short-Term Memory (PI-LSTM) is proposed here for predicting the plastic strain and related fatigue lifetime in solder joints. The LSTM model is trained on data generated by FEM simulations, enhanced by incorporating the flow rule into the loss function. The PI-LSTM accurately predicts the plastic strain and the stress components, enabling efficient reliability predictions. Using different reliability models, the estimated cycles to failure are found to be in close agreement with those from conventional FEM simulations, demonstrating the PI-LSTM’s capability for reliability assessments.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"172 ","pages":"Article 115797"},"PeriodicalIF":1.6,"publicationDate":"2025-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144272002","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Separate investigation of performance degradation for the Si and GaN parts in cascode GaN devices under repetitive short circuits","authors":"Zhebie Lu,&nbsp;Francesco Iannuzzo","doi":"10.1016/j.microrel.2025.115779","DOIUrl":"10.1016/j.microrel.2025.115779","url":null,"abstract":"<div><div>In this paper, the performance degradation under repetitive short circuits was investigated for the Si and GaN separately in cascode GaN devices. Self-sustained oscillation is a main obstacle in deeper studying the short-circuit characteristics of cascode GaN devices, in many cases, the device is damaged by the self-sustained oscillations rather than the thermal/electrical stress of short circuits. To avoid the self-sustained oscillations during short circuits, a modified short-circuit test platform is proposed to conduct the short-circuit test safely. To characterize the static performance of the Si and GaN parts separately in a fair way, a new decapsulation method without affecting the die performance is proposed on a commercial cascode GaN device. Considering the trap effect on GaN devices, a fair test procedure is designed to avoid the influence brought by the fluctuation of the GaN threshold voltage. In the end, the performance degradation is analysed after going through repetitive short-circuit tests under 100 V/10 μs. The results show that the on-state resistance increases after short circuits, the Si part is responsible for 38 % in it and the GaN part is responsible for 62 % in it. The threshold of Si part is not changed while the threshold of GaN part increases.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"172 ","pages":"Article 115779"},"PeriodicalIF":1.6,"publicationDate":"2025-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144262152","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}