Microelectronics Reliability最新文献_第8页

Thermo-electrical reliability of power MOSFETs influenced by packaging architecture in stack-die and single-die configurations 封装结构对功率mosfet热电可靠性的影响

IF 1.6 4区工程技术

Microelectronics Reliability Pub Date : 2025-06-20 DOI: 10.1016/j.microrel.2025.115831

You-Cheol Jang

{"title":"Thermo-electrical reliability of power MOSFETs influenced by packaging architecture in stack-die and single-die configurations","authors":"You-Cheol Jang","doi":"10.1016/j.microrel.2025.115831","DOIUrl":"10.1016/j.microrel.2025.115831","url":null,"abstract":"<div><div>As the demand for high-power semiconductor devices continues to grow, wide bandgap (WBG) MOSFETs are being increasingly adopted across diverse power electronic applications. Compared to conventional Si-based MOSFETs, however, the reliability characteristics of WBG devices, particularly those employing cascode GaN configurations, remain inadequately explored from a packaging standpoint. This study presents a comparative investigation of degradation mechanisms and failure modes in a 650 V vertical Si MOSFET with a single-die package and a cascode GaN FET integrated with a Si MOSFET in a stack-die configuration. A Highly Accelerated Life Test (HALT) combining temperature and power cycling was implemented, with the Coffin-Manson model yielding an acceleration factor of 1.66, thereby reducing the total test time by 14 h. In parallel, gate bias stress was evaluated using Weibull distribution modeling, which identified 30 <em>V</em> as a critical threshold for initiating accelerated degradation without immediate device breakdown.</div><div>The results demonstrate that packaging architecture significantly influences solder joint degradation and overall thermal performance. The findings also confirm the value of the proposed HALT methodology in efficiently identifying failure mechanisms, providing actionable insights into the packaging reliability of 650 <em>V</em> power MOSFETs under harsh operating conditions.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"172 ","pages":"Article 115831"},"PeriodicalIF":1.6,"publicationDate":"2025-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144321984","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Design of an energy-efficient soft error resilient RHBD SRAM cell with high read stability and minimum write errors 具有高读取稳定性和最小写入错误的节能软错误弹性RHBD SRAM单元的设计

IF 1.6 4区工程技术

Microelectronics Reliability Pub Date : 2025-06-19 DOI: 10.1016/j.microrel.2025.115812

Biby Joseph, R.K. Kavitha

{"title":"Design of an energy-efficient soft error resilient RHBD SRAM cell with high read stability and minimum write errors","authors":"Biby Joseph, R.K. Kavitha","doi":"10.1016/j.microrel.2025.115812","DOIUrl":"10.1016/j.microrel.2025.115812","url":null,"abstract":"<div><div>This article proposes an energy-efficient, soft-error tolerant, read-stability improved SRAM cell with less Write Error Rate (WER). The proposed S8P9N has 8 PMOS and 9 NMOS transistors including access transistors. This SRAM cell has only two sensitive nodes, achieved by surrounding the nodes with the same type of transistors. The proposed cell is immune to all Single Event Upsets (SEUs) at sensitive nodes and shows 83.3% and 50% tolerance to Double Node Upsets (DNUs) and Triple Node Upsets (TNUs) respectively. The four access transistors in the S8P9N cell reduce write delay, and WER. Additionally, the proposed SRAM cell achieves the lowest dynamic power dissipation of 1.25 <span><math><mi>μ</mi></math></span>W, high read stability of 320 mW, and low read and write energy of 0.83 aJ and 0.07 fJ, respectively. All designs are implemented using UMC 65 nm technology, operating at a supply voltage of 1.2 V and at a temperature of 27 °<span><math><mi>C</mi></math></span>. Reliability is analyzed through 5000-point Monte Carlo (MC) simulation under various Process Voltage Temperature (PVT) conditions. The proposed design has a critical charge, Qc of <span><math><mo>></mo></math></span> 90 fC . The S8P9N RHBD SRAM cell has a minimum soft error occurrence probability (P<span><math><msub><mrow></mrow><mrow><mi>S</mi></mrow></msub></math></span>) of 1.6%. The combination of low power consumption, low energy, high read stability, less write error rate of <span><math><mo><</mo></math></span> 0.1%, and improved reliability makes the S8P9N design suitable for low-power cache in aerospace applications.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"172 ","pages":"Article 115812"},"PeriodicalIF":1.6,"publicationDate":"2025-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144313800","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Interfacial fracture behavior of polyimide/copper in RDL structures for advanced electronic packaging 先进电子封装用RDL结构中聚酰亚胺/铜的界面断裂行为

IF 1.6 4区工程技术

Microelectronics Reliability Pub Date : 2025-06-17 DOI: 10.1016/j.microrel.2025.115829

Wenqing Chen , Yuexing Wang , Bofeng Li , Shuai Yao , Jichao Qiao , Xiangyu Sun

{"title":"Interfacial fracture behavior of polyimide/copper in RDL structures for advanced electronic packaging","authors":"Wenqing Chen , Yuexing Wang , Bofeng Li , Shuai Yao , Jichao Qiao , Xiangyu Sun","doi":"10.1016/j.microrel.2025.115829","DOIUrl":"10.1016/j.microrel.2025.115829","url":null,"abstract":"<div><div>Polyimide (PI) is widely used in the fabrication of redistribution layers (RDL) for fan-out packaging due to its excellent mechanical properties. However, the miniaturization of electronic components has posed numerous new challenges to the electronics manufacturing industry. As an important part for signal redistribution and structure support, the evaluation of the structural stability of RDL has become an urgent issue in advanced packaging. In this study, PI/Cu lap joint specimens were used to investigate the mechanical properties and interfacial adhesion performance of PI under different curing conditions. Through lap shear tests, scanning electron microscopy (SEM) analysis, and finite element method (FEM) simulation, the applicability of PI in packaging structures was systematically analyzed. The results show that PI sintered at high temperature exhibits good structural stability and is less prone to crack formation during deformation. But it has relatively low fracture toughness and strength, and tends to delaminate from Cu, making it unsuitable for structures subjected to large deformations. In contrast, PI cured at room temperature demonstrates higher fracture strength and better interfacial adhesion, as well as greater deformability, but is more prone to crack initiation, making it less suitable for structures under long-term loading. This study not only reveals the influence mechanism of curing conditions on the structural properties and adhesion performance of PI, but also provides theoretical support and research guidance for the manufacturing of RDL and the optimization of PI forming processes in advanced packaging.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"172 ","pages":"Article 115829"},"PeriodicalIF":1.6,"publicationDate":"2025-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144297649","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Thermal-mechanical analysis of copper pillar pitch size during reflow soldering assembly process 回流焊装配过程中铜柱节距尺寸的热-力学分析

IF 1.6 4区工程技术

Microelectronics Reliability Pub Date : 2025-06-17 DOI: 10.1016/j.microrel.2025.115827

Jing Rou Lee , Mohd Sharizal Abdul Aziz , Chu Yee Khor , Mohammad Hafifi Hafiz Ishaik , Janter Pangaduan Simanjuntak , Yong Jie Wong

{"title":"Thermal-mechanical analysis of copper pillar pitch size during reflow soldering assembly process","authors":"Jing Rou Lee , Mohd Sharizal Abdul Aziz , Chu Yee Khor , Mohammad Hafifi Hafiz Ishaik , Janter Pangaduan Simanjuntak , Yong Jie Wong","doi":"10.1016/j.microrel.2025.115827","DOIUrl":"10.1016/j.microrel.2025.115827","url":null,"abstract":"<div><div>This study investigates the effect of pitch sizes on the thermal and mechanical performance of the copper (Cu) pillar bumps during the reflow soldering assembly process. The simulated reflow temperature is compared with the experimental result, which is in good agreement. The simulated flow field reveals that radiation is the dominant heat transfer mode in the reflow oven. Moreover, the heat transfer is affected by airflow circulation, leading to uneven temperature distribution and temperature deviations between the bumps. The simulation results demonstrate that overall reflow temperature, the temperature difference between peak temperatures of bumps, deformation, and stress-strain distribution significantly impact Cu pillar bump reliability. Pitch size of 0.40 mm yielded minor total deformation and the lowest stress distribution. Thus, this study provides a comprehensive guide for monitoring the temperature distributions on Cu pillar bumps and their capability to resist deformation and stress strain, which are crucial criteria for achieving high-quality bonding and reliable electronic products during the reflow soldering assembly process.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"172 ","pages":"Article 115827"},"PeriodicalIF":1.6,"publicationDate":"2025-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144297650","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Reading reliability analysis and modeling in 1S1R devices based on Phase-Change Memory and Ovonic Threshold Switching selector integrated in a double-patterned self-aligned structure 基于相位存储器和Ovonic阈值开关选择器集成在双模式自对准结构中的1S1R器件读取可靠性分析与建模

IF 1.6 4区工程技术

Microelectronics Reliability Pub Date : 2025-06-14 DOI: 10.1016/j.microrel.2025.115801

Renzo Antonelli , C. De Camaret , G. Bourgeois , Z. Saghi , T. Monniez , S. Martin , N. Castellani , M. Bernard , L. Fellouh , A. Salvi , S. Gout , F. Andrieu , A. Souifi , G. Navarro

{"title":"Reading reliability analysis and modeling in 1S1R devices based on Phase-Change Memory and Ovonic Threshold Switching selector integrated in a double-patterned self-aligned structure","authors":"Renzo Antonelli , C. De Camaret , G. Bourgeois , Z. Saghi , T. Monniez , S. Martin , N. Castellani , M. Bernard , L. Fellouh , A. Salvi , S. Gout , F. Andrieu , A. Souifi , G. Navarro","doi":"10.1016/j.microrel.2025.115801","DOIUrl":"10.1016/j.microrel.2025.115801","url":null,"abstract":"<div><div>This study investigates the impact and the reliability of the reading operation in one-selector one-resistor (1S1R) memory devices based on an Ovonic Threshold Switching (OTS) selector and Phase Change Memory (PCM) co-integrated in a Double-Patterned Self-Aligned (DPSA) structure targeting Crossbar applications. Upon reading, the SET state can face a threshold voltage (V<sub>th</sub>) increase of more than 20% depending on the reading current and on the number of reading operations, which can lead to a bit-flip soft failure. We isolate the contributions to this increase coming respectively from the OTS and the PCM, providing an assessment protocol for the reading reliability. We model the evolution of the V<sub>th</sub>, which allow us to extract the performance metrics such as the read window margin (RWM), the reading-cycles-to-failure, and the maximum Crossbar array size. Finally, we present the SET and RESET threshold voltage distributions before and after the reading operation.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"172 ","pages":"Article 115801"},"PeriodicalIF":1.6,"publicationDate":"2025-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144279802","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Solder joint reliability predictions using physics-informed machine learning 利用物理信息的机器学习进行焊点可靠性预测

IF 1.6 4区工程技术

Microelectronics Reliability Pub Date : 2025-06-12 DOI: 10.1016/j.microrel.2025.115797

S.D.M. de Jong , A.G. Ghezeljehmeidan , W.D. van Driel

引用次数: 0

Separate investigation of performance degradation for the Si and GaN parts in cascode GaN devices under repetitive short circuits 重复短路下级联GaN器件中Si和GaN部分性能退化的单独研究

IF 1.6 4区工程技术

Microelectronics Reliability Pub Date : 2025-06-12 DOI: 10.1016/j.microrel.2025.115779

Zhebie Lu, Francesco Iannuzzo

{"title":"Separate investigation of performance degradation for the Si and GaN parts in cascode GaN devices under repetitive short circuits","authors":"Zhebie Lu, Francesco Iannuzzo","doi":"10.1016/j.microrel.2025.115779","DOIUrl":"10.1016/j.microrel.2025.115779","url":null,"abstract":"<div><div>In this paper, the performance degradation under repetitive short circuits was investigated for the Si and GaN separately in cascode GaN devices. Self-sustained oscillation is a main obstacle in deeper studying the short-circuit characteristics of cascode GaN devices, in many cases, the device is damaged by the self-sustained oscillations rather than the thermal/electrical stress of short circuits. To avoid the self-sustained oscillations during short circuits, a modified short-circuit test platform is proposed to conduct the short-circuit test safely. To characterize the static performance of the Si and GaN parts separately in a fair way, a new decapsulation method without affecting the die performance is proposed on a commercial cascode GaN device. Considering the trap effect on GaN devices, a fair test procedure is designed to avoid the influence brought by the fluctuation of the GaN threshold voltage. In the end, the performance degradation is analysed after going through repetitive short-circuit tests under 100 V/10 μs. The results show that the on-state resistance increases after short circuits, the Si part is responsible for 38 % in it and the GaN part is responsible for 62 % in it. The threshold of Si part is not changed while the threshold of GaN part increases.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"172 ","pages":"Article 115779"},"PeriodicalIF":1.6,"publicationDate":"2025-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144262152","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Mechanical and electrical testing of encapsulated stretchable substrate interconnect models for emerging flexible electronic systems 新兴柔性电子系统封装可拉伸衬底互连模型的机械和电气测试

IF 1.6 4区工程技术

Microelectronics Reliability Pub Date : 2025-06-11 DOI: 10.1016/j.microrel.2025.115824

Gulafsha Bhatti , Yash Agrawal , Vinay Palaparthy , Rohit Sharma , Mekala Girish Kumar

{"title":"Mechanical and electrical testing of encapsulated stretchable substrate interconnect models for emerging flexible electronic systems","authors":"Gulafsha Bhatti , Yash Agrawal , Vinay Palaparthy , Rohit Sharma , Mekala Girish Kumar","doi":"10.1016/j.microrel.2025.115824","DOIUrl":"10.1016/j.microrel.2025.115824","url":null,"abstract":"<div><div>Flexible electronics (FE) technology incorporates stretchable interconnects to enable devices those conform to irregular surfaces, bend and stretch without sacrificing functionality. These interconnects are crafted of specialized materials and designs those can withstand mechanical deformations with facilitating seamless integration of electronic components. Serpentine structures are widely used in flexible and stretchable interconnect. However, understanding their mechanical properties under different design parameters is crucial for optimal performance and reliability. In this work, through finite element analysis (FEA), the mechanical behaviour of serpentine interconnect structures with varying geometric parameters, along with and without encapsulation layer is novely investigated. The silver (Ag) material is used as conductor, while both substrate and encapsulation layers are formed using polydimethylsiloxane (PDMS). Also, the effect of mesh analysis is performed on the stretching of the considered interconnect models. Further, the Coffin-Mansons law based fatigue cycle test and the conductivity of the interconnect are analyzed. Finally, the simulation results are validated with experimental results. This research provides essential insightful observations on the interplay between design parameters, mechanical and electrical behaviour for the development of robust stretchable interconnect geometry in flexible electronic systems.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"172 ","pages":"Article 115824"},"PeriodicalIF":1.6,"publicationDate":"2025-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144262153","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Gate oxide lifetime modeling of vertical SiC-MOS under accelerated reverse bias (ARB) 加速反向偏压（ARB）下垂直SiC-MOS栅氧化寿命建模

IF 1.6 4区工程技术

Microelectronics Reliability Pub Date : 2025-06-10 DOI: 10.1016/j.microrel.2025.115825

Ayan K. Biswas, Daniel J. Lichtenwalner, Brett Hull, Donald A. Gajewski

引用次数: 0

Machine learning-based surrogate models for finned heatsink thermal modeling 基于机器学习的翅片散热器热建模代理模型

IF 1.6 4区工程技术

Microelectronics Reliability Pub Date : 2025-06-06 DOI: 10.1016/j.microrel.2025.115775

Z. Wang, Y. Zhang, H. Wang

引用次数: 0