Microelectronics Reliability最新文献_第8页

Cause analysis on abnormal defects between metal layers of IGBT dies for power modules

IF 1.6 4区工程技术

Microelectronics Reliability Pub Date : 2025-03-01 DOI: 10.1016/j.microrel.2025.115642

Jie Chen , Yi Gong , Zhen-Guo Yang

{"title":"Cause analysis on abnormal defects between metal layers of IGBT dies for power modules","authors":"Jie Chen , Yi Gong , Zhen-Guo Yang","doi":"10.1016/j.microrel.2025.115642","DOIUrl":"10.1016/j.microrel.2025.115642","url":null,"abstract":"<div><div>IGBT dies are widely applied in power modules for new energy vehicles at present, and meanwhile, the reliability has been a research emphasis. As addressed in this paper, abnormal defects at the Al-Ni interfaces of IGBT dies resulted in the failure of power modules for new energy vehicles during the power cycling tests. Based on the failure characteristics, a systematical investigation was conducted to explore the root causes of these defects through a series of study methods such as process traceability, characterization analysis and theoretical analysis. At last, the root causes of the failure were determined through the comprehensive analysis. Furthermore, the formation processes of abnormal defects under different states were reverted, and the detailed formation mechanisms were also confirmed from the special separation characteristics at the Al-Ni interface. Besides, the corresponding countermeasures were also proposed according to the conclusions obtained. It was believed that the achievements would help improve the preparation quality of metal layers of IGBT dies and enhance the integral reliability of power modules for new energy vehicles.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"167 ","pages":"Article 115642"},"PeriodicalIF":1.6,"publicationDate":"2025-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143519529","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Evolution analysis of mechanical behaviours of through‑silicon via under thermal cycling load

IF 1.6 4区工程技术

Microelectronics Reliability Pub Date : 2025-03-01 DOI: 10.1016/j.microrel.2025.115647

Kaihong Hou , Zhengwei Fan , Xun Chen , Shufeng Zhang , Yashun Wang , Yu Jiang

{"title":"Evolution analysis of mechanical behaviours of through‑silicon via under thermal cycling load","authors":"Kaihong Hou , Zhengwei Fan , Xun Chen , Shufeng Zhang , Yashun Wang , Yu Jiang","doi":"10.1016/j.microrel.2025.115647","DOIUrl":"10.1016/j.microrel.2025.115647","url":null,"abstract":"<div><div>As the key interconnecting structure of high-performance 3D chips, through‑silicon via (TSV) is of great significance to improve the packaging efficiency and computing performance of chips. However, under the increasingly complex and severe service environment, the failure mechanism of TSV is increasingly becoming a key problem hindering the development of 3D chips in the future. In this study, based on the crystal plasticity theory and with the help of literature data, the plasticity constitutive considering thermal expansion coefficient and temperature dependent plasticity parameters is constructed to simulate the mechanical behavior evolution mechanism of TSV under thermal cycling load. Results show that the mean Cu grain area increases from 55.42 μm<sup>2</sup> to 65.74 μm<sup>2</sup> after thermal cyclic loading, and the mean misorientation angle decreases from 41.34° to 35.53° correspondingly. The stability at the grain boundary is lower than that inside the grain, which can be proof by the resolved shear stress distribution, shear rate distribution and slip resistance distribution in different slip system. This study can be regard as the basis for the reliability research in extreme service environments, and has certain reference significance for promoting the development of 3D chips.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"167 ","pages":"Article 115647"},"PeriodicalIF":1.6,"publicationDate":"2025-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143527162","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Experimental and numerical analysis of cyclic ratchetting and low cycle fatigue behaviour in meander-shaped interconnects for stretchable electronics applications

IF 1.6 4区工程技术

Microelectronics Reliability Pub Date : 2025-03-01 DOI: 10.1016/j.microrel.2025.115632

Amir Sarikhan Khelejani , Amir Jahanshahi , Mahnaz Shamshirsaz

{"title":"Experimental and numerical analysis of cyclic ratchetting and low cycle fatigue behaviour in meander-shaped interconnects for stretchable electronics applications","authors":"Amir Sarikhan Khelejani , Amir Jahanshahi , Mahnaz Shamshirsaz","doi":"10.1016/j.microrel.2025.115632","DOIUrl":"10.1016/j.microrel.2025.115632","url":null,"abstract":"<div><div>Stretchable interconnect is a crucial component of a wearable device, responsible for establishing electrical connections throughout the system. Among various technologies, thin film-based interconnects provide superior electrical conductivity comparable to bulk metals, enabling high-quality signals in diverse wearable applications. Nevertheless, their relatively low mechanical fatigue life remains a significant challenge. Research has shown that flexible polymer-supported interconnects exhibit improved fatigue life compared to non-supported counterparts.</div><div>Albeit widespread adoption of thin film-based stretchable tracks, underlying physical principles governing their fatigue life is not thoroughly studied. In this work, stretchable interconnects are fabricated and analysed using a cost-effective method suitable for mass fabrication. This study focuses on modelling of the stretchable interconnects using FEM under both static and dynamic loadings to discover the significant role of flexible polymer in increasing the cyclic fatigue life. Polyimide (PI)-supported interconnects show a major decrease (~ 20 %) in maximum strain under static load compared to non-supported interconnects. It has been demonstrated that under dynamic loading, non-supported interconnects fail mostly based on ratcheting strain, whereas low cycle fatigue (LCF) governs the failure mechanism of PI supported tracks. The latter happens due to the beneficial residual stress imposed by the flexible support layer. The findings are supported by characterizing the experimentally fabricated stretchable interconnects.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"167 ","pages":"Article 115632"},"PeriodicalIF":1.6,"publicationDate":"2025-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143519527","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

The impact of mold compound on power cycling capability of SiC MOSFETs in double sided cooled modules

IF 1.6 4区工程技术

Microelectronics Reliability Pub Date : 2025-03-01 DOI: 10.1016/j.microrel.2025.115655

T. Lentzsch, J. Lutz, T. Basler

引用次数: 0

Enhancing long-term thermal reliability of sintered joints through the use of silver-coated copper particles

IF 1.6 4区工程技术

Microelectronics Reliability Pub Date : 2025-02-28 DOI: 10.1016/j.microrel.2025.115654

Dajung Kim, Mi so Won, Hyunseung Yang, Chulmin Oh

{"title":"Enhancing long-term thermal reliability of sintered joints through the use of silver-coated copper particles","authors":"Dajung Kim, Mi so Won, Hyunseung Yang, Chulmin Oh","doi":"10.1016/j.microrel.2025.115654","DOIUrl":"10.1016/j.microrel.2025.115654","url":null,"abstract":"<div><div>This study investigated the long-term thermal reliability of a sintering paste incorporating Ag-coated Cu (Cu@Ag) particles to inhibit copper oxidation. After thermal aging, shear strength increased in Cu@Ag joints under inert and air atmospheres, showing different microstructures. In an inert atmosphere, a Cu<img>Cu sintering network emerged, while in air, atmosphere facilitated the formation of a Cu<sub>2</sub>O network encasing the Cu@Ag particles within the sintered joint. Subsequent analyses of the sintered joint microstructures, post long-term thermal reliability testing and differentiated by pressurization and non-pressurization in air, unveiled further disparities. Pressurized samples exhibited a dense sintering network within the joint microstructure that restricted oxygen access to copper, leading to a thin Cu<sub>2</sub>O shell encapsulating the copper particles. Conversely, non-pressurized samples featured a porous sintering network, enabling direct contact between copper and oxygen during thermal aging and the formation of a significant Cu<sub>2</sub>O bulk network. The fracture modes also varied between the pressurized and non-pressurized samples, with ductile fracture observed in the former and brittle fracture in the latter. Based on these findings, this study proposes an optimal microstructure for the Cu@Ag paste, promoting the use of a Cu@Ag sintering paste as a cost-effective and antioxidative approach for enhancing thermal reliability.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"167 ","pages":"Article 115654"},"PeriodicalIF":1.6,"publicationDate":"2025-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143519525","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Laser voltage probing and simulation of a flip-flop with undesired quasi-static switching

IF 1.6 4区工程技术

Microelectronics Reliability Pub Date : 2025-02-28 DOI: 10.1016/j.microrel.2025.115637

A.A. Merassi , T. Melis

引用次数: 0

Failure analysis and simulation of IGBT under active and passive thermal cycling

IF 1.6 4区工程技术

Microelectronics Reliability Pub Date : 2025-02-28 DOI: 10.1016/j.microrel.2025.115638

Jing Han , Xin Li , Tong An , Yishu Wang , Fu Guo

引用次数: 0

Degradation modeling of InGaAs/InP avalanche photodiodes using calibrated technology computer-aided design

IF 1.6 4区工程技术

Microelectronics Reliability Pub Date : 2025-02-27 DOI: 10.1016/j.microrel.2025.115636

Heewon Bang , Yunseok Han , Sunho Kim , Ilgu Yun

{"title":"Degradation modeling of InGaAs/InP avalanche photodiodes using calibrated technology computer-aided design","authors":"Heewon Bang , Yunseok Han , Sunho Kim , Ilgu Yun","doi":"10.1016/j.microrel.2025.115636","DOIUrl":"10.1016/j.microrel.2025.115636","url":null,"abstract":"<div><div>In this study, the degradation models of InGaAs/InP avalanche photodiodes (APDs) are proposed based on accelerated life testing (ALT) using technology computer-aided design (TCAD). Degradation modes identified by ALT are categorized into three types: (1) dark current (I<sub>D</sub>) increase, (2) breakdown voltage (V<sub>BR</sub>) reduction, and (3) the combination of (1) and (2). Two possible degradation mechanisms are suggested based on TCAD simulation: surface degradation for increasing I<sub>D</sub> and Zn penetration for decreasing V<sub>BR</sub>. After the initial I-V calibration using TCAD simulations, key degradation parameters were calibrated with ALT results to model the degraded characteristics of the APDs. As a result, an increase in the surface trap density of states at the SiN<sub>x</sub>/InP interface (N<sub>int</sub>) and the fixed charge at the SiN<sub>x</sub>/InP interface (Q<sub>int</sub>) leads to an increase in I<sub>D</sub> at the InP/SiN<sub>x</sub> surface. In addition, a doping region was added with a gaussian function profile to model Zn penetration. An increase in the degradation parameter (α) within the gaussian equation leads to a decrease in V<sub>BR</sub>. The degradation models are investigated to evaluate changes in the structural and material properties over ALT time and performance of APDs. This study contributes to the understanding of degradation processes in InGaAs/InP APDs and also provides valuable insights into the analysis of device characteristics through similar reliability tests without the need for destructive or chemical analysis.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"167 ","pages":"Article 115636"},"PeriodicalIF":1.6,"publicationDate":"2025-02-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143508957","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Changes in the extraction and collection efficiency of GaN-based MQW solar cells under optical step-stress

IF 1.6 4区工程技术

Microelectronics Reliability Pub Date : 2025-02-27 DOI: 10.1016/j.microrel.2025.115633

M. Nicoletto , S. Bertin , A. Caria , N. Roccato , C. De Santi , M. Buffolo , G. Meneghesso , E. Zanoni , M. Meneghini

{"title":"Changes in the extraction and collection efficiency of GaN-based MQW solar cells under optical step-stress","authors":"M. Nicoletto , S. Bertin , A. Caria , N. Roccato , C. De Santi , M. Buffolo , G. Meneghesso , E. Zanoni , M. Meneghini","doi":"10.1016/j.microrel.2025.115633","DOIUrl":"10.1016/j.microrel.2025.115633","url":null,"abstract":"<div><div>InGaN/GaN multiple quantum well (MQWs) solar cells are promising devices for application in harsh environments. However, understanding their degradation kinetics can be complicated by the high periodicity of the active region (AR). To overcome this issue, we carried out an experiment on structures with only two quantum wells, having different indium concentrations, that were submitted to an optical power step stress at 55 °C. Firstly, illuminated current-voltage (I-V) characterizations indicate that the QW near the p-side of the device strongly contributes to carrier collection. This is explained by the enhanced hole extraction and collection efficiency. Notably, a non-monotonic ‘hump effect’ emerges when the device design is suboptimal. Secondly, during optical power step stress, two key phenomena were observed: a) a reduction in short-circuit current (Isc), especially at high excitation intensities; b) an increase in current conduction below the main diode turn-on voltage, which is ascribed to the increased amount of traps in the active region of the devices. The degradation leads to a reduction in the extraction and collection efficiency of photogenerated carriers, as evidenced by the decrease in the open circuit voltage (Voc), the parameter most affected by degradation. Results give insight for the optimization of InGaN/GaN-based solar cells structure, which can be used to improve performance and reliability.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"167 ","pages":"Article 115633"},"PeriodicalIF":1.6,"publicationDate":"2025-02-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143508955","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A vertical diode-triggered silicon-controlled rectifier with adjustable holding voltage for ESD protection

IF 1.6 4区工程技术

Microelectronics Reliability Pub Date : 2025-02-27 DOI: 10.1016/j.microrel.2025.115631

Zhihua Zhu , Gongtang Yu , Shanglin Yang , Lei Xu , Zhaonian Yang , Tao Wang , Feibo Du , Dimitar Nikolov , Juin Jei Liou , Yanshan Tian , Xinwei Zhang , Boris Dobrichkov , Vladimir Garistov

{"title":"A vertical diode-triggered silicon-controlled rectifier with adjustable holding voltage for ESD protection","authors":"Zhihua Zhu , Gongtang Yu , Shanglin Yang , Lei Xu , Zhaonian Yang , Tao Wang , Feibo Du , Dimitar Nikolov , Juin Jei Liou , Yanshan Tian , Xinwei Zhang , Boris Dobrichkov , Vladimir Garistov","doi":"10.1016/j.microrel.2025.115631","DOIUrl":"10.1016/j.microrel.2025.115631","url":null,"abstract":"<div><div>This paper presents a vertical diode-triggered silicon-controlled rectifier (VDTSCR) device with adjustable holding voltage, fabricated using 180 nm CMOS technology for 3.3 V and 5 V I/O interface applications. The conventional heavily doped P and N stripes in the SCR well are reconfigured into P and N block regions, which are then connected to separate electrodes to form diodes. These embedded diodes effectively reduce the SCR's trigger voltage. The holding voltage is further improved by cascading multiple identical cells. The ESD characteristics of the proposed VDTSCR and the DTSCR were evaluated using Transmission Line Pulse (TLP) and Very Fast TLP (VFTLP). The proposed VDTSCR structure demonstrates a significant increase in holding voltage, with a 31 % reduction in turn-on time in transient waveforms compared to the DTSCR. Additionally, this paper investigates the quasi-static characteristics of the VDTSCR with various parameter configurations, achieving a figure of merit of 41.6 mA/μm.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"167 ","pages":"Article 115631"},"PeriodicalIF":1.6,"publicationDate":"2025-02-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143508956","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0