减轻通行字线诱导行锤击失效机制的相对独立性研究

IF 1.9 4区 工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC
Shanyong Chen, Hanqing Luo, Liping Liang
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引用次数: 0

摘要

本文基于三维TCAD仿真研究了不同n型掺杂情况下的排锤击(RH)失效。我们提出了一种称为去电极结构(DS)的模拟结构。通过比较正常结构和DS结构中存储节点(SN)电容电压的变化,分别得到了电子迁移(EM)和电容串扰(CC)引起的电荷变化趋势。仿真结果表明,在不同的失效模式下,导致RH失效的机制表现出不同的贡献。传递字线(pass word line, PWL)导致单失效的主要机制是传递字线(CC),而EM和传递字线(CC)共同促成了传递字线(PWL)导致的零失效。根据电荷计算结果,我们发现随着位线结深度DBL的增加,EM不断增强,而CC被抑制。因此,我们通过改善PWL功函数(WF)和注入氟(F)来调整DRAM单元的物理环境。这种调整使得CC对RH失效的抑制大于EM的增强。该优化方案提高了DBL增加对RH失效抑制的限制,对RH失效抑制研究具有重要意义。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Research on the relative independence of failure mechanisms for mitigating passing word line induced row hammering
In this article, we investigate the Row Hammering (RH) failure with different n-type doping profiles based on 3D TCAD simulation. We propose a simulation structure called de-electrode structure (DS). By comparing the storage node (SN) capacitance voltage variations in the normal structure and the DS, we obtain the trend of charge change induced by electron migration (EM) and capacitive crosstalk (CC) respectively. The simulation result reveals that the mechanisms responsible for RH failure exhibit distinct contributions across different failure modes. CC is the main mechanism of the one-failure induced by passing word line (PWL), while EM and CC synergistically contribute to the zero-failure induced by PWL. According to the charge calculation results, we find that as the bit line (BL) junction depth DBL increases, EM is continuously enhanced, while CC is suppressed. Therefore, we adjust the physical environment of DRAM cell through the PWL work function (WF) improvement and fluorine (F) implantation. This adjustment makes CC the suppression of is greater than the enhancement of EM. This optimization scheme improves the limitation of DBL increase for RH failure suppression, which has important significance for RH failure suppression research.
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来源期刊
Microelectronics Reliability
Microelectronics Reliability 工程技术-工程:电子与电气
CiteScore
3.30
自引率
12.50%
发文量
342
审稿时长
68 days
期刊介绍: Microelectronics Reliability, is dedicated to disseminating the latest research results and related information on the reliability of microelectronic devices, circuits and systems, from materials, process and manufacturing, to design, testing and operation. The coverage of the journal includes the following topics: measurement, understanding and analysis; evaluation and prediction; modelling and simulation; methodologies and mitigation. Papers which combine reliability with other important areas of microelectronics engineering, such as design, fabrication, integration, testing, and field operation will also be welcome, and practical papers reporting case studies in the field and specific application domains are particularly encouraged. Most accepted papers will be published as Research Papers, describing significant advances and completed work. Papers reviewing important developing topics of general interest may be accepted for publication as Review Papers. Urgent communications of a more preliminary nature and short reports on completed practical work of current interest may be considered for publication as Research Notes. All contributions are subject to peer review by leading experts in the field.
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