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Effect of stress interruption on TDDB lifetime during constant voltage stressing in metal-ferroelectric-insulator-semiconductor ferroelectric devices
IF 1.6 4区 工程技术
Microelectronics Reliability Pub Date : 2025-02-01 DOI: 10.1016/j.microrel.2024.115584
Tiang Teck Tan , Tian-Li Wu , Hsien-Yang Liu , Cheng-Yu Yu , Kalya Shubhakar , Nagarajan Raghavan , Kin Leong Pey
{"title":"Effect of stress interruption on TDDB lifetime during constant voltage stressing in metal-ferroelectric-insulator-semiconductor ferroelectric devices","authors":"Tiang Teck Tan ,&nbsp;Tian-Li Wu ,&nbsp;Hsien-Yang Liu ,&nbsp;Cheng-Yu Yu ,&nbsp;Kalya Shubhakar ,&nbsp;Nagarajan Raghavan ,&nbsp;Kin Leong Pey","doi":"10.1016/j.microrel.2024.115584","DOIUrl":"10.1016/j.microrel.2024.115584","url":null,"abstract":"<div><div>TDDB lifetime is an important reliability metric for ferroelectric devices, which is dependent on the complex interplay between a multitude of factors. Mechanisms such as oxygen vacancy generation, charge trapping and detrapping are relevant in the degradation physics of hafnia-based ferroelectric devices. A large difference in Time-to-Failure in Metal – Ferroelectric – Insulator - Semiconductor (MFIS) devices in response to Interrupted and Uninterrupted Constant Voltage Stressing was found, which underscores the significance of stress interruption on the degradation physics occurring in the device. However, the effect of interruptions during stressing in MFIS devices is relatively unexplored. This work aims to pave the way for the development of stressing schemes for the evaluation of ferroelectric devices with closer adherence to practical operating conditions.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"165 ","pages":"Article 115584"},"PeriodicalIF":1.6,"publicationDate":"2025-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143352104","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Total ionizing dose radiation effect of HfO2/TaOx-based resistive random-access memories
IF 1.6 4区 工程技术
Microelectronics Reliability Pub Date : 2025-02-01 DOI: 10.1016/j.microrel.2025.115590
Xinpei Duan , Yahui Qing , Yong Wang , Ruohao Hong , Jiawei Chen , Pei Yang , Yanan Yin , Xinjie Zhou , Xingqiang Liu , Bei Jiang
{"title":"Total ionizing dose radiation effect of HfO2/TaOx-based resistive random-access memories","authors":"Xinpei Duan ,&nbsp;Yahui Qing ,&nbsp;Yong Wang ,&nbsp;Ruohao Hong ,&nbsp;Jiawei Chen ,&nbsp;Pei Yang ,&nbsp;Yanan Yin ,&nbsp;Xinjie Zhou ,&nbsp;Xingqiang Liu ,&nbsp;Bei Jiang","doi":"10.1016/j.microrel.2025.115590","DOIUrl":"10.1016/j.microrel.2025.115590","url":null,"abstract":"<div><div>Resistive random-access memory (RRAM) demonstrates excellent radiation tolerance characteristics, making it highly suitable for a wide range of applications in harsh radiation environments such as aerospace. This work specifically investigates the impact of total ionizing dose (TID) radiation on the electrical performance of HfO<sub>2</sub>/TaO<sub>x</sub>-based RRAM. Through an analysis of the electrical characteristics before and after irradiation, we thoroughly examine the evolution of performance and the mechanism of radiation damage in two types of HfO<sub>2</sub>/TaO<sub>x</sub>-based RRAMs under high-energy gamma rays. The findings from this study will serve as a valuable reference for the development and radiation hardening of HfO<sub>2</sub>/TaO<sub>x</sub>-based RRAMs designed to operate effectively in harsh radiation environments.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"165 ","pages":"Article 115590"},"PeriodicalIF":1.6,"publicationDate":"2025-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143352102","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Interface trap charge modeling of surrounding gate-engineered tubular channel junctionless MOSFET exploring temperature induced variations
IF 1.6 4区 工程技术
Microelectronics Reliability Pub Date : 2025-02-01 DOI: 10.1016/j.microrel.2024.115583
Pritha Banerjee, Jayoti Das
{"title":"Interface trap charge modeling of surrounding gate-engineered tubular channel junctionless MOSFET exploring temperature induced variations","authors":"Pritha Banerjee,&nbsp;Jayoti Das","doi":"10.1016/j.microrel.2024.115583","DOIUrl":"10.1016/j.microrel.2024.115583","url":null,"abstract":"<div><div>Current research presents the mathematical modeling highlighting the interface trap charge degraded characteristics of Surrounding Gate-Engineered Tubular Channel Junctionless MOSFET including temperature variation. Salient device features such as drain current, Ion/Ioff ratio, transconductance, off-current temperature sensitivity, threshold voltage have been explored to investigate the temperature influences comparing the damaged and undamaged configuration of the device. Extent of subthreshold swing variations under thermal influence has been analyzed. Impact of channel length scaling, channel thickness and oxide-thickness variation on device features have also been reported in this research. Analytical outputs have been corroborated using simulation outputs from Silvaco Atlas 3D.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"165 ","pages":"Article 115583"},"PeriodicalIF":1.6,"publicationDate":"2025-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143352105","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Conductance variability in RRAM and its implications at the neural network level
IF 1.6 4区 工程技术
Microelectronics Reliability Pub Date : 2025-02-01 DOI: 10.1016/j.microrel.2025.115594
H. Aziza , M. Fieback , S. Hamdioui , H. Xun , M. Taouil
{"title":"Conductance variability in RRAM and its implications at the neural network level","authors":"H. Aziza ,&nbsp;M. Fieback ,&nbsp;S. Hamdioui ,&nbsp;H. Xun ,&nbsp;M. Taouil","doi":"10.1016/j.microrel.2025.115594","DOIUrl":"10.1016/j.microrel.2025.115594","url":null,"abstract":"<div><div>While Resistive RRAM (RRAM) provides appealing features for artificial neural networks (NN) such as low power operation and high density, its conductance variation can pose significant challenges for synaptic weight storage. This paper reports an experimental evaluation of the conductance variations of manufactured RRAMs memory cells at the memory array level. Variability is evaluated with respect to the RRAM low resistance state (LRS) and high resistance state (HRS) conductance ratio. This ratio is selected as the parameter of interest as it guarantees the proper operation of the RRAM: the larger the ratio, the more reliable and robust the RRAM cell is in storing and retrieving data. The measurement results show that conductance ratio is significantly influenced by variability. Using these findings, the performance of an artificial neural network that uses individual RRAM cells for synaptic weight storage is evaluated in relation to conductance variability. It is shown that RRAM variability can heavily affect the network behavior, resulting in a substantial decrease in the classification accuracy during inference.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"166 ","pages":"Article 115594"},"PeriodicalIF":1.6,"publicationDate":"2025-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143208162","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A non-volatile and radiation-hardened SRAM based on fourteen transistors and two perpendicular anisotropy magnetic tunnel junctions
IF 1.6 4区 工程技术
Microelectronics Reliability Pub Date : 2025-01-31 DOI: 10.1016/j.microrel.2025.115603
Pei Yang, Kaixuan Li, Yunjiao Zhu, Xinpei Duan, Yanan Yin, Jiawei Chen, Tao Wang, Xinjie Zhou
{"title":"A non-volatile and radiation-hardened SRAM based on fourteen transistors and two perpendicular anisotropy magnetic tunnel junctions","authors":"Pei Yang,&nbsp;Kaixuan Li,&nbsp;Yunjiao Zhu,&nbsp;Xinpei Duan,&nbsp;Yanan Yin,&nbsp;Jiawei Chen,&nbsp;Tao Wang,&nbsp;Xinjie Zhou","doi":"10.1016/j.microrel.2025.115603","DOIUrl":"10.1016/j.microrel.2025.115603","url":null,"abstract":"<div><div>As a high-speed memory, the static random-access memory (SRAM) has been widely used and well investigated. However, with the advanced manufactory technology develops and the critical dimension of transistor scales rapidly, SRAM has confronted with many challenges, such as the high-power consumption and the robustness issue, which impede the application of SRAM in advanced electronic devices. Here, by integrating two perpendicular anisotropy magnetic tunnel junctions (p-MTJs) to the conventional SRAM and reinforcing the CMOS circuits, a non-volatile and radiation hardened SRAM (NVRH-SRAM) design based on 14 transistors (14T) and 2 p-MTJs has been implemented. This MTJ-based NVRH-SRAM is primarily single event upset (SEU) tolerant and is a promising candidate for low power circuits, aerospace devices, and other high-speed memory applications.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"166 ","pages":"Article 115603"},"PeriodicalIF":1.6,"publicationDate":"2025-01-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143208161","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Investigation of ESD protection devices for SiC-based monolithic integrated circuits
IF 1.6 4区 工程技术
Microelectronics Reliability Pub Date : 2025-01-31 DOI: 10.1016/j.microrel.2025.115611
Chao-Yang Ke, Ming-Dou Ker
{"title":"Investigation of ESD protection devices for SiC-based monolithic integrated circuits","authors":"Chao-Yang Ke,&nbsp;Ming-Dou Ker","doi":"10.1016/j.microrel.2025.115611","DOIUrl":"10.1016/j.microrel.2025.115611","url":null,"abstract":"<div><div>ESD characterization of on-chip ESD protection devices, including the gate-grounded NMOS (GGNMOS), the gate-VDD PMOS (GDPMOS), the N+/PW diode, and the P+/NW diode was investigated. With respect to GGNMOS and GDPMOS, ESD robustness was unrelated to the number of fingers under the breakdown mode. On the contrary, under the forward mode, ESD robustness can be effectively enhanced by increasing the number of fingers. Similar results were observed on the N+/PW and the P+/NW diodes. Under the breakdown mode, ESD robustness was not related to the junction perimeter of the diode. Under the forward mode, ESD robustness can be effectively enhanced by increasing the junction perimeter. By comparing the figure of merit (FoM) among these four devices, the FoM of diode is higher than that of MOS-based ESD devices. Moreover, the concept of whole-chip ESD protection with power-rail ESD clamp circuit was recommended to guarantee the sufficient ESD robustness of SiC-based integrated circuits.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"166 ","pages":"Article 115611"},"PeriodicalIF":1.6,"publicationDate":"2025-01-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143207513","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
The research on the infrared time-sequence imaging inspection method for internal defects of 3D TSV packaging
IF 1.6 4区 工程技术
Microelectronics Reliability Pub Date : 2025-01-29 DOI: 10.1016/j.microrel.2025.115608
Nie Lei , Zhang Ming , Yu Chenrui , Yan Han , Liao Guanglan , Liu Mengran
{"title":"The research on the infrared time-sequence imaging inspection method for internal defects of 3D TSV packaging","authors":"Nie Lei ,&nbsp;Zhang Ming ,&nbsp;Yu Chenrui ,&nbsp;Yan Han ,&nbsp;Liao Guanglan ,&nbsp;Liu Mengran","doi":"10.1016/j.microrel.2025.115608","DOIUrl":"10.1016/j.microrel.2025.115608","url":null,"abstract":"<div><div>In the realm of microelectronic packaging, 3D packaging employing Through-Silicon Vias (TSVs) is prevalent in high-end electronic devices due to its enhanced integration density and reduced power consumption. Nevertheless, the intricate fabrication processes of TSVs frequently engender internal defects, critically impairing the reliability and performance stability of the packaging. Conventional inspection methodologies are generally ineffectual in detecting subsurface defects. To address this, we propose an inspection method for internal defects in 3D TSV packaging utilizing infrared time-sequence imaging. This method involves dynamic laser excitation to induce defect-specific thermal anomalies, which are subsequently captured via infrared time-sequence imagery. These images are processed using a deep learning C3D network to facilitate defect recognition and classification. An experimental setup was developed with an infrared laser mounted on a 2D translation stage to dynamically excite the test samples while an infrared thermograph records the time-sequenced thermal images. The experimental results validate the efficacy of this approach, achieving detection accuracies of 98.1 % for identical defect types at the same location and 97.8 % for various defect locations.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"166 ","pages":"Article 115608"},"PeriodicalIF":1.6,"publicationDate":"2025-01-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143207509","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Effects of solder solidification temperature on residual stress distribution and failure location in BGA solder joints
IF 1.6 4区 工程技术
Microelectronics Reliability Pub Date : 2025-01-29 DOI: 10.1016/j.microrel.2025.115609
Mohammed Abdel Razzaq , Michael Meilunas , Xian A. Cao , Jim Wilcox , Abdallah Ramini
{"title":"Effects of solder solidification temperature on residual stress distribution and failure location in BGA solder joints","authors":"Mohammed Abdel Razzaq ,&nbsp;Michael Meilunas ,&nbsp;Xian A. Cao ,&nbsp;Jim Wilcox ,&nbsp;Abdallah Ramini","doi":"10.1016/j.microrel.2025.115609","DOIUrl":"10.1016/j.microrel.2025.115609","url":null,"abstract":"<div><div>This study investigates how the solder solidification temperature affects residual stress distribution and failure locations in BGA solder joints, aiming to provide insights that enhance solder alloy selection and reflow process optimization. Through experimental thermal cycling tests on BGA208 assemblies using SAC305 (∼220 °C) and Sn37Pb (∼180 °C) solder alloys, subjected to temperatures ranging from −40 °C to 125 °C, we found that SAC305 assemblies predominantly failed at corner joints due to warpage stresses. In contrast, Sn37Pb assemblies failed at second-row joints under the die edge due to shear stresses. These results were validated by Finite element analysis (FEA) simulations, which showed that higher solidification temperatures, as in SAC305, resulted in higher residual stresses and maximum stresses at corner joints, whereas lower solidification temperatures, as in Sn37Pb, shifted stress concentrations to non-corner joints. These results underscore the critical role of the solidification temperature in determining failure locations and provide valuable insights for improving the reliability of BGA components in electronic applications.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"166 ","pages":"Article 115609"},"PeriodicalIF":1.6,"publicationDate":"2025-01-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143207511","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Gate sizing and buffer insertion for circuit aging and thermal resilience enhancement
IF 1.6 4区 工程技术
Microelectronics Reliability Pub Date : 2025-01-29 DOI: 10.1016/j.microrel.2025.115604
Ling Xiong, Wangyong Chen, Mingyue Zheng, Linlin Cai
{"title":"Gate sizing and buffer insertion for circuit aging and thermal resilience enhancement","authors":"Ling Xiong,&nbsp;Wangyong Chen,&nbsp;Mingyue Zheng,&nbsp;Linlin Cai","doi":"10.1016/j.microrel.2025.115604","DOIUrl":"10.1016/j.microrel.2025.115604","url":null,"abstract":"<div><div>The ongoing drive to shrink transistor sizes has yielded substantial benefits but has also amplified reliability concerns, especially concerning aging effects. Moreover, the wide range of applications demands distinct reliability standards, with temperature playing a pivotal role. To tackle these challenges, this paper presents three approaches based on critical gate sorting: buffer insertion, gate sizing, and a hybrid technique that combines both. Simulations using the ASAP 7 nm standard cell library reveal that these methods significantly improve circuit robustness against aging and temperature fluctuations. Among these methods, buffer insertion achieves performance optimization at the expense of significant area overhead, while gate sizing provides a more balanced trade-off between performance and resource usage. Compared to gate sizing, the hybrid technique proves to be the most effective solution in scenarios with stringent power consumption requirements.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"166 ","pages":"Article 115604"},"PeriodicalIF":1.6,"publicationDate":"2025-01-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143207512","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Investigation of electromagnetic force effect in IGBT modules
IF 1.6 4区 工程技术
Microelectronics Reliability Pub Date : 2025-01-29 DOI: 10.1016/j.microrel.2025.115606
Jiahao Wang, Cong Chen, Libing Bai, Yuxin Luo, Chaoyue Song, Yuhua Cheng
{"title":"Investigation of electromagnetic force effect in IGBT modules","authors":"Jiahao Wang,&nbsp;Cong Chen,&nbsp;Libing Bai,&nbsp;Yuxin Luo,&nbsp;Chaoyue Song,&nbsp;Yuhua Cheng","doi":"10.1016/j.microrel.2025.115606","DOIUrl":"10.1016/j.microrel.2025.115606","url":null,"abstract":"<div><div>As a kind of widely employed power semiconductor devices, insulated gate bipolar transistor (IGBT) modules are often confronted with strong load current from tens to hundreds of amperes. Thus, the electrical-magnetic-mechanical coupling characteristics in IGBT modules deserve priority attention for reliability evaluation. Herein, an in-depth investigation of electromagnetic force effect in IGBT modules is implemented from both theoretical and experimental approaches. Utilizing uniquely designed excitation strategy of single frequency sinusoidal alternating load current superimposed by direct current bias, the exclusive frequency-doubled vibration signal induced by electromagnetic force effect is successfully observed on the IGBT bare die with the aid of laser interferometric vibrometer, providing direct and confident evidence for the existence of electromagnetic force effect in IGBT modules. This work is bound to bring new insights to fundamental exploration of electrical-mechanical coupling induced reliability issues in power electronic devices.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"166 ","pages":"Article 115606"},"PeriodicalIF":1.6,"publicationDate":"2025-01-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143207510","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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