Microelectronics Reliability最新文献

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Study on the optimization of bending-vibration coupling stress of QFN solder joints based on Taguchi orthogonal experimental design and Harris Hawks Optimization algorithm 基于田口正交试验设计和Harris Hawks优化算法的QFN焊点弯曲-振动耦合应力优化研究
IF 1.6 4区 工程技术
Microelectronics Reliability Pub Date : 2025-07-05 DOI: 10.1016/j.microrel.2025.115839
Jisheng Wei, Chunyue Huang, Chao Gao, Gui Wang
{"title":"Study on the optimization of bending-vibration coupling stress of QFN solder joints based on Taguchi orthogonal experimental design and Harris Hawks Optimization algorithm","authors":"Jisheng Wei,&nbsp;Chunyue Huang,&nbsp;Chao Gao,&nbsp;Gui Wang","doi":"10.1016/j.microrel.2025.115839","DOIUrl":"10.1016/j.microrel.2025.115839","url":null,"abstract":"<div><div>A three-dimensional finite element analysis model of QFN (Quad Flat No-Lead package) solder joints was established, and stress–strain analysis under bending-vibration coupling conditions was conducted. A validation experiment for measuring the bending-vibration coupled strain of QFN solder joints was designed and successfully carried out. Based on Taguchi Orthogonal Experimental Design and analysis of variance and range, the effects of pad length, pad width, and solder joint standoff height on the bending-vibration coupled stress and strain of solder joints were investigated. Taking the bending-vibration coupled stress as the optimization objective, the structural parameters of the solder joints were optimized using the Harris Hawks Optimization (HHO) algorithm. The results show that the solder joint standoff height has the greatest influence on the bending-vibration coupled stress. The optimal parameter combination for the QFN solder joints is: pad length of 0.62 mm, pad width of 0.21 mm, and solder joint standoff height of 0.09 mm. The optimized parameter combination reduced the bending-vibration coupled stress by 34.8%. These findings provide theoretical guidance for reducing the bending-vibration coupled stress in QFN solder joints.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"173 ","pages":"Article 115839"},"PeriodicalIF":1.6,"publicationDate":"2025-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144563138","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Reliability of discrete SiC MOSFETs under severe temperature-shock and power cycling tests 离散SiC mosfet在剧烈温度冲击和功率循环试验下的可靠性
IF 1.6 4区 工程技术
Microelectronics Reliability Pub Date : 2025-07-03 DOI: 10.1016/j.microrel.2025.115844
Patrick Heimler, Sandro Richter, Josef Lutz, Thomas Basler
{"title":"Reliability of discrete SiC MOSFETs under severe temperature-shock and power cycling tests","authors":"Patrick Heimler,&nbsp;Sandro Richter,&nbsp;Josef Lutz,&nbsp;Thomas Basler","doi":"10.1016/j.microrel.2025.115844","DOIUrl":"10.1016/j.microrel.2025.115844","url":null,"abstract":"<div><div>In this work, discrete SiC MOSFETs with an R<sub>DS(ON)</sub> of 60 mΩ and a blocking capability of 1200 V have been subjected to extreme thermal shock tests and additional power cycling tests to study interactions between the failure modes in both tests. In this context, an R<sub>th,jc</sub> (thermal resistance: junction - case) increase of up to 55 %, confirmed by found solder degradation in cross sections, can be noted after the thermal shock test. However, bond wire degradation remains the dominant cause of failure after the power cycling test, even if the solder layer of the test specimens was previously damaged.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"173 ","pages":"Article 115844"},"PeriodicalIF":1.6,"publicationDate":"2025-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144534338","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Impact of near interface defects on NO annealed SiC MOSFET mobility 近界面缺陷对NO退火SiC MOSFET迁移率的影响
IF 1.6 4区 工程技术
Microelectronics Reliability Pub Date : 2025-07-02 DOI: 10.1016/j.microrel.2025.115841
Yu-Xin Wen , Bing-Yue Tsui , Kin P. Cheung
{"title":"Impact of near interface defects on NO annealed SiC MOSFET mobility","authors":"Yu-Xin Wen ,&nbsp;Bing-Yue Tsui ,&nbsp;Kin P. Cheung","doi":"10.1016/j.microrel.2025.115841","DOIUrl":"10.1016/j.microrel.2025.115841","url":null,"abstract":"<div><div>The cause of low mobility in SiC MOSFETs, particularly after post-oxidation nitric oxide (NO) annealing, remains a critical question in wide-bandgap device reliability. Previous reports have attributed poor mobility to the formation of fast near-interface traps (NITs) introduced by NO annealing. In this study, we utilize fast drain current–gate voltage (<em>I</em><sub><em>d</em></sub>-<em>V</em><sub><em>g</em></sub>) measurements, which has a simple interpretation, to directly probe these NITs to check if these assertions are true. Our fast drain current–gate voltage measurements show that on the time scales of 10 ns to 500 ns, filling near interface traps leads to &lt;10 % reduction in the mobility, implying that such traps cannot explain the poor mobility in SiC MOSFETs. This finding challenges the attribution of poor mobility solely to fast NITs and point toward alternative mechanisms, such as above band edge states.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"173 ","pages":"Article 115841"},"PeriodicalIF":1.6,"publicationDate":"2025-07-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144523120","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Stress–strain analysis and optimization of BGA stacked solder joints under extreme temperatures based on orthogonal design and grey relational analysis 基于正交设计和灰色关联分析的极端温度下BGA堆叠焊点应力应变分析与优化
IF 1.6 4区 工程技术
Microelectronics Reliability Pub Date : 2025-07-02 DOI: 10.1016/j.microrel.2025.115846
Yonglin Chen, Chunyue Huang, Chao Gao, Gui Wang
{"title":"Stress–strain analysis and optimization of BGA stacked solder joints under extreme temperatures based on orthogonal design and grey relational analysis","authors":"Yonglin Chen,&nbsp;Chunyue Huang,&nbsp;Chao Gao,&nbsp;Gui Wang","doi":"10.1016/j.microrel.2025.115846","DOIUrl":"10.1016/j.microrel.2025.115846","url":null,"abstract":"<div><div>A finite element analysis (FEA) model of Ball Grid Array (BGA) stacked solder joints was established, and the stress–strain behavior under extreme temperature conditions was simulated. Using an orthogonal experimental design method, the influence and significance ranking of four structural parameters—solder ball diameter, solder joint height, pad diameter, and joint pitch—on the stress and strain of the solder joints were analyzed. Grey relational analysis was employed to determine the correlation between these structural parameters and solder joint stress. A multi-objective optimization of stress and strain was then performed based on orthogonal experimental results to identify the optimal combination of structural parameters. The results show that, with a confidence level of 95 %, solder ball diameter and joint height have a significant effect on stress and strain in BGA stacked solder joints. The influence ranking of the four structural parameters on solder joint stress is as follows: solder ball diameter &gt; solder joint height &gt; joint pitch &gt; pad diameter. The optimal combination of parameters is: solder ball diameter of 0.60 mm, solder joint height of 0.52 mm, pad diameter of 0.50 mm, and joint pitch of 0.96 mm. This configuration reduces the maximum stress and strain under extreme temperature conditions by 14.2 %, thereby effectively improving the reliability of BGA stacked solder joints under extreme temperature conditions.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"173 ","pages":"Article 115846"},"PeriodicalIF":1.6,"publicationDate":"2025-07-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144523026","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Significance of phase formation in multicomponent lead-free solder alloys 多组分无铅钎料合金相形成的意义
IF 1.6 4区 工程技术
Microelectronics Reliability Pub Date : 2025-07-01 DOI: 10.1016/j.microrel.2025.115843
Farzaneh Zareipour , Hamed Shahmir , Ali Mirzavand-Borujeni , Alireza Derakhshandeh , Farsad Forghani
{"title":"Significance of phase formation in multicomponent lead-free solder alloys","authors":"Farzaneh Zareipour ,&nbsp;Hamed Shahmir ,&nbsp;Ali Mirzavand-Borujeni ,&nbsp;Alireza Derakhshandeh ,&nbsp;Farsad Forghani","doi":"10.1016/j.microrel.2025.115843","DOIUrl":"10.1016/j.microrel.2025.115843","url":null,"abstract":"<div><div>This research focuses on the significance of alloying elements and phase formation in the microstructure, mechanical properties, wettability and interfacial behaviour of multicomponent lead-free solder alloys to address important parameters for achieving high-performance solder joints in electronic packages. For this purpose, five lead-free solder alloys including Sn-0.7Cu, Sn-1.0Ag-0.5Cu, Sn-3.0Ag-0.5Cu, Sn-3.0Ag-0.5Cu-0.8Bi and Sn-4.0Ag-0.5Cu-4.1In (all in wt%) were fabricated and studied in this investigation. Experiments and thermodynamic calculations confirm the formation of different phases including Cu<sub>6</sub>Sn<sub>5</sub> in binary Sn<img>Cu, Cu<sub>6</sub>Sn<sub>5</sub> and Ag<sub>3</sub>Sn in ternary Sn-Ag-Cu and, Cu<sub>6</sub>(Sn,In)<sub>5</sub> and Ag<sub>3</sub>(Sn,In) in quaternary Sn-Ag-Cu-In solder alloys. Nevertheless, the β-Sn matrix can dissolve a small amount of Bi, which effectively produces finer eutectic phases of β-Sn and Cu<sub>6</sub>Sn<sub>5</sub> during solidification in the quaternary Sn-Ag-Cu-Bi solder alloy. In fact, there is a favorable bonding tendency between Sn<img>Ag, Sn<img>Cu and Sn<img>In, which promotes the formation of intermetallic compounds. In addition, the significant difference between the atomic radius of Sn elements with Cu and In (&gt;10 %) promotes the formation of secondary phases. The slightly positive mixing enthalpy of Sn and Bi, together with their similarity in atomic size, allows for slight solubility of Bi in Sn. The addition of 0.8 wt% Bi and 4.1 wt% In reduced the melting points and solidification range of the lead-free solder alloy and led to improved wettability. The quaternary solder alloys exhibit superior thermal and mechanical properties compared to conventional alloys, making them potential replacements for lead-containing solder alloys.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"173 ","pages":"Article 115843"},"PeriodicalIF":1.6,"publicationDate":"2025-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144518057","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Geometry-driven physics-of-failure lifetime analysis of aluminum bonding wires in discrete SiC power electronics 离散碳化硅电力电子中铝键合线的几何驱动失效寿命分析
IF 1.6 4区 工程技术
Microelectronics Reliability Pub Date : 2025-06-30 DOI: 10.1016/j.microrel.2025.115835
Borja Kilian , Youssef Maniar , Jonas Gleichauf , Olaf Wittler , Martin Schneider-Ramelow
{"title":"Geometry-driven physics-of-failure lifetime analysis of aluminum bonding wires in discrete SiC power electronics","authors":"Borja Kilian ,&nbsp;Youssef Maniar ,&nbsp;Jonas Gleichauf ,&nbsp;Olaf Wittler ,&nbsp;Martin Schneider-Ramelow","doi":"10.1016/j.microrel.2025.115835","DOIUrl":"10.1016/j.microrel.2025.115835","url":null,"abstract":"<div><div>Bonding wire reliability remains one of the major challenges in power electronics as device miniaturization progresses and demands on performance increase. Physics-of-failure models are commonly formulated to determine the lifetime of wire bond interconnects, relying on damage metrics derived from finite element models often based on modeling assumptions, especially when dealing with molded packages. These conventional approaches neglect the effect of the actual geometries of the bond foot and encapsulation cavity.</div><div>In this work, the reliability of encapsulated Al bonding wires in SiC power devices is investigated using active power cycling tests. The bonding wire material is characterized across various strain rates and temperatures, while its geometry is measured using high-resolution white light interferometry. Finite element models are solved using a two-stage simulation approach: First, an upstream wire bonding simulation is performed to obtain realistic bond foot and mold cavity geometries, and then the active power cycling tests are simulated. A Coffin–Manson lifetime model is calibrated using damage quantities derived from the simulation results, and the effect of various bond foot geometries on lifetime is analyzed. The results demonstrate that the modeled bond foot geometry can significantly influence lifetime predictions. By addressing the limitations of conventional simplified models, the presented approach offers a more accurate prediction.</div><div>The aim of the presented methodology is to accelerate the design of ECUs for automotive applications with the help of robust simulation models, reducing the experimental effort and ultimately the time to market.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"172 ","pages":"Article 115835"},"PeriodicalIF":1.6,"publicationDate":"2025-06-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144514206","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Reliability analysis of dopingless vertical nanowire TFET with interface trap charges for ring-oscillator circuit implementation 带界面阱电荷的无掺杂垂直纳米线TFET环振电路可靠性分析
IF 1.6 4区 工程技术
Microelectronics Reliability Pub Date : 2025-06-28 DOI: 10.1016/j.microrel.2025.115840
Anjana Bhardwaj , Amit Das , Ranjeeta Yadav , Pradeep Kumar
{"title":"Reliability analysis of dopingless vertical nanowire TFET with interface trap charges for ring-oscillator circuit implementation","authors":"Anjana Bhardwaj ,&nbsp;Amit Das ,&nbsp;Ranjeeta Yadav ,&nbsp;Pradeep Kumar","doi":"10.1016/j.microrel.2025.115840","DOIUrl":"10.1016/j.microrel.2025.115840","url":null,"abstract":"<div><div>This manuscript is presenting a dopingless (DL) vertical nanowire tunnel FET (V-NW-TFET) with gate all around (GAA) structure with the effect of Interface-Trap-Charges (ITCs). By implanting the metal with the required work function, the charge plasma method induces the required doping in the source and drain. The ITCs' effects on the dopingless device are comprehensively discussed along with the linearity performance parameters such as higher order harmonic distortions (HDs), intermodulation distortions (IMDs), and interception points. According to the different findings, negative ITCs degrade the device performance, whereas positive ITCs can aid in enhancing device attributes and characteristics. With the positive trap charges, the ratio of ON to OFF current goes up along with the enhancement of the ON-state current by about 50 %. Positive ITCs enhance the ITC-DL-V-NW-TFET's driving capabilities, making it a better choice for analog applications. The proposed device has shown increased cut-off frequency and reduced threshold voltage for higher positive ITCs. A wide temperature ranges from 200 K to 400 K is applied to check the reliability of the device, but only a minor change in different device characteristics can be observed. In this paper, for the first time the dopingless vertical nanowire tunnel FET with ITC effect is utilized for ring-oscillator circuit implementation, where three inverters are used to design the three-stage ring-oscillator. The proposed ring-oscillator circuit exhibits reduced delay and power consumption as compared to MOSFET based ring-oscillator circuit.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"172 ","pages":"Article 115840"},"PeriodicalIF":1.6,"publicationDate":"2025-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144501548","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Local thermal runaway during surge events in power rectifiers 电源整流器浪涌事件时的局部热失控
IF 1.6 4区 工程技术
Microelectronics Reliability Pub Date : 2025-06-26 DOI: 10.1016/j.microrel.2025.115833
Ole Jonathan Bergmann , Tim Boettcher , Hoan Vu , Hoc Khiem Trieu
{"title":"Local thermal runaway during surge events in power rectifiers","authors":"Ole Jonathan Bergmann ,&nbsp;Tim Boettcher ,&nbsp;Hoan Vu ,&nbsp;Hoc Khiem Trieu","doi":"10.1016/j.microrel.2025.115833","DOIUrl":"10.1016/j.microrel.2025.115833","url":null,"abstract":"<div><div>This article presents a model for device failure of power rectifiers during surge current events. A possible failure cause of those devices are exceeding surge currents. Therefore, the detailed understanding of the device behaviour under surge conditions and the related failure mode is essential to achieve and maintain a stable device performance. In this work, the IFSM failure mode is investigated in terms of experimental determination of the failure temperature for rectifier diodes. The failure locations of the stressed devices are determined on the chip and partial-electro-thermal simulations are run to model the temperature distribution. The simulated temperature distribution matches with the analysed failure locations. The failure can be explained by local thermal runaway for PN as well as Schottky diodes, if hole injection from the PN junction or the Schottky contact is taken into account.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"172 ","pages":"Article 115833"},"PeriodicalIF":1.6,"publicationDate":"2025-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144491272","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Microstructure and properties of Cu/In-Sn-xZn-yAg/Cu solder joints after thermal aging Cu/In-Sn-xZn-yAg/Cu焊点热时效后的组织与性能
IF 1.6 4区 工程技术
Microelectronics Reliability Pub Date : 2025-06-25 DOI: 10.1016/j.microrel.2025.115837
Yucong He , Yang Zheng , Zheng Liu , Xixuan Jiao , Yaocheng Zhang , Li Yang , Xiuting Zhao
{"title":"Microstructure and properties of Cu/In-Sn-xZn-yAg/Cu solder joints after thermal aging","authors":"Yucong He ,&nbsp;Yang Zheng ,&nbsp;Zheng Liu ,&nbsp;Xixuan Jiao ,&nbsp;Yaocheng Zhang ,&nbsp;Li Yang ,&nbsp;Xiuting Zhao","doi":"10.1016/j.microrel.2025.115837","DOIUrl":"10.1016/j.microrel.2025.115837","url":null,"abstract":"<div><div>Cu/In-Sn-5Zn/Cu and Cu/In-Sn-2.5Zn-50Ag/Cu solder joints were prepared by Transient Liquid Phase (TLP) bonding. The solder joints were aged at 50 °C, 75 °C and 100 °C for 1008 h to study the microstructural evolution and changes in shear strength. After long-term thermal aging, cracks appeared in the in-situ reaction zone of Cu/In-Sn-5Zn/Cu solder joints. The addition of Ag nanoparticles led to the generation of Ag₃In phases in Cu/In-Sn-2.5Zn-50Ag/Cu solder joints, which were dispersed in the in-situ reaction zone and effectively hindered crack propagation. After long-term thermal aging, potential crack propagation regions formed by the aggregation of Kirkendall voids appeared in the interfacial reaction zone of Cu/In-Sn-5Zn/Cu solder joints. The addition of Ag particles inhibited the overgrowth of Cu₃(In,Sn) intermetallic compound (IMC) and the formation of Kirkendall voids, enabling the solder joints to maintain a dense interfacial structure and high shear strength after long-term thermal aging. The cracks in the in-situ reaction zone and Kirkendall voids in the interfacial reaction zone of Cu/In-Sn-5Zn/Cu solder joints affected the shear strength and fracture location. The fracture locations of Cu/In-Sn-2.5Zn-50Ag/Cu solder joints were relatively stable and all occurred in the in-situ reaction zone.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"172 ","pages":"Article 115837"},"PeriodicalIF":1.6,"publicationDate":"2025-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144469976","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Crack propagation in ultrasonic-bonded copper wires investigated by power cycling and accelerated mechanical fatigue interconnection test methods 采用功率循环和加速机械疲劳互连试验方法研究了超声结合铜线的裂纹扩展
IF 1.6 4区 工程技术
Microelectronics Reliability Pub Date : 2025-06-24 DOI: 10.1016/j.microrel.2025.115836
L. Karanja , P. Pichon , M. Legros
{"title":"Crack propagation in ultrasonic-bonded copper wires investigated by power cycling and accelerated mechanical fatigue interconnection test methods","authors":"L. Karanja ,&nbsp;P. Pichon ,&nbsp;M. Legros","doi":"10.1016/j.microrel.2025.115836","DOIUrl":"10.1016/j.microrel.2025.115836","url":null,"abstract":"<div><div>The introduction of robust interconnects such as copper wire and metallization, and silver sinter die technology have significantly increased the reliability of insulated gate bipolar transistor (IGBT) power devices. As a result, the reliability testing duration has increased, and it is particularly challenging to investigate the degradation mechanism in the wire bonds. To shorten the testing time, and to test the failure modes in the wire bonds an isothermal accelerated mechanical fatigue interconnect test has been introduced. This mechanical fatigue test attempts to mimic thermomechanical stresses caused during power cycling. In this work, an in-depth microstructure investigation of the failure mode in copper top interconnects after power cycling and after mechanical fatigue testing was carried out. It was found that the crack propagation path for both tests was similar. The mechanical test is seen to alter the microstructure of the wire bond, particularly around the wire and metallization interface.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"172 ","pages":"Article 115836"},"PeriodicalIF":1.6,"publicationDate":"2025-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144365434","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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