Microelectronics Reliability最新文献

{"title":"Enhanced thermal management of SiGe HBT integrated circuits using the Peltier effect and DBC metal tracks","authors":"Abdelaaziz Boulgheb","doi":"10.1016/j.microrel.2025.115896","DOIUrl":"10.1016/j.microrel.2025.115896","url":null,"abstract":"<div><div>Effective thermal management remains a major challenge for SiGe heterojunction bipolar transistor (HBT) integrated circuits, particularly in BiCMOS9MW 0.13 μm technology. This study proposes a novel two-stage heat dissipation strategy that combines active thermoelectric cooling with passive DBC-based conduction an approach not previously explored in this context to address this issue. First, the Peltier effect is leveraged in combination with conventional plastic packaging to regulate circuit thermal performance. Second, Direct Bonded Copper (DBC) metal tracks are implemented to establish an efficient thermal pathway between the internal circuit and external heat sinks. Experimental results indicate that standard plastic packaging alone results in excessive heating (T_max = 467 K). The incorporation of the Peltier effect significantly reduces the peak temperature to 380 K, while the addition of DBC tracks further enhances cooling, lowering the temperature to 340 K. Unlike traditional cooling solutions that rely solely on packaging or external heatsinks, our method enables localized, controllable heat extraction directly at the chip level, ensuring better thermal regulation and improved electrical performance. This dual approach not only mitigates self-heating but also leads to notable improvements in DC and RF performance. Specifically, the maximum current gain (β_max) increases from 1913 to 2183, and the transit frequency (<em>f</em>_<em>t</em>) rises from 265 GHz to 285.6 GHz. These findings underscore the effectiveness of the combined Peltier-based cooling and DBC thermal management in enabling next-generation high-frequency applications.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"174 ","pages":"Article 115896"},"PeriodicalIF":1.9,"publicationDate":"2025-08-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144896074","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Effect of Ni nanoparticles reinforcement on wettability, microstructure and mechanical properties of SAC387 lead-free solder alloy","authors":"Hisham J. Muhammed ,&nbsp;K. Narayan Prabhu","doi":"10.1016/j.microrel.2025.115895","DOIUrl":"10.1016/j.microrel.2025.115895","url":null,"abstract":"<div><div>The study investigates the influence of nickel (Ni) nanoparticles on the wettability, microstructure, and mechanical properties of Sn-3.8Ag-0.7Cu (SAC387) lead-free solder alloy. Nanocomposite solders containing 0.3 wt% and 0.5 wt% Ni were prepared and reflowed at temperatures of 230 °C, 250 °C, and 270 °C to evaluate their performance on copper substrates with a surface roughness (Ra) of 0.01 ± 0.002 μm. Wettability improved with increasing reflow temperature; however, the addition of Ni nanoparticles had minimal direct impact on spreading behavior. Microstructural analysis revealed enhanced formation of interfacial intermetallic compounds (IMCs), particularly (Cu,Ni)₆Sn₅ which contributed to improved joint stability. The optimal mechanical performance was observed at 250 °C with 0.3 wt% Ni addition, yielding a 51.14 % increase in shear strength compared to the unreinforced solder. Microhardness also improved significantly by 43.7 % at the IMC layer and 18.3 % in the solder bulk. Weibull analysis further confirmed higher joint performance with Ni nanoparticle incorporation. These findings highlight the potential of addition of Ni nanoparticles in improving the performance of SAC387 solder joints in electronic packaging.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"174 ","pages":"Article 115895"},"PeriodicalIF":1.9,"publicationDate":"2025-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144890772","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A fuzzy-arithmetic-based reliability assessment model for digital circuits (FARAM-DC)","authors":"Somayeh Bahramnejad","doi":"10.1016/j.microrel.2025.115893","DOIUrl":"10.1016/j.microrel.2025.115893","url":null,"abstract":"<div><div>Reliability is crucial in digital circuits and SRAM-based FPGAs, the programmable devices used for circuit implementation. Hence, this article proposes an assessment method for failure probability and reliability of digital circuits in SRAM-based FPGAs. There are various studies on the reliability of FPGA circuits; most of them consider the effect of cosmic radiation on the circuit's reliability, which results in Single-Event Upsets (SEUs). The impact of hardware and software failures is rarely considered. The proposed method in this research considers the effects of different factors on the circuit's failure, including hardware failures resulting from dust, wetness, temperature, and jitter, software failures resulting from programming errors, and SEUs resulting from radiation. Since precise estimation of the factors’ effects on the circuit's failure is difficult, qualitative values are used to explain the impacts and estimate the failure probability and reliability using Fuzzy arithmetic. The results present a precise evaluation of the reliability of digital circuits, which, ignoring each effective factor, leads to an overestimation of reliability.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"174 ","pages":"Article 115893"},"PeriodicalIF":1.9,"publicationDate":"2025-08-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144878852","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A strategy for monitoring the influence of moisture on the Cu/low-k interconnect patterning and reliability in the manufacturing process","authors":"Ki Dong Yang ,&nbsp;Jae Hyeong Lee ,&nbsp;Eunji Hwang ,&nbsp;Byoungwook Woo ,&nbsp;Nam Hyun Lee ,&nbsp;Hoomi Choi ,&nbsp;Eunyoung Han ,&nbsp;Young Jeong Kim","doi":"10.1016/j.microrel.2025.115894","DOIUrl":"10.1016/j.microrel.2025.115894","url":null,"abstract":"<div><div>This study investigates the impact of moisture on the patterning process and reliability of Cu/low-k interconnects. Using optical emission spectroscopy (OES), we observed differences in the end-point detection (EPD) signal depending on the storage conditions, with an increase in CF-related peaks. This was found to be due to the faster etch rate of the low-k dielectric film caused by the increased surface -OH, as confirmed by X-ray photoelectron spectroscopy (XPS). In addition, the influence of moisture-uptake on the electrical performance of the Cu/low-k interconnects were observed through I-V curves, and this trend was found to be predictable and interpretable according to the EPD value. These findings demonstrate a methodology for predicting reliability characteristics using a large amount of fab data, highlighting the importance of optimizing the fabrication process and storage environment for low-k dielectric materials to ensure their reliability in advanced semiconductor devices.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"174 ","pages":"Article 115894"},"PeriodicalIF":1.9,"publicationDate":"2025-08-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144878853","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Fault diagnosis of SiC MOSFETs based on time-frequency analysis of acoustic emission signals","authors":"Yongjiang Lei ,&nbsp;Wenbiao Zhang ,&nbsp;Menglin Liu ,&nbsp;Lei Chi","doi":"10.1016/j.microrel.2025.115897","DOIUrl":"10.1016/j.microrel.2025.115897","url":null,"abstract":"<div><div>In the high-frequency switching applications of SiC MOSFETs, traditional techniques are faced with challenges in achieving non-invasiveness measurement, real-time evaluation, and online monitoring. An effective condition monitoring approach for SiC MOSFETs is crucial to ensure the safe operation of power electronic systems. A solution based on the acoustic emission (AE) detection technique is proposed in this paper. Through the utilization of time-frequency analysis, the time-frequency characteristics of the AE signals generated by SiC MOSFETs under double-pulse test conditions have been explored. Three multi-dimensional characteristic parameters, namely time-frequency variance, energy entropy, and time-frequency center of gravity, have been used, which can achieve quantitative characterization of the dynamic behavior from SiC MOSFETs. By systematically comparing the time-frequency characteristics of AE signals from SiC MOSFETs under normal operating conditions and typical faulty states, the experimental results indicate that the combination of the three characteristics can be employed to identify different types of faults.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"174 ","pages":"Article 115897"},"PeriodicalIF":1.9,"publicationDate":"2025-08-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144887379","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Sputtering impact on warpage in FOWLP","authors":"Xu Zhang,&nbsp;Qizhe Li,&nbsp;Zhimo Zhang,&nbsp;Chenhui Xia,&nbsp;Gang Wang","doi":"10.1016/j.microrel.2025.115891","DOIUrl":"10.1016/j.microrel.2025.115891","url":null,"abstract":"<div><div>Fan-out wafer level packaging (FOWLP), an advanced packaging technology that can achieve high performance and miniaturisation, has become a subject of considerable research interest. As one of the important high-temperature steps in the FOWLP process, the influence of the sputtering step on the amount of wafer deformation is a key element in the study of the reliability of FOWLP. This study investigates the changes in warpage during the sputtering steps through both simulation and experimental approaches. Particularly, for the degassing chamber (Degas) that has the greatest impact on wafer warpage, the study analyzed its working principle and the mechanism of warpage formation. It is proposed that the primary causes of the warpage change in the Degas chamber are the maximum wafer temperature and the maximum temperature difference. Based on this, simulation and experimental studies were conducted on wafer temperature and warpage changes under different heat flow rate, while also considering silicon chip thickness ratio, to provide insights into more methods for mitigating wafer warpage in PVD (Physical Vapor Deposition) processes. The results of the study show that the wafer temperature is positively correlated with the heat flow rate and high wafer temperature can lead to wafer warpage greater than 5 mm, which is a great challenge to the process. In addition, the article uses simulation to verify the impact of wafer silicon chip thickness ratio on warpage, verifying the conclusion that the wafer warpage is the largest when the silicon chip thickness ratio is around 20 %–30 %.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"174 ","pages":"Article 115891"},"PeriodicalIF":1.9,"publicationDate":"2025-08-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144860960","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Multi-mode aging decoupling monitoring method for IGBT modules based on TSEPs separation strategy","authors":"Mingxing Du,&nbsp;Songwei Guo,&nbsp;Jinliang Yin","doi":"10.1016/j.microrel.2025.115892","DOIUrl":"10.1016/j.microrel.2025.115892","url":null,"abstract":"<div><div>The health condition of insulate gate bipolar transistor (IGBT) modules directly determines whether the entire power electronics system can operate stably over the long term. Currently, IGBT module health monitoring methods mainly focus on single failure modes. However, in engineering applications, IGBT modules often undergo multiple types of aging due to the combined effects of electrical, thermal, and mechanical stresses. Moreover, the high-speed switching of IGBT modules generates significant self-heating, accurate junction temperature prediction is also critically important. To address the above issues, this paper proposes a multi-mode aging decoupling monitoring method for IGBT modules based on temperature sensitive electrical parameters (TSEPs) separation strategy. By analyzing the effects of junction temperature variation, gate oxide degradation, and bond wires lift-off on pre-threshold voltage change rate d<em>V</em>_th-pre/d<em>t</em>, threshold voltage <em>V</em>_th, and auxiliary emitter voltage <em>V</em>_eE, the specificity of these parameters to junction temperature and different aging modes are obtained, achieving multi-mode aging decoupling. The experimental results show that the proposed method can effectively identify IGBT modules gate oxide degradation or bond wires lift-off while predicting the junction temperature. It is also capable of decoupling and quantifying each aging mode degrees, and exhibits a certain level of immunity to load current variations.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"174 ","pages":"Article 115892"},"PeriodicalIF":1.9,"publicationDate":"2025-08-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144861150","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Orbital validation for tin whisker suppression by conformal coating","authors":"Shinichiro Ichimaru ,&nbsp;Tsuyoshi Nakagawa ,&nbsp;Norio Nemoto ,&nbsp;Katsuaki Suganuma ,&nbsp;Hiroaki Tatsumi ,&nbsp;Hiroshi Nishikawa","doi":"10.1016/j.microrel.2025.115888","DOIUrl":"10.1016/j.microrel.2025.115888","url":null,"abstract":"<div><div>To investigate the use of lead-free tin-based parts for satellites, the effectiveness of using a conformal coating for suppressing the growth of tin whiskers in Earth orbit was validated. An exposed handrail attachment mechanism on Kibo, the outboard platform of the International Space Station, was used in the experiments in the study. Experimental samples were exposed in orbit for up to four years, and the ability of parylene and polyurethane coatings to suppress whisker growth was investigated. Numerous thin, long, and straight whiskers grew in orbit on the uncoated samples, but the whiskers did not penetrate the parylene- and polyurethane-coated samples. In addition, no whiskers were generated from tin plating under these coatings. Parylene exhibited hardness, which completely suppressed the growth of whiskers and nodules. Polyurethane, being a softer material, showed some nodules under the coating, but no whiskers were observed. Furthermore, there was no difference between the whisker suppression effect in the orbital and ground test samples for both coatings. There was also no significant degradation in the hardness or Young's modulus of the coatings. These results demonstrate that lead-free parts coated with parylene or polyurethane can be used in satellites operating in this orbit for four years. To our knowledge, this is the first study to report and clarify the effects of a conformal coating on whisker suppression in Earth orbit.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"174 ","pages":"Article 115888"},"PeriodicalIF":1.9,"publicationDate":"2025-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144829018","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Accelerated lifetime estimation and failure analysis of micromachined humidity sensors under high temperature and high humidity conditions","authors":"Krisztián Dubek ,&nbsp;Christoph Schneidhofer ,&nbsp;Nicole Dörr ,&nbsp;Harald Rojacz ,&nbsp;Bernhard Plank ,&nbsp;Ulrich Schmid","doi":"10.1016/j.microrel.2025.115885","DOIUrl":"10.1016/j.microrel.2025.115885","url":null,"abstract":"<div><div>Accelerated Life Testing (ALT) is used to detect and understand failure mechanisms, as well as to calculate and evaluate the robustness and resulting reliability of electronic components such as sensors subjected to various influencing factors in different applications. Based on the successful lab and field robustness validation of the customized Humidity Sensor in Axle Bearings (HSAB) system utilized for the condition monitoring of lubricated rail components, an ALT methodology was designed for a micromachined humidity sensor, and respective results are presented. ALT was aimed at quantifying the robustness of the selected sensor under higher-than-normal use environmental loads (temperature and humidity), with a focus on its sensor element. Thus, ALTs under constant high temperatures combined with low- and high-humidity conditions were executed until all the tested sensor elements failed. Thereafter, the resulting failures were investigated using various methods. The solder joint failure of the sensor element was determined as a central failure mode. Based on the data obtained for the time to failure of the sensor elements, a two-parameter Weibull distribution function was fitted, in agreement with comparable scientific works on solder joint failures. As the aged sensor elements themselves did not seem to be significantly influenced or even damaged by the executed ALTs, their existing functionality was proven afterwards. For this purpose, they were first resoldered and then tested using a developed step-validation test program for temperature and humidity. After a statistical evaluation of the sensor signal deviations relative to a calibrated reference sensor, the amount of still operational sensor elements was assessed. As a result, it was determined that sensor elements aged at high temperatures in a high-humidity atmosphere failed to a significantly greater extent owing to the damaging effect of water. This indicates that water significantly affected not only the solder joints of the sensor but also the sensor element itself under the investigated test conditions.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"174 ","pages":"Article 115885"},"PeriodicalIF":1.9,"publicationDate":"2025-08-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144771536","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Temperature-dependent characteristics and mechanisms in thin-barrier AlGaN/GaN MIS-HEMTs with LPCVD-SiN passivation layer","authors":"Simei Huang,&nbsp;Jiejie Zhu,&nbsp;Mengdi Li,&nbsp;Lingjie Qin,&nbsp;Huilin Li,&nbsp;Boxuan Gao,&nbsp;Qing Zhu,&nbsp;Xiaohua Ma","doi":"10.1016/j.microrel.2025.115877","DOIUrl":"10.1016/j.microrel.2025.115877","url":null,"abstract":"<div><div>This paper investigates the temperature-dependent characteristics and degradation mechanisms of thin-barrier AlGaN/GaN metal–insulator–semiconductor high electron mobility transistors with low-pressure chemical vapor deposition SiN passivation layers on silicon substrate from 223 to 463 K. The channel current degradation in large gate-length devices is primarily attributed to mobility degradation. Through temperature-dependent field-effect mobility analysis, polar optical phonon scattering mechanism dominates at high temperatures, with an extracted optical phonon energy of 92.65 meV. Besides, the mechanisms of gate leakage current were studied. At temperatures above 373 K, slight increased gate leakage after pinch-off is dominated by two-dimensional variable range hopping, with the activation energy of 0.018 to 0.013 eV. While in the reverse bias region, trap-assisted tunneling (TAT) and Poole–Frenkel (PF) emission mechanism were found to dominate. The PF mechanism prevails above 403 K with a trap activation energy of 0.64 eV, while TAT dominates below 298 K showing the trap energy of 0.215 to 0.242 eV. In the medium forward bias region, defect-assisted tunneling (DAT) is the dominant mechanism. In the high forward bias region, TAT dominates with the trap energy ranging from 0.237 to 0.265 eV.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"174 ","pages":"Article 115877"},"PeriodicalIF":1.9,"publicationDate":"2025-08-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144771537","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}