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Microelectronics Reliability最新文献

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Failure analysis and reliability assessment of gold-plated fuzz buttons in elevated temperature
IF 1.6 4区 工程技术
Microelectronics Reliability Pub Date : 2025-03-18 DOI: 10.1016/j.microrel.2025.115687
L. Zhang , S. Wang , X. Chen , J. Guo , L. Xu , S. Ling , X. Zhang
{"title":"Failure analysis and reliability assessment of gold-plated fuzz buttons in elevated temperature","authors":"L. Zhang ,&nbsp;S. Wang ,&nbsp;X. Chen ,&nbsp;J. Guo ,&nbsp;L. Xu ,&nbsp;S. Ling ,&nbsp;X. Zhang","doi":"10.1016/j.microrel.2025.115687","DOIUrl":"10.1016/j.microrel.2025.115687","url":null,"abstract":"<div><div>Gold-plated electrical contacts are widely used in electrical and electronic systems to provide high-quality and reliable connections with minimal signal distortion or power loss. Many studies have been conducted on the failure analysis of gold-coated contacts in high-temperature environments. However, fuzz buttons, as one of the typical end-face contacts, have been less studied. This paper presents an experimental method to analyze the effects of elevated environmental temperatures on the performance of gold-plated fuzz buttons. The results show that the natural length and compression force of fuzz buttons were both shortened and reduced after the elevated temperature tests. Quantitative analysis of the microstructural changes in the test samples was conducted using characterization techniques such as optical microscopy, scanning electron microscopy (SEM), and focused ion beam (FIB) technology. The findings indicate that a large number of twin structures disappeared, the size of the precipitated phases increased, and the dislocation density decreased, leading to a reduced ability of fuzz buttons to resist plastic deformation and resulting in stress relaxation. Furthermore, a nonlinear Wiener stochastic process was used to model the degradation path of the test samples, while the generalized Eyring model was employed to describe the relationship between sample lifetimes and high temperatures. Using the maximum likelihood estimation (MLE) method, the model parameters were estimated from the integral statistics of all performance degradation data, successfully predicting the reliability of the fuzz buttons.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"168 ","pages":"Article 115687"},"PeriodicalIF":1.6,"publicationDate":"2025-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143641640","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Localization enhancement in quantitative thermal lock-in analysis using spatial phase evaluation
IF 1.6 4区 工程技术
Microelectronics Reliability Pub Date : 2025-03-15 DOI: 10.1016/j.microrel.2025.115690
S. Brand , M. Koegel , C. Grosse , F. Altmann , H.T. Devarajulu , F.M. Benito , D. Goyal , M. Pacheco
{"title":"Localization enhancement in quantitative thermal lock-in analysis using spatial phase evaluation","authors":"S. Brand ,&nbsp;M. Koegel ,&nbsp;C. Grosse ,&nbsp;F. Altmann ,&nbsp;H.T. Devarajulu ,&nbsp;F.M. Benito ,&nbsp;D. Goyal ,&nbsp;M. Pacheco","doi":"10.1016/j.microrel.2025.115690","DOIUrl":"10.1016/j.microrel.2025.115690","url":null,"abstract":"<div><div>The paper discusses enhancements in quantitative thermal lock-in analysis through spatial phase evaluation for defect localization in complex microelectronic components. It addresses the challenges of increasing integration density and diverse material composition in microelectronics. The primary focus of the present work is placed on improving sensitivity and spatial resolution of lock-in thermography for detection, imaging and the quantitative localization of thermally active electrical defects in all three spatial dimensions inside a device under test (DUT) to enable precise fault isolation. The paper describes the analysis of the lateral phase distribution in the presence of a thermal hot spot for reconstructing the thermal wave at the surface of the DUT and its back-tracing to its source inside the DUT. In the practical application this processing results in a reduction of thermal spreading effects and a precise localization in the lateral and axial (depth) directions. Experimental results demonstrate substantial improvements in precision and accuracy of defect localization and additionally a quantitative depth estimation. The paper highlights the potential application of the proposed method for non-destructive defect localization in 3D-integrated microelectronic devices.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"168 ","pages":"Article 115690"},"PeriodicalIF":1.6,"publicationDate":"2025-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143627843","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Fast and high-resolution X-ray nano tomography for failure analysis in advanced packaging
IF 1.6 4区 工程技术
Microelectronics Reliability Pub Date : 2025-03-14 DOI: 10.1016/j.microrel.2025.115694
T. Dreier, D. Nilsson, J. Hållstedt
{"title":"Fast and high-resolution X-ray nano tomography for failure analysis in advanced packaging","authors":"T. Dreier,&nbsp;D. Nilsson,&nbsp;J. Hållstedt","doi":"10.1016/j.microrel.2025.115694","DOIUrl":"10.1016/j.microrel.2025.115694","url":null,"abstract":"<div><div>Advanced packaging in electronics involves integrating semiconductor devices and sensors into a unified package, often employing complex 3D structures for enhanced performance and efficiency. As electronic components become smaller and more densely packed, conventional 2D X-ray radiography is not sufficient for inspection. Here we demonstrate the use of nano-CT with a high bandwidth memory (HBM) example illustrating the potential of fast detection of sub-micron voids and cracks in micro-bumps. Using a 30 s overview scan at 2.6 μm voxel size for navigation, a region is selected for a high-resolution scan with a voxel size of 600 nm to analyse 20 μm micro-bumps in between DRAM layers. Additionally, high-resolution laminography is performed showing the differences of the 2 techniques. The results show how high-resolution nano-CT can effectively be used for fast failure analysis and R&amp;D as well as important feedback to production ramp up and yield improvements of advanced packaging technologies.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"168 ","pages":"Article 115694"},"PeriodicalIF":1.6,"publicationDate":"2025-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143620393","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Understanding improved pitting corrosion resistance under high temperature application leading to a newly developed palladium coated copper wire
IF 1.6 4区 工程技术
Microelectronics Reliability Pub Date : 2025-03-14 DOI: 10.1016/j.microrel.2025.115696
Noritoshi Araki , Motoki Eto , Shinya Azuma , Robert Klengel , Sandy Klengel , Takashi Yamada
{"title":"Understanding improved pitting corrosion resistance under high temperature application leading to a newly developed palladium coated copper wire","authors":"Noritoshi Araki ,&nbsp;Motoki Eto ,&nbsp;Shinya Azuma ,&nbsp;Robert Klengel ,&nbsp;Sandy Klengel ,&nbsp;Takashi Yamada","doi":"10.1016/j.microrel.2025.115696","DOIUrl":"10.1016/j.microrel.2025.115696","url":null,"abstract":"<div><div>As the application of palladium coated copper (PCC) wire in automotive semiconductor sector increases, its reliability under high temperature is a topic of frequent discussion ever in the industry. One of the reliability concerns for PCC wire is pitting corrosion at ball bond and wedge bond contact areas. Pitting corrosion is a unique issue for PCC wire that could become prominent at high temperature (≥175 °C) in a sulfur containing environment. To overcome this issue, we developed a new PCC wire that has exceptionally high resistance against pitting corrosion by introducing the corrosion inhibitor inside the Pd coating layer. This paper discusses the reliability performance of the new wire, including the results of high temperature storage life test at elevated temperatures (up to 250 °C) and the investigation of the improving mechanism by high resolution microstructural analysis.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"168 ","pages":"Article 115696"},"PeriodicalIF":1.6,"publicationDate":"2025-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143620392","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Current balancing of parallel-connected silicon carbide (SiC) MOSFET power devices using peak detection via PCB sensors
IF 1.6 4区 工程技术
Microelectronics Reliability Pub Date : 2025-03-14 DOI: 10.1016/j.microrel.2025.115688
Ravi Nath Tripathi , Ichiro Omura
{"title":"Current balancing of parallel-connected silicon carbide (SiC) MOSFET power devices using peak detection via PCB sensors","authors":"Ravi Nath Tripathi ,&nbsp;Ichiro Omura","doi":"10.1016/j.microrel.2025.115688","DOIUrl":"10.1016/j.microrel.2025.115688","url":null,"abstract":"<div><div>The parallelling of power semiconductor devices is essential for desired current ratings and the system is prone to the current unbalancing due to parameter variations. SiC devices with significant variable threshold voltage due to manufacturing yield and temperature distribution have a consequential possibility of dynamic current unbalancing. This paper presents the peak detection-based current balancing of parallel-connected SiC devices to minimize the turn-on and turn-off current unbalancing. PCB current sensors are used for the measurement and feedback of the signal for this peak detection-based current balancing mechanism.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"168 ","pages":"Article 115688"},"PeriodicalIF":1.6,"publicationDate":"2025-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143620394","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Optimization of the drain-side configuration in ESD-protection SCR-LDMOS for high holding-voltage applications
IF 1.6 4区 工程技术
Microelectronics Reliability Pub Date : 2025-03-13 DOI: 10.1016/j.microrel.2025.115664
L. Zunarelli , S. Rotorato , E. Gnani , S. Reggiani , R. Sankaralingam , M. Dissegna , G. Boselli
{"title":"Optimization of the drain-side configuration in ESD-protection SCR-LDMOS for high holding-voltage applications","authors":"L. Zunarelli ,&nbsp;S. Rotorato ,&nbsp;E. Gnani ,&nbsp;S. Reggiani ,&nbsp;R. Sankaralingam ,&nbsp;M. Dissegna ,&nbsp;G. Boselli","doi":"10.1016/j.microrel.2025.115664","DOIUrl":"10.1016/j.microrel.2025.115664","url":null,"abstract":"<div><div>A conventional silicon-controlled rectifier integrated into a laterally diffused MOSFET (SCR-LDMOS) is studied through 2D TCAD simulations in order to obtain the maximum holding voltage without increasing the area consumption or degrading the power-to-failure robustness. A reference device with 150V trigger voltage, 3V holding voltage and an approximate thermal breakdown at 30 mA/<span><math><mrow><mi>μ</mi><mi>m</mi></mrow></math></span> is adopted. Different configurations of the drain-side region are compared, with the best solution showing a 5x improvement on the holding condition without a significant variation on the other figures of merit.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"168 ","pages":"Article 115664"},"PeriodicalIF":1.6,"publicationDate":"2025-03-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143611533","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Toward understanding the impacts of dynamic Ron on the efficiency in GaN-based AC-DC flyback converter
IF 1.6 4区 工程技术
Microelectronics Reliability Pub Date : 2025-03-13 DOI: 10.1016/j.microrel.2025.115692
Chih-Yao Chang , Hsing-Hua Hsieh , Cheng-Tsung Ho , Tsung-Hsiu Wu , Ming-Chang Tsou , Chih-Wen Hsiung , Ming-Nan Chuang , Tian-Li Wu
{"title":"Toward understanding the impacts of dynamic Ron on the efficiency in GaN-based AC-DC flyback converter","authors":"Chih-Yao Chang ,&nbsp;Hsing-Hua Hsieh ,&nbsp;Cheng-Tsung Ho ,&nbsp;Tsung-Hsiu Wu ,&nbsp;Ming-Chang Tsou ,&nbsp;Chih-Wen Hsiung ,&nbsp;Ming-Nan Chuang ,&nbsp;Tian-Li Wu","doi":"10.1016/j.microrel.2025.115692","DOIUrl":"10.1016/j.microrel.2025.115692","url":null,"abstract":"<div><div>In this work, the dynamic R<sub>on</sub> effects on the efficiency and conduction loss in GaN-based AC-DC flyback converter was evaluated. Compared to the static on-resistance, the dynamic R<sub>on</sub> of single p-GaN gate HEMT shows a significant increase under hard switching via a double pulse test. In addition, the dynamic R<sub>on</sub> shows a further increase when the pulse time increases, indicating that the real dynamic R<sub>on</sub> in the continuous switching system may not be totally revealed by a single pulse test. On the other hand, the combo IC operated in the system indicates that the substantial increase of dynamic R<sub>on</sub> (&gt;188 % increases) in p-GaN gate HEMTs have the limited impacts on 1) the conduction loss (&lt;9 %) in p-GaN gate HEMTs and 2) the system efficiency (&gt;92 %) in GaN-based AC-DC flyback converter.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"168 ","pages":"Article 115692"},"PeriodicalIF":1.6,"publicationDate":"2025-03-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143611534","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Solder joint reliability - glass core substrate versus organic core substrate
IF 1.6 4区 工程技术
Microelectronics Reliability Pub Date : 2025-03-13 DOI: 10.1016/j.microrel.2025.115701
John H. Lau, Ning Liu, Mike Ma, Tzyy-Jang Tseng
{"title":"Solder joint reliability - glass core substrate versus organic core substrate","authors":"John H. Lau,&nbsp;Ning Liu,&nbsp;Mike Ma,&nbsp;Tzyy-Jang Tseng","doi":"10.1016/j.microrel.2025.115701","DOIUrl":"10.1016/j.microrel.2025.115701","url":null,"abstract":"<div><div>The thermal-fatigue reliability of flip chip micro solder joints on glass core build-up package substrate and C4 (controlled collapse chip connection) or BGA (ball grid array) solder joints on printed circuit board (PCB) is investigated. Emphasis is placed on the deformation of the structure and the accumulated inelastic strain at the critical locations of the micro and C4 solder joints. Some recommendations are also provided.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"168 ","pages":"Article 115701"},"PeriodicalIF":1.6,"publicationDate":"2025-03-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143611577","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Heterogeneity-induced thermal mismatch in BGA interconnects: Insights from mechanical-thermal finite element modeling
IF 1.6 4区 工程技术
Microelectronics Reliability Pub Date : 2025-03-13 DOI: 10.1016/j.microrel.2025.115703
Liu Chu , Jiajia Shi , Xu Long
{"title":"Heterogeneity-induced thermal mismatch in BGA interconnects: Insights from mechanical-thermal finite element modeling","authors":"Liu Chu ,&nbsp;Jiajia Shi ,&nbsp;Xu Long","doi":"10.1016/j.microrel.2025.115703","DOIUrl":"10.1016/j.microrel.2025.115703","url":null,"abstract":"<div><div>Thermal expansion mismatch due to the heterogeneous materials in ball grid array (BGA) interconnects of electronic packaging structures often results in localized strain concentration, leading to creep, fatigue, or potential failure. Modeling BGA solder balls independently, without considering connected and contacting components, fails to comprehensively monitor the system's state. In this study, a mechanical-thermal finite element model (FEM) comprising solder balls, a printed circuit board (PCB), chips, and underfill is systematically developed. Time-dependent nonlinear analysis is performed on Sn-Ag-Cu (SAC) solder-bumped flip chips in PCB assemblies subjected to thermal cycling. Thermal gradient contours illustrate inhomogeneous in-plane and vertical thermal diffusion within the components. The Garofalo model is employed in the FEM to simulate visco-plastic behavior. The results reveal significant thermal gradient mismatches due to the intrinsic properties of heterogeneous components, which are often overlooked in independent material studies. Additionally, the central region of the BGA exhibits more pronounced creep strain compared to edge solder balls. These findings provide valuable insights for optimizing BGA geometric design. This work also offers a comprehensive framework to quantify thermal mismatches and simulate creep behavior under thermal cycling based on FEM.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"168 ","pages":"Article 115703"},"PeriodicalIF":1.6,"publicationDate":"2025-03-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143611535","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Fast reverse engineering of chips using lasers, Focused Ion Beams, and confocal and scanning electron microscopy
IF 1.6 4区 工程技术
Microelectronics Reliability Pub Date : 2025-03-13 DOI: 10.1016/j.microrel.2025.115697
Matthew Maniscalco , Hongbin Choi , Adrian Phoulady , Alexander Blagojevic , Toni Moore , Mohammad Taghi Mohammadi Anaei , Parisa Mahyari , Nicholas May , Sina Shahbazmohamadi , Pouya Tavousi
{"title":"Fast reverse engineering of chips using lasers, Focused Ion Beams, and confocal and scanning electron microscopy","authors":"Matthew Maniscalco ,&nbsp;Hongbin Choi ,&nbsp;Adrian Phoulady ,&nbsp;Alexander Blagojevic ,&nbsp;Toni Moore ,&nbsp;Mohammad Taghi Mohammadi Anaei ,&nbsp;Parisa Mahyari ,&nbsp;Nicholas May ,&nbsp;Sina Shahbazmohamadi ,&nbsp;Pouya Tavousi","doi":"10.1016/j.microrel.2025.115697","DOIUrl":"10.1016/j.microrel.2025.115697","url":null,"abstract":"<div><div>This study presents novel methodologies for the reverse engineering and failure analysis of semiconductor devices, focusing on overcoming the limitations of traditional Focused Ion Beam (FIB) techniques. Central to our approach are two innovative methods: high-precision volumetric imaging via 3D reconstruction from laser-delayered surface profiles and a hybrid delayering technique combining ultrashort pulsed laser removal with FIB polishing. These methods address the challenges of slow delayering processes and uneven layer exposure by enabling faster material removal, minimizing thermal damage, and ensuring precise surface preparation for imaging. The effectiveness of these approaches is demonstrated through detailed imaging of embedded chip circuitry in two advanced technology chips. Our findings highlight significant advancements in the speed, accuracy, and efficiency of semiconductor device analysis, promising to streamline reverse engineering efforts and enhance failure analysis processes.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"168 ","pages":"Article 115697"},"PeriodicalIF":1.6,"publicationDate":"2025-03-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143611536","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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