Microelectronics Reliability最新文献

{"title":"Separate investigation of performance degradation for the Si and GaN parts in cascode GaN devices under repetitive short circuits","authors":"Zhebie Lu,&nbsp;Francesco Iannuzzo","doi":"10.1016/j.microrel.2025.115779","DOIUrl":"10.1016/j.microrel.2025.115779","url":null,"abstract":"<div><div>In this paper, the performance degradation under repetitive short circuits was investigated for the Si and GaN separately in cascode GaN devices. Self-sustained oscillation is a main obstacle in deeper studying the short-circuit characteristics of cascode GaN devices, in many cases, the device is damaged by the self-sustained oscillations rather than the thermal/electrical stress of short circuits. To avoid the self-sustained oscillations during short circuits, a modified short-circuit test platform is proposed to conduct the short-circuit test safely. To characterize the static performance of the Si and GaN parts separately in a fair way, a new decapsulation method without affecting the die performance is proposed on a commercial cascode GaN device. Considering the trap effect on GaN devices, a fair test procedure is designed to avoid the influence brought by the fluctuation of the GaN threshold voltage. In the end, the performance degradation is analysed after going through repetitive short-circuit tests under 100 V/10 μs. The results show that the on-state resistance increases after short circuits, the Si part is responsible for 38 % in it and the GaN part is responsible for 62 % in it. The threshold of Si part is not changed while the threshold of GaN part increases.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"172 ","pages":"Article 115779"},"PeriodicalIF":1.6,"publicationDate":"2025-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144262152","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Mechanical and electrical testing of encapsulated stretchable substrate interconnect models for emerging flexible electronic systems","authors":"Gulafsha Bhatti ,&nbsp;Yash Agrawal ,&nbsp;Vinay Palaparthy ,&nbsp;Rohit Sharma ,&nbsp;Mekala Girish Kumar","doi":"10.1016/j.microrel.2025.115824","DOIUrl":"10.1016/j.microrel.2025.115824","url":null,"abstract":"<div><div>Flexible electronics (FE) technology incorporates stretchable interconnects to enable devices those conform to irregular surfaces, bend and stretch without sacrificing functionality. These interconnects are crafted of specialized materials and designs those can withstand mechanical deformations with facilitating seamless integration of electronic components. Serpentine structures are widely used in flexible and stretchable interconnect. However, understanding their mechanical properties under different design parameters is crucial for optimal performance and reliability. In this work, through finite element analysis (FEA), the mechanical behaviour of serpentine interconnect structures with varying geometric parameters, along with and without encapsulation layer is novely investigated. The silver (Ag) material is used as conductor, while both substrate and encapsulation layers are formed using polydimethylsiloxane (PDMS). Also, the effect of mesh analysis is performed on the stretching of the considered interconnect models. Further, the Coffin-Mansons law based fatigue cycle test and the conductivity of the interconnect are analyzed. Finally, the simulation results are validated with experimental results. This research provides essential insightful observations on the interplay between design parameters, mechanical and electrical behaviour for the development of robust stretchable interconnect geometry in flexible electronic systems.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"172 ","pages":"Article 115824"},"PeriodicalIF":1.6,"publicationDate":"2025-06-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144262153","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Gate oxide lifetime modeling of vertical SiC-MOS under accelerated reverse bias (ARB)","authors":"Ayan K. Biswas,&nbsp;Daniel J. Lichtenwalner,&nbsp;Brett Hull,&nbsp;Donald A. Gajewski","doi":"10.1016/j.microrel.2025.115825","DOIUrl":"10.1016/j.microrel.2025.115825","url":null,"abstract":"<div><div>Robustness under reverse bias is a pivotal reliability metric for MOS based SiC power devices. Accelerated reverse bias (ARB) stressing, typically involving multiple V_DS stress values beyond the rated drain bias but below the avalanche voltage, is deemed optimal for assessing the device lifetime in the blocking mode. However, generating adequate failure statistics within a feasible timeframe during ARB tests can be arduous, particularly for devices engineered to undergo avalanche breakdown at lower drain voltages than those necessary to induce gate oxide wear-out failures within a reasonable time. This paper presents an innovative, streamlined alternative modeling approach, where qualification-like high temperature reverse bias (HTRB) or ARB test at a singular stress voltage for a suitable stress duration can be utilized to predict gate oxide lifetimes under blocking conditions, obviating the need for any prolonged testing.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"172 ","pages":"Article 115825"},"PeriodicalIF":1.6,"publicationDate":"2025-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144241417","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Machine learning-based surrogate models for finned heatsink thermal modeling","authors":"Z. Wang,&nbsp;Y. Zhang,&nbsp;H. Wang","doi":"10.1016/j.microrel.2025.115775","DOIUrl":"10.1016/j.microrel.2025.115775","url":null,"abstract":"<div><div>With the continuous increase in power density in modern power converter, there is a growing focus on thermal system design, as its performance is a key factor influencing power density and determining the reliability of power converter. As the main heat dissipation component in the power conversion field, the heatsink plays a significant role in improving the reliability of power converters. However, it is difficult to forecast the accurate thermal performance of the device in field use. Thus, the purpose of this work is to present and propose a methodology for heatsink modeling that are based on high-performance computing and machine learning. The developed ML-based surrogate models can predict the thermal performances of the heatsink without a complicated analytical model.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"172 ","pages":"Article 115775"},"PeriodicalIF":1.6,"publicationDate":"2025-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144221675","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Interconnect electromigration modeling based on chemical mechanical polishing process variation","authors":"Yali Wang,&nbsp;Lan Chen,&nbsp;Zhaohui Qin,&nbsp;Renjie Lu,&nbsp;Rong Chen","doi":"10.1016/j.microrel.2025.115809","DOIUrl":"10.1016/j.microrel.2025.115809","url":null,"abstract":"<div><div>The interconnect electromigration (EM) analysis technology based on process variation is innovatively proposed in this study. The defect morphology in the interconnect is accurately described for the dishing defect characterization of the interconnect, and the interconnect based on technology computer aided design (TCAD) model under the influence of flattening process like chemical mechanical polishing (CMP) variation is established. For different interconnect structures and defect types, accurate simulation analysis of temperature, current density and electromigration phenomena in complex process variation environments is realized, which provides theoretical support and analysis methods for improving the reliability and performance optimization of interconnects. Moreover, the void growth model and resistance switching model of interconnect electromigration considering process variation are proposed, and the mean time to failure (MTTF) model of interconnect electromigration is established to improve the accuracy of electromigration failure time and reliability model.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"172 ","pages":"Article 115809"},"PeriodicalIF":1.6,"publicationDate":"2025-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144221673","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Remaining useful life prediction of DC contactor based on LSTM","authors":"Yu Wang ,&nbsp;Yong Xie ,&nbsp;Huimin Liang ,&nbsp;Hangyu Ma","doi":"10.1016/j.microrel.2025.115815","DOIUrl":"10.1016/j.microrel.2025.115815","url":null,"abstract":"<div><div>As a crucial electronic component in DC systems, predicting the Remaining Useful Life (RUL) of DC contactors can significantly enhance the operational reliability of the systems they are part of. Current methods for RUL prediction, which are based on single data points or traditional machine learning, face issues such as the selection of features that are inconvenient to monitor, high application costs, and low accuracy. In response, this paper proposes a method for predicting the RUL of DC contactors using Long Short-Term Memory (LSTM) neural networks. A specific DC contactor is examined as a case study to demonstrate the feasibility of applying this method. The advantage of the proposed method lies in its requirement for only the collection of current signals throughout the full lifecycle of the DC contactor to predict its RUL, resulting in low application costs. Compared to RUL prediction methods based on traditional Back Propagation Neural Networks (BPNN), this method achieves higher accuracy. Moreover, by considering key structural parameters that affect the lifespan of DC contactors, the method provides guidance for contactor design and exhibits better generalization capabilities in the predictive model.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"172 ","pages":"Article 115815"},"PeriodicalIF":1.6,"publicationDate":"2025-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144194684","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Single-particle irradiation effect and anti-irradiation optimization of a heterogeneous dielectric vertical TFET with dual material gate","authors":"Haiwu Xie ,&nbsp;Fujin Yu","doi":"10.1016/j.microrel.2025.115816","DOIUrl":"10.1016/j.microrel.2025.115816","url":null,"abstract":"<div><div>In this paper, the single-particle irradiation effect of a dual material gate heterogeneous dielectric vertical TFET (DMG-HD-VTFET) is investigated. During the irradiation, single-particle having a certain energy value generates electron-hole pairs along the incident path, which results in transient current that can disrupt the device's logic state when the quantity of these pairs becomes sufficiently large. In simulation of single-particle irradiation effect and anti-irradiation optimization, the energy carried by single-particle is represented by the linear energy transfer (LET) value. The typical value of LET is 10 MeV·cm²/mg, which is equivalent to 0.25 pC/μm along incident path. In our simulation, we first investigate the influence of single-particle with different LET energy, then the influence of incident angle variation on single-particle effect is simulated. Further, the influence of incident completion time, incident position and drain bias voltage on single-particle effect is explored. Based on these findings, anti-irradiation optimization for DMG-HD-VTFET is performed, where the dielectric and length of tunneling gate is compromised to enhance the reliability.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"171 ","pages":"Article 115816"},"PeriodicalIF":1.6,"publicationDate":"2025-05-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144178171","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Fatigue damage of automotive LEDs: Experimental approach and thermomechanical model","authors":"Khalil Maarouf ,&nbsp;Christine Roucoules ,&nbsp;Kouadio Joseph Akrou ,&nbsp;Sergio Sao-Joao ,&nbsp;Helmut Klöcker","doi":"10.1016/j.microrel.2025.115799","DOIUrl":"10.1016/j.microrel.2025.115799","url":null,"abstract":"<div><div>The automotive lighting industry continues to experience significant growth as it embraces new trends focused on higher performance and smarter functionalities.</div><div>Any new products in automotive must undergo severe accelerated tests in order to ensure its reliability under the various conditions that it may be confronted with during its lifetime.</div><div>Due to the coefficient of thermal expansion mismatch between the LED package and the PCB substrate, the solder joint fatigue failure was revealed to be one of the major failure modes during accelerated thermal cycling.</div><div>The present work focuses on analyzing three LEDs (2-pads, 3-pads and 4-pads) configurations subject to thermal cycling test. First, the damage in the solder joints during tests is observed with dye penetration at different stages of cycling. During the tests, monitoring of the variation of ΔV_F was made to follow the performance evolution of LED as a function of cycles. The dye penetration observations were analyzed to follow the evolution of the damage. On the 3 configurations of LEDs (2-pads, 3-pads and 4-pads) a model predicting the damage as function of the ΔV_F was defined and used to establish a damage law.</div><div>The second part is focusing on a thermomechanical modeling of the strains on the solder SAC305 joint occurring during thermal cycles for the 3 configurations of LEDs mounted on the type of IMS PCB.</div><div>Finally, a fatigue analysis is addressed based on the 3 configurations of LEDs on the time to failure in the thermal cycle test. A comparison between three configurations is made and a correlation with test results is performed to evaluate the accuracy of the prediction.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"171 ","pages":"Article 115799"},"PeriodicalIF":1.6,"publicationDate":"2025-05-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144178046","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Vibration characteristics and lead stress optimization for printed circuit board with PQFP under random loads","authors":"Bin Hu,&nbsp;Yunyun Sun,&nbsp;Shijing Wu","doi":"10.1016/j.microrel.2025.115817","DOIUrl":"10.1016/j.microrel.2025.115817","url":null,"abstract":"<div><div>Random vibration loads are one of the important causes of electronic device failure, and it is necessary to conduct vibration reliability analysis on the circuit boards and their leads that are prone to failure. In this paper, a finite element model of the printed circuit board (PCB) with plastic quad flat package (PQFP) is established, to investigate the reliability design of the PCB under random vibration load. The modal analysis of the circuit board is conducted using the digital image correlation (DIC) technology combined with the force hammer method, which is a non-contact measurement method, to verify the validity of the simulation model and avoid the additional mass caused by contact measurement. Based on the verified model, the optimal parameter configuration of PCB thickness (H1), package thickness (H2), lead width (w), thickness (t), length (l) and foot angle (θ) is obtained by using Taguchi orthogonal method. After the collaborative optimization of the structural parameters of the PCBA, the maximum equivalent stress value of the leads decreased by 33.54 %. Based on the response surface method, a nonlinear mapping relationship between the lead stress and the component placement was established with the offset in the X and Y directions as variables. The response surface results show that the lead stress varies non-monotonically with the component offset, and there exists an optimal placement of the component with the minimum lead stress. Moreover, the maximum stress value of the component leads is highly sensitive to the combined effect of the X and Y offset. The optimal offset from the center position reduces the lead stress by 72 %. In addition, the circuit boards before and after optimization are compared under different random vibration environments, the results show that the lead stress of the optimized circuit board is 48 % smaller than that of the unoptimized circuit board, verifying the effectiveness of the optimization design. The simultaneous optimization provides a systematic framework for early-stage design optimization, reducing development costs and improving reliability.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"171 ","pages":"Article 115817"},"PeriodicalIF":1.6,"publicationDate":"2025-05-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144185142","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Reduced-order model for solder balls – Potential of projection-based approaches for representing viscoplastic behavior","authors":"Mike Feuchter ,&nbsp;Hanna Baumgartl ,&nbsp;Martin Hanke ,&nbsp;Bernhard Wunderle ,&nbsp;Sven Rzepka","doi":"10.1016/j.microrel.2025.115796","DOIUrl":"10.1016/j.microrel.2025.115796","url":null,"abstract":"<div><div>The increasing complexity of automotive and industrial electronic control units makes traditional finite element analysis impractical for comprehensive design optimization, particularly when addressing thermomechanical reliability. To tackle this issue, a novel approach is introduced that dramatically reduces computational effort while preserving accuracy. The key innovation lies in utilizing a modular system of reduced-order models, which provides a more efficient way to simulate and optimize complex systems. This paper presents projection-based techniques specifically designed to effectively capture the nonlinear material behavior of solder balls, a critical component in electronic assemblies. Employing the Discrete Empirical Interpolation Method enables the representation of all solder balls within an assembly using a single, generalized reduced-order model that captures the highly nonlinear, viscoplastic behavior. This approach reduces the number of elements, leading to significantly faster simulations. Despite the reduction in computational effort, the accuracy of the simulations is maintained, ensuring reliable predictions of the thermomechanical behavior of the solder balls under different loadings. The paper demonstrates the advantages of this method, showing that it can be applied to assemblies with multiple solder balls, offering substantial reductions in the number of elements without compromising accuracy. The results indicate that the proposed approach has great potential for the design process for electronic control units, allowing for more efficient thermomechanical design optimization. Further research will focus on extending the method to handle larger models and investigating its performance for more complex applications.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"171 ","pages":"Article 115796"},"PeriodicalIF":1.6,"publicationDate":"2025-05-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144185147","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}