Microelectronics Reliability最新文献

{"title":"Microstructure and properties of Cu/In-Sn-xZn-yAg/Cu solder joints after thermal aging","authors":"Yucong He ,&nbsp;Yang Zheng ,&nbsp;Zheng Liu ,&nbsp;Xixuan Jiao ,&nbsp;Yaocheng Zhang ,&nbsp;Li Yang ,&nbsp;Xiuting Zhao","doi":"10.1016/j.microrel.2025.115837","DOIUrl":"10.1016/j.microrel.2025.115837","url":null,"abstract":"<div><div>Cu/In-Sn-5Zn/Cu and Cu/In-Sn-2.5Zn-50Ag/Cu solder joints were prepared by Transient Liquid Phase (TLP) bonding. The solder joints were aged at 50 °C, 75 °C and 100 °C for 1008 h to study the microstructural evolution and changes in shear strength. After long-term thermal aging, cracks appeared in the in-situ reaction zone of Cu/In-Sn-5Zn/Cu solder joints. The addition of Ag nanoparticles led to the generation of Ag₃In phases in Cu/In-Sn-2.5Zn-50Ag/Cu solder joints, which were dispersed in the in-situ reaction zone and effectively hindered crack propagation. After long-term thermal aging, potential crack propagation regions formed by the aggregation of Kirkendall voids appeared in the interfacial reaction zone of Cu/In-Sn-5Zn/Cu solder joints. The addition of Ag particles inhibited the overgrowth of Cu₃(In,Sn) intermetallic compound (IMC) and the formation of Kirkendall voids, enabling the solder joints to maintain a dense interfacial structure and high shear strength after long-term thermal aging. The cracks in the in-situ reaction zone and Kirkendall voids in the interfacial reaction zone of Cu/In-Sn-5Zn/Cu solder joints affected the shear strength and fracture location. The fracture locations of Cu/In-Sn-2.5Zn-50Ag/Cu solder joints were relatively stable and all occurred in the in-situ reaction zone.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"172 ","pages":"Article 115837"},"PeriodicalIF":1.6,"publicationDate":"2025-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144469976","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Crack propagation in ultrasonic-bonded copper wires investigated by power cycling and accelerated mechanical fatigue interconnection test methods","authors":"L. Karanja ,&nbsp;P. Pichon ,&nbsp;M. Legros","doi":"10.1016/j.microrel.2025.115836","DOIUrl":"10.1016/j.microrel.2025.115836","url":null,"abstract":"<div><div>The introduction of robust interconnects such as copper wire and metallization, and silver sinter die technology have significantly increased the reliability of insulated gate bipolar transistor (IGBT) power devices. As a result, the reliability testing duration has increased, and it is particularly challenging to investigate the degradation mechanism in the wire bonds. To shorten the testing time, and to test the failure modes in the wire bonds an isothermal accelerated mechanical fatigue interconnect test has been introduced. This mechanical fatigue test attempts to mimic thermomechanical stresses caused during power cycling. In this work, an in-depth microstructure investigation of the failure mode in copper top interconnects after power cycling and after mechanical fatigue testing was carried out. It was found that the crack propagation path for both tests was similar. The mechanical test is seen to alter the microstructure of the wire bond, particularly around the wire and metallization interface.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"172 ","pages":"Article 115836"},"PeriodicalIF":1.6,"publicationDate":"2025-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144365434","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Thermo-mechanical analysis on 10 kV SiC-MOSFETs to improve the reliability of solder layers","authors":"Masaki Takahashi ,&nbsp;Zhongchao Sun ,&nbsp;Akihiko Watanabe ,&nbsp;Ichiro Omura ,&nbsp;Stig Munk-Nielsen ,&nbsp;Asger Bjørn Jørgensen","doi":"10.1016/j.microrel.2025.115826","DOIUrl":"10.1016/j.microrel.2025.115826","url":null,"abstract":"<div><div>The study clarifies the thermo-mechanical characteristics of 10 kV SiC-MOSFET power modules to optimize die structures to improve their solder layer reliability The 10 kV SiC-MOSFET die is 8.1 mm square in size with 500 <span><math><mrow><mi>μ</mi><mi>m</mi></mrow></math></span> thickness. As a reliability evaluation, a power cycle test (PCT) at a temperature swing 100 <span><math><msup><mrow></mrow><mrow><mi>o</mi></mrow></msup></math></span>C was performed on 10 kV and 3.3 kV SiC-MOSFETs, which differ in die size, thickness, and die edge width. Both samples failed in the solder layer under the die. A number of cycles to failure <span><math><msub><mrow><mi>N</mi></mrow><mrow><mi>f</mi></mrow></msub></math></span> of 3.3 kV, which has a shorter edge, was 30% compared to 10 kV. This <span><math><msub><mrow><mi>N</mi></mrow><mrow><mi>f</mi></mrow></msub></math></span> difference matched the calculated <span><math><msub><mrow><mi>N</mi></mrow><mrow><mi>f</mi></mrow></msub></math></span> based on plastic strain changes per cycle <span><math><mrow><mi>Δ</mi><msub><mrow><mi>ɛ</mi></mrow><mrow><mi>p</mi><mi>l</mi></mrow></msub></mrow></math></span> from 3D simulations. 3D simulations with various models indicate that the larger edge of SiC-MOSFETs, such as 10 kV, have higher solder lifetimes because the large temperature distribution of the die makes smaller solder temperature swings <span><math><mrow><mi>Δ</mi><msub><mrow><mi>T</mi></mrow><mrow><mi>s</mi><mi>o</mi><mi>l</mi></mrow></msub></mrow></math></span>. As an investigation of the influence of 10 kV SiC-MOSFET die structures, reducing the die thickness with the rectangular die shape was improved <span><math><msub><mrow><mi>N</mi></mrow><mrow><mi>f</mi></mrow></msub></math></span> by up to 3.5 times by halving <span><math><mrow><mi>Δ</mi><msub><mrow><mi>ɛ</mi></mrow><mrow><mi>p</mi><mi>l</mi></mrow></msub></mrow></math></span>. These results contribute to achieving an efficient digital design through thermo-mechanical simulations.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"172 ","pages":"Article 115826"},"PeriodicalIF":1.6,"publicationDate":"2025-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144365433","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Condition monitoring for detection of humidity-induced failures in control electronics of power converters","authors":"F. Sehr,&nbsp;S. Wagner,&nbsp;A. Schulz,&nbsp;A. Vorwerk","doi":"10.1016/j.microrel.2025.115832","DOIUrl":"10.1016/j.microrel.2025.115832","url":null,"abstract":"<div><div>This paper presents a condition monitoring system for predicting failures of power converters in humid environments by detection of moisture-induced structural changes on printed circuit boards. To this end, probable failure mechanisms and possible condition monitoring concepts are presented. Subsequently, a condition monitoring concept is developed that targets electrochemical migration as a dominant failure mechanism, detecting potential failures by using comb structures as condition indicators or canaries. A suitable circuit is designed, consisting of a high voltage supply for inducing electrochemical migration and a transimpedance amplifier to measure surface insulation resistance, using a minimum number of common components and PCB space. The circuit is realized as a prototype and subjected to characterization and long-term measurements.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"172 ","pages":"Article 115832"},"PeriodicalIF":1.6,"publicationDate":"2025-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144365432","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A comparative study between the improved unified creep-plasticity model and Anand model: Experimental investigations at the material-scale and packaging structure-scale","authors":"Fan Yang ,&nbsp;Yuexing Wang ,&nbsp;Linwei Cao ,&nbsp;Xiangyu Sun ,&nbsp;Yao Yao","doi":"10.1016/j.microrel.2025.115838","DOIUrl":"10.1016/j.microrel.2025.115838","url":null,"abstract":"<div><div>With the increasing miniaturization and complexity of electronic packaging, accurately characterizing internal mechanical responses through finite element simulation has become crucial for reliability assessment. This study comparatively evaluates the damage-coupled Unified Creep Plasticity (UCP) model and Anand model in simulating solder joint behavior under cyclic loading across material and structural levels. Material-level simulations of the SAC305 alloy under uniaxial tension-compression reveal that the damage-coupled UCP model yields smoother stress-strain curves with better experimental agreement, while the Anand model exhibits folded inflections near yield points, showing 12 % strain deviation. Structural-level analysis employing silicon-embedded stress sensors demonstrates that the UCP model's stress evolution correlates strongly with experimental measurements, whereas the Anand model shows 15–20 % peak stress deviations. Three-dimensional flip-chip BGA modeling further clarifies mechanistic differences: The Anand model omits plastic phase evolution, only capturing elastic and creep stages, while the UCP model fully describes three-phase evolution (elastic-plastic-creep), accurately reflecting actual deformation mechanisms. These multi-scale results validate the UCP model's superiority in characterizing visco-plastic behavior of solder joints, providing critical theoretical support for packaging reliability optimization.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"172 ","pages":"Article 115838"},"PeriodicalIF":1.6,"publicationDate":"2025-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144365557","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Long-term positive and negative gate bias stress tests on parallel connected SiC MOSFETs at −40 °C and 175 °C","authors":"A. Deb ,&nbsp;M. Taha ,&nbsp;J. Ortiz Gonzalez ,&nbsp;P. Mawby ,&nbsp;S. Jahdi ,&nbsp;B. Etoz ,&nbsp;O. Alatise","doi":"10.1016/j.microrel.2025.115834","DOIUrl":"10.1016/j.microrel.2025.115834","url":null,"abstract":"<div><div>Bias temperature instability (BTI) is known to adversely impact the performance of parallel connected SiC MOSFETs. The short circuit robustness of SiC modules is known to reduce with increased threshold voltage (<em>V</em>_<em>TH</em>) variation within the parallel devices due to poor current sharing. In this paper, 400-h positive BTI (<em>V</em>_<em>GS</em> = 25 V) and negative BTI (<em>V</em>_<em>GS</em> = −10 V) stress tests at both −40 °C and 175 °C have been performed on 5 parallel connected SiC MOSFETs. Both the individual <em>V</em>_<em>TH</em> shift for each of the 5 devices and the module <em>V</em>_<em>TH</em> shift have been measured alongside the <em>V</em>_<em>TH</em> range (highest <em>V</em>_<em>TH</em> minus lowest <em>V</em>_<em>TH</em>). Bipolar preconditioning has been performed before <em>V</em>_<em>TH</em> measurement to record both the peak <em>V</em>_<em>TH</em> (measured before bipolar preconditioning) and permanent <em>V</em>_<em>TH</em> (measured after bipolar preconditioning). The results show that p-BTI stress yields 21 % higher peak module <em>V</em>_<em>TH</em> shift compared to n-BTI at −40 °C and 29 % higher at 175 °C. The measured <em>V</em>_<em>TH</em> range was unchanged by the BTI tests if permanent <em>V</em>_<em>TH</em> shift is assessed. However, the peak <em>V</em>_<em>TH</em> range was higher after stressing thereby indicating increased variability in the injected temporary charge. The peak <em>V</em>_<em>TH</em> range also exhibits a positive temperature coefficient indicating that temperature increases variability of the injected charge. If <em>V</em>_<em>TH</em> range is taken as an indicator of short circuit robustness in parallel connected devices, the measurements presented show that bipolar preconditioning ensures that the short circuit performance of the module would likely be unaffected by the stress tests since <em>ΔV</em>_<em>TH</em> shift is uniform.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"172 ","pages":"Article 115834"},"PeriodicalIF":1.6,"publicationDate":"2025-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144338743","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Research on high-power high-frequency electrical transmission characteristics of through glass via interconnections","authors":"Luming Chen ,&nbsp;Shitao Wang ,&nbsp;Zhilin Wei ,&nbsp;Zhizhen Wang ,&nbsp;Yihan Xie ,&nbsp;Chunlei Li ,&nbsp;Shenglin Ma ,&nbsp;Shuwei He ,&nbsp;Hai Yuan","doi":"10.1016/j.microrel.2025.115828","DOIUrl":"10.1016/j.microrel.2025.115828","url":null,"abstract":"<div><div>Through Glass Via (TGV) have attracted significant attention as advanced package solutions. Compared to silicon, glass has lower dielectric losses but thermal conductivity two orders of magnitude lower. This may introduce transmission degradation due to self electro-thermal coupling in high-power, high-frequency signal applications such as RadioFrequency (RF) transceiver and high-performance computing chip package. To address the issue, A Microstrip Resonant Ring (MRR) test structure was designed and fabricated for temperature-dependent high-frequency parameter extraction. Coplanar Waveguide (CPW) and Substrate integrated waveguide (SIW) test structures were designed and fabricated for high-frequency transmission tests at various temperatures. A quadruple redundant TGV connected CPW test structure was designed and fabricated for high-frequency high-power self electro-thermal testing, followed with self electro-thermal coupling simulation to verify experimental results. The research reveals that, under high-power, high-frequency signal input, transmission losses in TGV interconnects are primarily dominated by conductor losses. The optimized quadruple redundant TGV connected CPW test structure demonstrated insertion losses of 0.51 dB, 0.94 dB, and 2.04 dB under input conditions of 10 W@6GHz, 7.9 W@12GHz, and 6.3 W@18GHz, respectively. The corresponding maximum temperatures recorded were 36.2 °C, 38.4 °C, and 55 °C for these operating conditions.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"172 ","pages":"Article 115828"},"PeriodicalIF":1.6,"publicationDate":"2025-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144321986","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"High-performance, low-area-overhead, and low-delay triple-node-upset self-recoverable latch design based on stacked transistors","authors":"Hui Xu ,&nbsp;Yue Dai ,&nbsp;Ruijun Ma ,&nbsp;Huaguo Liang ,&nbsp;Zhengfeng Huang ,&nbsp;Tianming Ni ,&nbsp;Chuanjian Zhang ,&nbsp;Xin Chen ,&nbsp;Ye Tang","doi":"10.1016/j.microrel.2025.115830","DOIUrl":"10.1016/j.microrel.2025.115830","url":null,"abstract":"<div><div>Due to the gradual reduction in the feature size of transistors in integrated circuits (ICs), triple-node-upsets (TNUs) caused by the striking of energetic particles in harsh radiation environments have become a considerable reliability concern for ICs. To overcome the limitations of current radiation-hardened designs regarding overhead and reliability, this paper proposes a high-performance, low-area-overhead, and low-delay TNU self-recoverable latch (HLLT) based on N-type stacked transistors for aerospace applications. The proposed HLLT latch comprises three symmetrical modules that protect each other. In addition, high-speed path and clock gating technology are employed to reduce delay overhead and power consumption, respectively. Simulation results show that, compared to five existing TNU-recoverable latches, the proposed HLLT latch achieves average reductions of 29.97 %, 57.12 %, 36.52 %, and 83.00 % in area overhead, power consumption, delay, and area-power-delay-product (APDP), respectively. Furthermore, the proposed HLLT latch has lower sensitivity and better stability to variations in PVT (Process, Voltage, Temperature).</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"172 ","pages":"Article 115830"},"PeriodicalIF":1.6,"publicationDate":"2025-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144321985","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Thermo-electrical reliability of power MOSFETs influenced by packaging architecture in stack-die and single-die configurations","authors":"You-Cheol Jang","doi":"10.1016/j.microrel.2025.115831","DOIUrl":"10.1016/j.microrel.2025.115831","url":null,"abstract":"<div><div>As the demand for high-power semiconductor devices continues to grow, wide bandgap (WBG) MOSFETs are being increasingly adopted across diverse power electronic applications. Compared to conventional Si-based MOSFETs, however, the reliability characteristics of WBG devices, particularly those employing cascode GaN configurations, remain inadequately explored from a packaging standpoint. This study presents a comparative investigation of degradation mechanisms and failure modes in a 650 V vertical Si MOSFET with a single-die package and a cascode GaN FET integrated with a Si MOSFET in a stack-die configuration. A Highly Accelerated Life Test (HALT) combining temperature and power cycling was implemented, with the Coffin-Manson model yielding an acceleration factor of 1.66, thereby reducing the total test time by 14 h. In parallel, gate bias stress was evaluated using Weibull distribution modeling, which identified 30 <em>V</em> as a critical threshold for initiating accelerated degradation without immediate device breakdown.</div><div>The results demonstrate that packaging architecture significantly influences solder joint degradation and overall thermal performance. The findings also confirm the value of the proposed HALT methodology in efficiently identifying failure mechanisms, providing actionable insights into the packaging reliability of 650 <em>V</em> power MOSFETs under harsh operating conditions.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"172 ","pages":"Article 115831"},"PeriodicalIF":1.6,"publicationDate":"2025-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144321984","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Design of an energy-efficient soft error resilient RHBD SRAM cell with high read stability and minimum write errors","authors":"Biby Joseph,&nbsp;R.K. Kavitha","doi":"10.1016/j.microrel.2025.115812","DOIUrl":"10.1016/j.microrel.2025.115812","url":null,"abstract":"<div><div>This article proposes an energy-efficient, soft-error tolerant, read-stability improved SRAM cell with less Write Error Rate (WER). The proposed S8P9N has 8 PMOS and 9 NMOS transistors including access transistors. This SRAM cell has only two sensitive nodes, achieved by surrounding the nodes with the same type of transistors. The proposed cell is immune to all Single Event Upsets (SEUs) at sensitive nodes and shows 83.3% and 50% tolerance to Double Node Upsets (DNUs) and Triple Node Upsets (TNUs) respectively. The four access transistors in the S8P9N cell reduce write delay, and WER. Additionally, the proposed SRAM cell achieves the lowest dynamic power dissipation of 1.25 <span><math><mi>μ</mi></math></span>W, high read stability of 320 mW, and low read and write energy of 0.83 aJ and 0.07 fJ, respectively. All designs are implemented using UMC 65 nm technology, operating at a supply voltage of 1.2 V and at a temperature of 27 °<span><math><mi>C</mi></math></span>. Reliability is analyzed through 5000-point Monte Carlo (MC) simulation under various Process Voltage Temperature (PVT) conditions. The proposed design has a critical charge, Qc of <span><math><mo>&gt;</mo></math></span> 90 fC . The S8P9N RHBD SRAM cell has a minimum soft error occurrence probability (P<span><math><msub><mrow></mrow><mrow><mi>S</mi></mrow></msub></math></span>) of 1.6%. The combination of low power consumption, low energy, high read stability, less write error rate of <span><math><mo>&lt;</mo></math></span> 0.1%, and improved reliability makes the S8P9N design suitable for low-power cache in aerospace applications.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"172 ","pages":"Article 115812"},"PeriodicalIF":1.6,"publicationDate":"2025-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144313800","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}