Microelectronics Reliability最新文献

{"title":"Deformation mechanism and optimization of high-density organic substrates during reflow soldering","authors":"Rongxing Cao ,&nbsp;Bang Qian ,&nbsp;Yuxiong Xue ,&nbsp;Jiaen Fang ,&nbsp;Yang Liu","doi":"10.1016/j.microrel.2024.115507","DOIUrl":"10.1016/j.microrel.2024.115507","url":null,"abstract":"<div><p>High-frequency organic dielectric substrate materials have been widely applied in the fabrication of FCBGA (Flip Chip Ball Grid Array) substrates due to their excellent characteristics of high-speed signal transmission. However, their higher coefficient of thermal expansion (CTE) causes the CTE mismatch between the chip and substrate to increase. High-temperature heating during the reflow soldering process intensifies the thermal mismatch within packaging structure, causing severe warping of the substrate, thereby reducing the yield and subsequent reliability. This study adopted a flatness analyzer and scanning electron microscope (SEM) to characterize the package deformation and micromorphology, and found that the substrate warped after reflow soldering, which caused defects such as chip cracks and micro-bump delamination. A fine finite element simulation model was constructed based on the structure of the experimental sample, and the structure deformation during the soldering process was simulated. An accurate finite element simulation model was constructed based on the structure of the experimental sample to simulate the deformation process of substrate during reflow. Research results show that the constraint of the chip on the substrate during the soldering process is the main factor affecting the thermal deformation mechanism, and the deformation can be suppressed by adding stiffener. This research benefits to the design of FCBGA high-density packaging.</p></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"162 ","pages":"Article 115507"},"PeriodicalIF":1.6,"publicationDate":"2024-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142272159","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Novel Latin square matrix code of large burst error correction for MRAM applications","authors":"Hui Jin ,&nbsp;Xiaoyang Xu ,&nbsp;Zhaohao Wang ,&nbsp;Siyu Chen ,&nbsp;Jing Guo ,&nbsp;Bi Wang","doi":"10.1016/j.microrel.2024.115505","DOIUrl":"10.1016/j.microrel.2024.115505","url":null,"abstract":"<div><p>With the scaling down of the technology node of complementary metal–oxide–semiconductor (CMOS) , the bit error rate (BER) of magnetic random memory (MRAM) seriously threats the reliability, especially multiple-cell upset (MBUs). Error correction codes (ECCs) such as one-step majority logic decodable (OS-MLD) codes are proposed with strong error correction capabilities, and efficient hardware overhead. However, the OS-MLD codes are not suitable for the burst error correction, which require more redundancy bits or extra memory cells. A novel m order Latin square matrix (LSM) codes for MRAM are presented, which can provide fewer equivalent bits and more flexible adjustments for correcting large burst errors. The 5-bit LSM code area is only 90898.71 <span><math><mrow><mi>μ</mi><msup><mrow><mi>m</mi></mrow><mrow><mn>2</mn></mrow></msup></mrow></math></span>, and the power consumption is only 0.82 mw.</p></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"162 ","pages":"Article 115505"},"PeriodicalIF":1.6,"publicationDate":"2024-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142243355","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Investigation on the microstructure, mechanical properties and chlorine resistance of fine aluminum alloy wires","authors":"Bo-Ding Wu,&nbsp;Fei-Yi Hung,&nbsp;Keng-Yi Hsu","doi":"10.1016/j.microrel.2024.115498","DOIUrl":"10.1016/j.microrel.2024.115498","url":null,"abstract":"<div><p>Wire bonding is a fundamental and mature technology in semiconductor packaging process, primarily using materials such as gold, silver, aluminum, and copper for the wires. To address application limitations of aluminum wires, such as low electromigration resistance and limited ductility, techniques including to enhance alloying (with Zn and Si), heat treatment, and surface treatment are employed to enhance the performance of aluminum alloy wires and broaden their application value. This study selects Al-3Zn-0.3Si (AZS303) and Al-7Zn-0.3Si (AZS703), with AZS303 undergoing gold plating to produce AC-AZS303 wires. Various high-temperature heat treatments are applied, verifying that under 400 °C conditions, the AZS series aluminum alloy wires exhibit grain growth and form single-crystal equiaxed grain structures, resulting in stable mechanical properties and excellent electrical performance. Additionally, the AC-AZS303 wires optimize resistance values through gold layer diffusion induced by the electrothermal effect.</p><p>Chlorine experiments indicates that the gold plating on AC-AZS303 can't enhance the aluminum wire's resistance to chlorine corrosion. However, the alloying effect of zine and silicon elements imparts excellent chlorine corrosion resistance to the Al-Zn-Si wires. This study of bonding properties examines the bond strength and observes the bonded area of Al-Zn-Si wires after bonding. It is noted that the H400-AZS303 wire exhibits the best bond strength and bonding area, demonstrating good bonding with the substrate.</p></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"162 ","pages":"Article 115498"},"PeriodicalIF":1.6,"publicationDate":"2024-09-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142231981","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Radiation hardened P-Quatro 12T SRAM cell with strong SEU tolerance for aerospace applications","authors":"Debabrata Mondal,&nbsp;Syed Farah Naz,&nbsp;Ambika Prasad Shah","doi":"10.1016/j.microrel.2024.115497","DOIUrl":"10.1016/j.microrel.2024.115497","url":null,"abstract":"<div><p>The aerospace environment contains extremely energetic particles that trigger single-event transients (SET), leading to single-event upsets (SEU) in the memory cell. An efficient SRAM cell must be designed to tolerate soft error to withstand the extreme environment. This paper proposes a highly efficient radiation hardened-by-design 12T P-Quatro SRAM cell based on a polarity upset mechanism. The proposed cell has better writability, and WSNM is 1.08<span><math><mo>×</mo></math></span> higher than its counterpart We-Quatro SRAM cell. The read access time of the proposed SRAM cell is 0.96<span><math><mo>×</mo></math></span>, 0.91<span><math><mo>×</mo></math></span>, 0.99<span><math><mo>×</mo></math></span>, 0.98<span><math><mo>×</mo></math></span> smaller than 6T, Quatro, We-Quatro, and NQuatro SRAM cells, and 1.01<span><math><mo>×</mo></math></span> higher than RHD12T cell, and the write delay of the proposed SRAM is 0.93<span><math><mo>×</mo></math></span>, 0.46<span><math><mo>×</mo></math></span>, 0.72<span><math><mo>×</mo></math></span>, 0.41<span><math><mo>×</mo></math></span>, 0.47<span><math><mo>×</mo></math></span>, less than that of 6T, Quatro, We-Quatro, RHD12T, and NQuatro respectively. 2000 Monte Carlo simulation for power dissipation and upset margin reveals that the process variation has less impact on the proposed SRAM and 1.64<span><math><mo>×</mo></math></span> better tolerance against logic flipping. Further, for the P-Quatro, the critical charge is 41.51 fC and is 2.05<span><math><mo>×</mo></math></span>, 1.75<span><math><mo>×</mo></math></span>, 1.93<span><math><mo>×</mo></math></span>, and 1.48<span><math><mo>×</mo></math></span> greater than Quatro, We-Quatro, RHD12T, and NQuatro memory cells. We conducted an assessment using an electrical quality matrix (EQM) that takes into account all performance parameters. The findings reveal that the EQM of the proposed cell surpasses that of the 6T, Quatro, We-Quatro, RHD12T, and NQuatro SRAM cells by factors of 0.82<span><math><mo>×</mo></math></span>, 0.35<span><math><mo>×</mo></math></span>, 0.49<span><math><mo>×</mo></math></span>, 0.71<span><math><mo>×</mo></math></span>, and 0.21<span><math><mo>×</mo></math></span>, respectively. This indicates that the proposed cell demonstrates superior electrical quality across various metrics compared to the other SRAM cell designs evaluated.</p></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"162 ","pages":"Article 115497"},"PeriodicalIF":1.6,"publicationDate":"2024-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142150715","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Revisiting the effectiveness of diamond heat spreaders on multi-finger gate GaN HEMT using chip-to-package-level thermal simulation","authors":"Amir Murtadha Mohamad Yussof ,&nbsp;Mohd Faizol Abdullah ,&nbsp;Muhammad Nur Affendy Muhammad Ridzwan ,&nbsp;Norazreen Abd Aziz ,&nbsp;Hing Wah Lee","doi":"10.1016/j.microrel.2024.115496","DOIUrl":"10.1016/j.microrel.2024.115496","url":null,"abstract":"<div><p>The study of chip-level and package-level heat transfer in a GaN high electron mobility transistor (HEMT) is often disconnected due to limited resources and tools. In this work, device simulation from Silvaco Victory Device is carried forward to the chip-to-package-level simulation using Icepak to provide a complete picture of the proposed thermal management strategies using polycrystalline diamond (PCD) heat spreaders. The max junction temperature, <em>T</em>_<em>j</em> = 105.8 °C and the relative magnitude of max temperature on the GaN surface, Δ<em>T</em>_<em>j</em> = 18 % are recorded for the original Si-GaN-Si₃N₄ chip inside TO-220 at 6.0 Wmm⁻¹. Replacing the Si₃N₄ with PCD (thermal conductivity of 500 Wm⁻¹ K⁻¹) results in <em>T</em>_<em>j</em> = 98.2 °C and Δ<em>T</em>_<em>j</em> = 8 %, while replacing the Si results in <em>T</em>_<em>j</em> = 97.0 °C and Δ<em>T</em>_<em>j</em> = 11 %. The top layer PCD spreads the heat from hotspot regions to the surrounding epoxy, while the bottom layer PCD improves the heat path from the hotspots to the base plate. Therefore, the reduction in <em>T</em>_<em>j</em> by the bottom layer PCD is more important than the reduction in Δ<em>T</em>_<em>j</em> by the top layer PCD. Implementing both the top and bottom layers of PCD results in the best offers of <em>T</em>_<em>j</em> = 92.9 °C and Δ<em>T</em>_<em>j</em> = 6 %. The performance of PCD as heat spreaders in multi-finger gate GaN HEMT suggested by these chip-to-package-level simulations are more reliable than device simulation alone since they cover the complete heat path from generation, conduction within the package, and convection to the ambient air.</p></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"161 ","pages":"Article 115496"},"PeriodicalIF":1.6,"publicationDate":"2024-08-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142095514","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"The sensitivity analysis of geometric parameters on the power cycling reliability of bond wires","authors":"Luhong Xie ,&nbsp;Erping Deng ,&nbsp;Dianjie Gu ,&nbsp;Hao Liu ,&nbsp;Ying Zhang ,&nbsp;Yongzhang Huang","doi":"10.1016/j.microrel.2024.115495","DOIUrl":"10.1016/j.microrel.2024.115495","url":null,"abstract":"<div><p>Considering the reliability of the bond wire comes as the main factor determining the reliability of power devices at present, and the geometric parameters of the bond wire have an in-negligible effect. A Finite Element (FE) simulation model based on a discrete device with TO-247 package and a single bond wire is established in this paper, and the influences of the geometric parameters are analyzed, which include the joint length <em>L</em>, the diameter <em>D</em>, and the aspect ratio <em>λ</em>. Then to understand the influence degree of the parameter on the reliability, the sensitivity analysis of these geometric parameters is carried out based on the sobol' method, using the Monte Carlo method for estimating the sensitivity index. The results show that increasing the joint length <em>L</em>, the diameter <em>D</em> and the aspect ratio <em>λ</em> all have a negative impact on the bond wire reliability, while a positive influence is presented by increasing the aspect ratio <em>λ</em> in the case without epoxy mold compound (EMC). This is because of the EMC's protective effect which inhibits the bond wire's thermal expansion. The aspect ratio <em>λ</em> is the most sensitive parameter of the three geometric parameters since it has the largest total sensitive index.</p></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"161 ","pages":"Article 115495"},"PeriodicalIF":1.6,"publicationDate":"2024-08-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142095515","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Enhancing flexible electronics: Unveiling the role of strain rate in the performance of molybdenum-coated PET films","authors":"Atif Alkhazali ,&nbsp;Mohammad M. Hamasha ,&nbsp;Haitham Khaled ,&nbsp;Mohammad Shbool ,&nbsp;Mazin Obaidat","doi":"10.1016/j.microrel.2024.115485","DOIUrl":"10.1016/j.microrel.2024.115485","url":null,"abstract":"<div><p>This work analyzes the mechanical and electrical properties of molybdenum (Mo) thin films at 100 and 200 nm thicknesses under different strain and strain rate circumstances. The study examines Mo film deposition by RF magnetron sputtering on PET substrates and their mechanical stress behavior. The investigation reveals distinct patterns of crack initiation and propagation, where primary cracks predominantly appear perpendicular to the direction of applied strain, and secondary cracks develop due to stress redistribution, displaying a complex interplay between film thickness, strain rate, and crack morphology. A key finding of this study is the observation of more advanced and irregular crack patterns in thicker films (200 nm) subjected to higher strain rates (1000 mm/min), suggesting a heightened sensitivity to mechanical stress and a more chaotic fracture process compared to thinner films or those under lower strain rates. Additionally, instances of film edge delamination, particularly under high strain conditions, highlight the challenges in maintaining film-substrate adhesion and integrity under extreme mechanical deformation. The research provides critical insights into the mechanical robustness and electrical performance of Mo thin films, emphasizing the influence of microstructural properties, deposition parameters, and external stressors on their applicability in high-tech industries. The findings underscore the importance of optimizing deposition techniques and understanding material behavior under stress to enhance the durability and reliability of Mo thin films in practical applications, ranging from semiconductor devices to photovoltaic systems.</p></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"161 ","pages":"Article 115485"},"PeriodicalIF":1.6,"publicationDate":"2024-08-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142083974","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Effect of solder junction void variation in power semiconductor package on power cycle lifetime","authors":"Hiroshi Onodera ,&nbsp;Nobuyuki Shishido ,&nbsp;Daisuke Asari ,&nbsp;Hiroshi Isono ,&nbsp;Wataru Saito","doi":"10.1016/j.microrel.2024.115471","DOIUrl":"10.1016/j.microrel.2024.115471","url":null,"abstract":"<div><p>Power semiconductor modules, such as IGBT and power MOSFET modules, have been increasingly used due to the growing application market, such as electric vehicles and renewable energy. A long lifetime of power semiconductor modules is strongly required, and the power cycle test is an important evaluation. Cracks in the mount solder of power semiconductor package are one of the main factors affecting the power cycle lifetime due to the increase in thermal resistance. Variations in the mounting process during the package assembly may lead to solder voids in the initial state, causing stress within the solder joint and influencing the power cycle lifetime. This paper reports the effect of the void ratio of chip mount solder on power cycle lifetime. Samples with intentionally varied initial void ratios and void positions were fabricated, and their power cycle lifetimes were evaluated. The results show that the power cycle lifetime is determined by the Coffin-Manson law, even with different void ratios and positions.</p></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"161 ","pages":"Article 115471"},"PeriodicalIF":1.6,"publicationDate":"2024-08-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142020765","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A machine learning approach to accelerate reliability prediction in nanowire FETs from self-heating perspective","authors":"T. Sandeep Kumar ,&nbsp;Anusha Hazarika ,&nbsp;P.S.T.N. Srinivas ,&nbsp;Pramod Kumar Tiwari ,&nbsp;Arun Kumar","doi":"10.1016/j.microrel.2024.115484","DOIUrl":"10.1016/j.microrel.2024.115484","url":null,"abstract":"<div><p>Nanowire Field Effect Transistors (NWFETs) have been considered as the next-generation technology for sub-10 nm technology nodes, succeeding FinFETs. However, the highly confined nature of Nanowire FETs creates reliability issues that significantly impact their performance. Therefore, this work proposes a machine learning-based technique for analyzing the self-heating-induced reliability issues in NWFETs. The influence of self-heating effects in NWFET has been predicted in terms of saturation current (I_dsat), threshold voltage (V_th), the maximum carrier temperature along the channel (eTmax), and the maximum Lattice temperature (LTmax) with multivariable regression. TCAD-assisted machine learning has been used for algorithm training and prediction. A dataset has been created by varying the parameters of the NWFETs like the thickness of the channel (t_si), the thickness of oxide (t_ox), Length of source/drain (L_sd), length of source/drain contact (L_sdc), doping concentrations etc. The Random Forest Regression algorithm has been used to estimate the performance of NWFETs in predicting the desired output parameters suitably with the given dataset.</p></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"161 ","pages":"Article 115484"},"PeriodicalIF":1.6,"publicationDate":"2024-08-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142011340","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Thermal cycling characterization of an integrated low-inductance GaN eHEMT power module","authors":"Zhongchao Sun,&nbsp;Masaki Takahashi,&nbsp;Wendi Guo,&nbsp;Stig Munk-Nielsen,&nbsp;Asger Bjørn Jørgensen","doi":"10.1016/j.microrel.2024.115482","DOIUrl":"10.1016/j.microrel.2024.115482","url":null,"abstract":"<div><p>To exploit the potential of wide-bandgap semiconductors in high-frequency applications, innovative packaging designs are developed to minimize the parasitic inductance of power modules. This study presents an integrated power module with a hybrid PCB/DBC structure, which uses top-side cooling prepackaged GaN enhancement-mode high-electron-mobility transistors. The module achieves a remarkably low parasitic inductance of 2.65 nH. However, there is relatively scarce research on the reliability of this heterostructure, particularly its sensitivity to thermomechanical stress due to the coefficients of thermal expansion mismatch among material interfaces. In this work, the thermal cycling characteristics of the integrated power module are comprehensively investigated. Electrical and thermal parameters were periodically and separately measured offline on a simplified package to monitor the health conditions and decouple possible synergy and competition effects among the failure modes from all packaging components. A thorough failure analysis was conducted using nondestructive visual inspections and scanning acoustic microscopy, complemented by destructive cross-sectional examination and scanning electron microscopy. The findings identified the delamination of the DBC upper copper layer, which exhibited a conchoidal fracture interface, as the primary factor that contributed to the failure of the power module with increased thermal resistance. Furthermore, the study dissected its initiation and propagation mechanisms. This investigation provides valuable insights for the development of more reliable low-inductance power module designs.</p></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"161 ","pages":"Article 115482"},"PeriodicalIF":1.6,"publicationDate":"2024-08-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://www.sciencedirect.com/science/article/pii/S0026271424001628/pdfft?md5=038e1075694401238843879d449ea601&pid=1-s2.0-S0026271424001628-main.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142011339","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}