Microelectronics Reliability最新文献

{"title":"Design and verification of silicon bridge in 2.5D advanced package based on universal chiplet interconnect express (UCIe)","authors":"Yuxuan Fan ,&nbsp;Yunyan Zhou ,&nbsp;Qidong Wang ,&nbsp;Bo Lei ,&nbsp;Gang Song ,&nbsp;Wenwen Zhang ,&nbsp;Hanchen Gan","doi":"10.1016/j.microrel.2025.115710","DOIUrl":"10.1016/j.microrel.2025.115710","url":null,"abstract":"<div><div>This paper presents the design and verification of an embedded silicon bridge interconnect structure for 2.5D advanced packaging based on the Universal Chiplet Interconnect Express (UCIe). To enable high-speed, low-latency communication between chiplets, various routing patterns and transmission structures were explored. Layouts and test vehicles were designed with bump pitches of 45 μm and 55 μm and underwent fabrication for validation. Test results indicate that the silicon bridge demonstrates excellent signal integrity (SI) at a transmission rate of 32 Gbps, with S-parameter, Voltage Transfer Function (VTF) and eye diagram test results all meeting UCIe specifications for advanced packaging, highlighting the feasibility of this interconnect structure for high-density integration and high-speed transmission. This research provides a viable design and manufacturing solution for UCIe-based chiplet interconnects and validates the potential of embedded silicon bridges in heterogeneous integration applications.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"168 ","pages":"Article 115710"},"PeriodicalIF":1.6,"publicationDate":"2025-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143705195","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"ESD Human Body Model step stress distributions of GaN HEMTs and the correlation with one level test results","authors":"R.A. van der Berg ,&nbsp;E. Jellema","doi":"10.1016/j.microrel.2025.115699","DOIUrl":"10.1016/j.microrel.2025.115699","url":null,"abstract":"<div><div>Evaluation of the Electro Sensitivity Discharge (ESD) robustness of Radio Frequency (RF) GaN HEMTs can result in different Human Body Model (HBM) ESD classifications due to different sample sizes, batch-to-batch variations, different test methodology and differences in the test set-up. For example, a low sample sizes per voltage level can lead to a higher classification level.</div><div>Two GaN HEMTs processed in the same technology with different power ratings were investigated with (i) step stress testing, and (ii) with testing at one voltage level, using different test set-ups and different wafer and assembly batches. A lognormal distribution gives a good fit for the HBM failure voltages acquired from step stress testing and can quantify the differences between GaN HEMTs, test set-ups and different batches.</div><div>The failure percentages observed with one level testing can be significantly lower than what is expected based on the step stress HBM failure distribution. Furthermore, the spread observed in the HBM failure distributions acquired by testing at one voltage level is significantly larger than the spread observed in the HBM failure distribution as determined by step stress testing.</div><div>The differences between one level and the step stress failure distribution can be explained by presence of traps inside the GaN HEMT devices.</div><div>Furthermore, the ESD classification according to JS-001 [1] is discussed and how Operating Characteristics (OC) curves can be used to compare ESD test plans with different sample sizes and number of failures observed.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"168 ","pages":"Article 115699"},"PeriodicalIF":1.6,"publicationDate":"2025-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143697144","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A PMOS-embedded low-voltage triggered silicon controlled rectifier ESD protection device for 3.3V I/O application","authors":"Jun Deng,&nbsp;Hongjiao Yang,&nbsp;Yang Wang,&nbsp;Fengfeng Zhou,&nbsp;Haotian Chen,&nbsp;Beibei Nie,&nbsp;Wei Liu","doi":"10.1016/j.microrel.2025.115706","DOIUrl":"10.1016/j.microrel.2025.115706","url":null,"abstract":"<div><div>In this paper, a novel low-trigger-voltage and high-robustness Electrostatic Discharge (ESD) protection device, called PMOS-embedded Low-Voltage Triggered Silicon Controlled Rectifier (PLVTSCR), is proposed for 3.3V I/O protection application in 0.18 μm CMOS process. The first improved PLVTSCR is called PLVTSCR-A. It is achieved by introducing a PMOS into the traditional SCR to provide a trigger current for SCR, thereby reducing the traditional SCR's trigger voltage (<em>V</em>_t1) and further increasing the failure current (<em>I</em>_t2) by utilizing the PMOS to introduce an additional parasitic SCR path. The second improved PLVTSCR is called PLVTSCR-B. The difference between PLVTSCR-B and PLVTSCR-A is that PLVTSCR-B does not have the DNW layer, making the base region of the parasitic NPN open circuit, further reducing PLVTSCR-A's trigger voltage. The third device is called PLVTSCR-C. PLVTSCR-C is another layout structure of PLVTSCR-B, and it can increase the holding current (<em>I</em>_h) and holding voltage of the device without increasing the area. The proposed series of devices can significantly improve the ESD characteristics of traditional SCR. Measurement results show that the PLVTSCR-C's trigger voltage is reduced by 51.5 %, and the failure current is increased by 10.3 % compared to traditional SCR. Furthermore, the holding current of PLVTSCR-C is 328.5 mA, which is much higher than the current during normal operation of the circuit and can effectively prevent latch-up. Additionally, the new device is expected to protect 3.3V I/O in deep submicron technology and has been implemented in a 0.18 μm CMOS process.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"168 ","pages":"Article 115706"},"PeriodicalIF":1.6,"publicationDate":"2025-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143679926","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Localization of heavy doping missing defect in MOSFET by the combined use of nanoprobing analysis and SCM technique","authors":"Shijun Zheng ,&nbsp;Xiangdong Wang ,&nbsp;Yi Che","doi":"10.1016/j.microrel.2025.115707","DOIUrl":"10.1016/j.microrel.2025.115707","url":null,"abstract":"<div><div>The paper demonstrates an effective flow to localize heavy doping missing defect accurately in failed metal-oxide-semiconductor field-effect transistor (MOSFET). It is commonly known that it is not feasible to localize rare doping anomaly and further visualize the corresponding less doped regions in MOSFET relying on ordinary transmission electron microscopy (TEM) analysis since the dopant distribution is not detectable for TEM. Nevertheless, we found that this kind of defect can be isolated by the combined use of nanoprobing analysis and scanning capacitance microscopy (SCM) technique. The combinational solution was rarely reported before. Nanoprobing analysis of transfer characteristic of failed MOSFET confirms the on-state current drop by two orders of magnitude. Next, the contacting state at source and drain region of MOSFET is examined. Current-voltage (I-V) characteristic of source and drain p-n junctions indicates that high contact resistance comes from metal-semiconductor interface change from ohmic contact to rectifying contact unexpectedly. Eventually, intensive analysis of SCM data proves that tungsten plugs touch lightly doped silicon so that the outcome leads to the formation of Schottky junction that owns rectifying I-V characteristic. In contrast, the tungsten plug touching heavily doped silicon produces ohmic contact, so it keeps normal I-V characteristic of p-n junction. Energy-band theory explains that I-V characteristic of metal-semiconductor interface is closely related to doping concentration in silicon since it determines the potential barrier width at interface where mobile carrier transport phenomenon occurs. The potential barrier width increases as the doping concentration decreases in the silicon side of the interface. We conclude that lack of heavy doping in MOSFET source and drain areas is responsible for high contact resistance. In the article, we present several practical examples to show accurate localization of heavy doping missing defect in different PMOS and NMOS. Furthermore, unwanted over-etching of tungsten plug hole caused MOSFET failure is also studied since it looks quite like heavy doping missing induced electrical fault. Our study promotes the understanding of failure mechanism about heavy doping missing defect in MOSFET of diverse mainstream technology nodes.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"168 ","pages":"Article 115707"},"PeriodicalIF":1.6,"publicationDate":"2025-03-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143679908","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Studies on Joint failure model of negative bias temperature instability and hot carrier degradation","authors":"Zhenyu Wu,&nbsp;Zhen Chai,&nbsp;Binyang Liu,&nbsp;Menglong Liu","doi":"10.1016/j.microrel.2025.115700","DOIUrl":"10.1016/j.microrel.2025.115700","url":null,"abstract":"<div><div>In this paper, a unified Joint model of negative bias temperature instability (NBTI) and hot carrier degradation (HCD) is proposed. It is based on the reaction-diffusion theoretical framework for an in-depth study of the mechanism of threshold voltage degradation of transistors under mixed stresses. The model fully considers the coupling effect of NBTI and HCD under actual operating conditions, and systematically describes the common impact of these two failure mechanisms on device performance through physical modeling and mathematical derivation. On this basis, a new circuit-level reliability simulation method combining failure modeling, stress profile extraction, and failure injection techniques is developed, aiming to provide an efficient and accurate solution for IC reliability analysis. With this method, the performance degradation of ring oscillator and SRAM memory circuits is investigated. The simulation results show that the proposed Joint failure model accurately describes the NBTI and HCD processes, which not only has good physical consistency, but also significantly reduces the computation time and complexity, and has a wide application prospect in the reliability assessment of large-scale integrated circuits.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"168 ","pages":"Article 115700"},"PeriodicalIF":1.6,"publicationDate":"2025-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143679925","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Stress–strain analysis and prediction of WLCSP solder joints under bending–torsion coupled loading","authors":"Lixiang Huang ,&nbsp;Chunyue Huang ,&nbsp;Chao Gao ,&nbsp;Ying Liang","doi":"10.1016/j.microrel.2025.115704","DOIUrl":"10.1016/j.microrel.2025.115704","url":null,"abstract":"<div><div>With the trend of miniaturization in electronic components, Wafer-Level Chip Scale Package(WLCSP) chips, known for their compact size, are widely used in various electronic devices. During the operation of these devices, they are inevitably subjected to bending and torsional loads, such as frequent touches on smartphone screens, the opening and closing actions of laptop screens, and keyboard typing. Research on the stress and strain of WLCSP solder joints is crucial for the reliability design of these joints, thereby enhancing the overall reliability of electronic devices. Therefore, this study establishes a finite element model of WLCSP solder joints and conducts a finite element analysis of their stress and strain under bending–torsion coupling loads.A strain testing platform for WLCSP solder joints under bending–torsion coupled loading was developed, and strain measurement tests were performed to verify the accuracy of the simulation results. Three structural parameters of the WLCSP solder joint — solder joint diameter, pad diameter, and solder joint height — were selected as influencing factors. Using the orthogonal design method, 16 different combinations of structural parameter levels for the WLCSP solder joints were designed to obtain the maximum bending–torsion coupled stress, followed by range and variance analysis of the maximum stress. A particle swarm optimization (PSO)–Back Propagation(BP) neural network prediction model for the bending–torsion coupled stress of the WLCSP solder joint was developed to predict the stress. The results indicate that, among the three structural parameters — solder joint diameter, pad diameter, and solder joint height — the ranking of their influence on the WLCSP solder joint bending–torsion coupled stress is as follows: solder joint height <span><math><mo>&gt;</mo></math></span> solder joint diameter <span><math><mo>&gt;</mo></math></span> pad diameter. When the confidence level is 95%, solder joint height and solder joint diameter have a significant impact on the bending–torsion coupled stress of the WLCSP solder joint. The established PSO-BP neural network model for predicting the bending–torsion coupled stress of the WLCSP solder joint shows a maximum prediction error of 5.58% and an average error of 3.01%, demonstrating a good prediction accuracy for the stress.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"168 ","pages":"Article 115704"},"PeriodicalIF":1.6,"publicationDate":"2025-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143679907","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A NBTI self-healing circuit for a 12 nm CMOS high-gain amplifier","authors":"Jun-an Zhang ,&nbsp;Hao Chen ,&nbsp;Bo Liu ,&nbsp;De-ming Liu ,&nbsp;Tiehu Li ,&nbsp;Zhenghao Wang ,&nbsp;Maoguo Gong ,&nbsp;Qingwei Zhang","doi":"10.1016/j.microrel.2025.115684","DOIUrl":"10.1016/j.microrel.2025.115684","url":null,"abstract":"<div><div>This paper presents a self-healing circuit for a 12 nm CMOS high-gain amplifier which can mitigate the degeneration of NBTI effects. Based on an 12 nm P-FinFET NBTI equivalent circuit model, the degeneration of a high gain amplifier under NBTI stress has been simulated. The DC-gain will degrade from 107.5 dB to 80.6 dB after 10 years NBTI stress. A monitoring circuit has been utilized to indirectly detect the degeneration degree of the input transconductance and DC-gain, and then compensate it through a bias circuit and an input transistors replacement circuit. The simulation results show that the input transconductance and DC-gain of the amplifier with the self-healing circuit will decrease about 0.01uS and 0.09 dB at 25 °C after 10 years of NBTI stress. Further corner simulations show that the lifespan of the amplifier with the self-healing circuit will be &gt;20 years under NBTI stress.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"168 ","pages":"Article 115684"},"PeriodicalIF":1.6,"publicationDate":"2025-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143641641","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Failure analysis and reliability assessment of gold-plated fuzz buttons in elevated temperature","authors":"L. Zhang ,&nbsp;S. Wang ,&nbsp;X. Chen ,&nbsp;J. Guo ,&nbsp;L. Xu ,&nbsp;S. Ling ,&nbsp;X. Zhang","doi":"10.1016/j.microrel.2025.115687","DOIUrl":"10.1016/j.microrel.2025.115687","url":null,"abstract":"<div><div>Gold-plated electrical contacts are widely used in electrical and electronic systems to provide high-quality and reliable connections with minimal signal distortion or power loss. Many studies have been conducted on the failure analysis of gold-coated contacts in high-temperature environments. However, fuzz buttons, as one of the typical end-face contacts, have been less studied. This paper presents an experimental method to analyze the effects of elevated environmental temperatures on the performance of gold-plated fuzz buttons. The results show that the natural length and compression force of fuzz buttons were both shortened and reduced after the elevated temperature tests. Quantitative analysis of the microstructural changes in the test samples was conducted using characterization techniques such as optical microscopy, scanning electron microscopy (SEM), and focused ion beam (FIB) technology. The findings indicate that a large number of twin structures disappeared, the size of the precipitated phases increased, and the dislocation density decreased, leading to a reduced ability of fuzz buttons to resist plastic deformation and resulting in stress relaxation. Furthermore, a nonlinear Wiener stochastic process was used to model the degradation path of the test samples, while the generalized Eyring model was employed to describe the relationship between sample lifetimes and high temperatures. Using the maximum likelihood estimation (MLE) method, the model parameters were estimated from the integral statistics of all performance degradation data, successfully predicting the reliability of the fuzz buttons.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"168 ","pages":"Article 115687"},"PeriodicalIF":1.6,"publicationDate":"2025-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143641640","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Localization enhancement in quantitative thermal lock-in analysis using spatial phase evaluation","authors":"S. Brand ,&nbsp;M. Koegel ,&nbsp;C. Grosse ,&nbsp;F. Altmann ,&nbsp;H.T. Devarajulu ,&nbsp;F.M. Benito ,&nbsp;D. Goyal ,&nbsp;M. Pacheco","doi":"10.1016/j.microrel.2025.115690","DOIUrl":"10.1016/j.microrel.2025.115690","url":null,"abstract":"<div><div>The paper discusses enhancements in quantitative thermal lock-in analysis through spatial phase evaluation for defect localization in complex microelectronic components. It addresses the challenges of increasing integration density and diverse material composition in microelectronics. The primary focus of the present work is placed on improving sensitivity and spatial resolution of lock-in thermography for detection, imaging and the quantitative localization of thermally active electrical defects in all three spatial dimensions inside a device under test (DUT) to enable precise fault isolation. The paper describes the analysis of the lateral phase distribution in the presence of a thermal hot spot for reconstructing the thermal wave at the surface of the DUT and its back-tracing to its source inside the DUT. In the practical application this processing results in a reduction of thermal spreading effects and a precise localization in the lateral and axial (depth) directions. Experimental results demonstrate substantial improvements in precision and accuracy of defect localization and additionally a quantitative depth estimation. The paper highlights the potential application of the proposed method for non-destructive defect localization in 3D-integrated microelectronic devices.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"168 ","pages":"Article 115690"},"PeriodicalIF":1.6,"publicationDate":"2025-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143627843","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Fast and high-resolution X-ray nano tomography for failure analysis in advanced packaging","authors":"T. Dreier,&nbsp;D. Nilsson,&nbsp;J. Hållstedt","doi":"10.1016/j.microrel.2025.115694","DOIUrl":"10.1016/j.microrel.2025.115694","url":null,"abstract":"<div><div>Advanced packaging in electronics involves integrating semiconductor devices and sensors into a unified package, often employing complex 3D structures for enhanced performance and efficiency. As electronic components become smaller and more densely packed, conventional 2D X-ray radiography is not sufficient for inspection. Here we demonstrate the use of nano-CT with a high bandwidth memory (HBM) example illustrating the potential of fast detection of sub-micron voids and cracks in micro-bumps. Using a 30 s overview scan at 2.6 μm voxel size for navigation, a region is selected for a high-resolution scan with a voxel size of 600 nm to analyse 20 μm micro-bumps in between DRAM layers. Additionally, high-resolution laminography is performed showing the differences of the 2 techniques. The results show how high-resolution nano-CT can effectively be used for fast failure analysis and R&amp;D as well as important feedback to production ramp up and yield improvements of advanced packaging technologies.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"168 ","pages":"Article 115694"},"PeriodicalIF":1.6,"publicationDate":"2025-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143620393","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}