Microelectronics Reliability最新文献

{"title":"RHBD current-mode bandgap with SET isolation using PVT-independent sensors","authors":"Jaime Cardenas Chavez ,&nbsp;Ming Yan ,&nbsp;Tejinder Sandhu ,&nbsp;Adriana Noguera Cundar ,&nbsp;Kamal El-Sankary ,&nbsp;Li Chen","doi":"10.1016/j.microrel.2025.115865","DOIUrl":"10.1016/j.microrel.2025.115865","url":null,"abstract":"<div><div>This manuscript introduces a single event transient (SET) detecting circuit which is used in a current- mode bandgap reference circuit to reduce the magnitude of SET-induced voltage pulses at the bandgap output. Switches controlled by the SET detectors are inserted between the bandgap and output. When either a positive or negative voltage transient is detected at bandgap, one of the switches will be turned off to temporarily isolate the bandgap circuit from the output, thus preventing the SET glitches from propagating to the load devices. A capacitor at the output was used to keep the output voltage stable in case of an SET. Once the collected charge is dissipated and the bandgap reference circuit resumes normal operation, the switches will be turned on so that normal reference voltage will be reconnected to the output. This proposed structure was fabricated in a 28-nm FDSOI technology. Simulated results revealed a significant reduction in the SET magnitude. These results were also validated experimentally by using a 105 MeV proton radiation facility, and the SET magnitude at the bandgap reference output can be limited to 10 mV. The implemented SET detector is a versatile structure that can be applicable to DC circuits including LDOs, DC-DC converters and other types of bandgap reference circuits, enhancing their reliability when operating in high radiation environments.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"173 ","pages":"Article 115865"},"PeriodicalIF":1.6,"publicationDate":"2025-07-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144687579","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Degradation of high reliability lead-free solder joints under harsh thermal cycling test","authors":"Jeyun Yeom,&nbsp;Hans Rudolf Elsener,&nbsp;Tobias Burgdorf,&nbsp;Regina Bischoff,&nbsp;Lars P.H. Jeurgens,&nbsp;Jolanta Janczak-Rusch","doi":"10.1016/j.microrel.2025.115868","DOIUrl":"10.1016/j.microrel.2025.115868","url":null,"abstract":"<div><div>In this study, the degradation behavior of solder joints made using pre-selected, highly reliable lead-free solder alloys was investigated under thermal cycling conditions. Innolot (Sn 3.8Ag 0.7Cu 3.0Bi 1.5Sb 0.2Ni) and SB6NX (Sn 3.5Ag 0.8Cu 0.5Bi 6.0In) as well as reference solders: SAC305 (Sn 3Ag 0.5Cu) and SnPb solder were selected for this study, and solder joints of R1812 ceramic chip resistors on a printed circuit board were prepared by reflow soldering. The mechanical and microstructural degradation of the solder joints was investigated after thermal cycles (3000 cycles) from −55 to +100 °C with extended dwell times of 30 min. The crack length and void area were determined by optical microscopy from joint cross-sections and correlated with maximum shear force degradation obtained in mechanical shear tests. The results of the study support the development of highly reliable surface-mounted components for aerospace applications.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"173 ","pages":"Article 115868"},"PeriodicalIF":1.6,"publicationDate":"2025-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144680518","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Towards Extended Hückel model-based reliability performance enhancement of gate stack graphene nanoribbon field effect transistor","authors":"Anshul ,&nbsp;Rishu Chaujar","doi":"10.1016/j.microrel.2025.115869","DOIUrl":"10.1016/j.microrel.2025.115869","url":null,"abstract":"<div><div>This paper examines the performance and reliability of the gate stack graphene nanoribbon field effect transistor (GS-GNRFET) with the varied number of carbon atoms along the graphene nanoribbon width (n) in the channel material. Initially, the Extended Hückel (EH) model approach is used to calculate bandgap and density of states (DOS) and transmission spectrum (TS) of bulk configured armchair graphene nanoribbon (ACGNR) with <em>n</em> = 4 and 7. Then, these ACGNR (<em>n</em> = 4 and 7) are used in channel material to analyze the performance of proposed devices, namely the A4 device (GS-GNRFET with ACGNR (n = 4) in channel material) and the A7 device (GS-GNRFET with ACGNR (<em>n</em> = 7) in channel material. The result shows that the bandgap value is lower in ACGNR (<em>n</em> = 7) with a value of 1.09 eV compared with ACGNR (<em>n</em> = 4). Also, the ACGNR (n = 7) shows improved DOS and TS. Also, the EH model shows good agreement with DFT methods, validating its reliability and efficiency for modeling ACGNR-based low-power devices. The variation in the value of ‘n’ from 4 to 7 enhances the on current (I_on, 481 times ↑), decreases off current (I_off, 99.92 % ↓), improves the switching ratio (SR), reduces threshold voltage (V_th, 27 % ↓), reduces drain induced barrier lowering (DIBL, 16 % ↓) in A7 device as compared with A4 device. Also, the higher device efficiency (DE) value for the A7 device indicates lower voltage for significant current modulation, making it highly reliable for low-power applications. Moreover, the A7 device exhibits better transport properties, namely the Device Density of States (DDOS), projected density of states (PLDOS), transmission coefficient T (E), transmission pathways (TP), and Electron Difference Density (EDD). These parameters provide a unique way to evaluate device performance in terms of resonance peaks and electrical structure. The DDOS and contour plot of PLDOS analysis indicate a higher electron occupation, leading to better performance of the A7 device. The T(E) and TP analysis confirms stronger conductance, faster switching, and lower power consumption due to robust electron tunneling in the A7 device compared to the A4 device. The EDD analysis reveals more effective gate control with reduced electron density variations, resulting in improved switching behavior in the A7 device. Additionally, the A7 device has a very low value of static power (1.58 × 10⁻¹³ watt) compared to previous devices available in the literature. The improved findings regarding DE, SR, V_th (27 % ↓), DIBL (16 % ↓), TP, EDD, DDOS, and static power analysis of the A7 device make it suitable for applications in low-power areas like biomedical devices, sensors, and signal amplification areas. Owing to enhanced findings, this research article highlights the A7 device as a reliable and suitable candidate for low–power applications.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"173 ","pages":"Article 115869"},"PeriodicalIF":1.6,"publicationDate":"2025-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144680519","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Grain morphology effect on interfacial void closure in Cu–Cu bonding for advanced semiconductor packaging","authors":"Han Jiang ,&nbsp;Yaohua Xu ,&nbsp;Saranarayanan Ramachandran ,&nbsp;Shuibao Liang","doi":"10.1016/j.microrel.2025.115864","DOIUrl":"10.1016/j.microrel.2025.115864","url":null,"abstract":"<div><div>Driven by the demands of increased integration density and heterogeneous integration in the post-Moore era, Cu–Cu direct bonding has become a critical technology for enabling fine-pitch interconnects in advanced packaging. However, achieving reliable bonds remains challenging due to the existence of interfacial voids and the complex grain morphology that develops during the bonding process. In this work, a phase field model is developed and employed to investigate the effect of grain morphology on the kinetics of interfacial void closure during the Cu–Cu bonding process. Representative configurations are constructed by varying grain size and morphology in both bonded Cu pads to simulate realistic microstructural scenario. The results show that configurations with a larger number of smaller grains on both sides of the bonding structures promote faster void closure and achieve more uniform interfacial densification. This behavior is attributed to the increased presence of grain boundaries, which serve as enhanced diffusion pathways across the interface. Furthermore, the evolution of stress fields during bonding indicates that stress becomes more evenly distributed as voids close. The stress triaxiality near void regions remains below −1 throughout the closure process, demonstrating a favorable hydrostatic compressive state for void elimination. These findings provide further fundamental understanding of the mechanisms of void closure and may offer valuable guidance for improving the reliability of Cu–Cu bonding in advanced packaging applications.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"173 ","pages":"Article 115864"},"PeriodicalIF":1.6,"publicationDate":"2025-07-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144670372","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"C-SMART: A preprocessor for neural network performance and reliability under radiation","authors":"Anuj Justus Rajappa ,&nbsp;Philippe Reiter ,&nbsp;Paolo Rech ,&nbsp;Siegfried Mercelis ,&nbsp;Jeroen Famaey","doi":"10.1016/j.microrel.2025.115859","DOIUrl":"10.1016/j.microrel.2025.115859","url":null,"abstract":"<div><div>Edge AI brings the benefits of AI, such as neural networks for computer vision analysis, to low-power edge computing platforms. However, application and resource constraints leading to inadequate protection can make edge devices vulnerable to environmental factors, such as cosmic rays that continually shower on Earth. These factors can cause bit-flips that affect the reliability of the neural network inferences computed using these edge devices. To address this issue, we developed the Conditional-SMART (C-SMART) preprocessor designed to answer the question ‘When to use SMART?’, for obtaining both reliability and performance benefits. SMART is a reliability improvement technique introduced in our previous work, which involves skipping the multiply–accumulate operations performed on the zero-valued inputs to the layers of the neural network. We demonstrated C-SMART with a commercial bare-metal system containing an ARM microprocessor by exposing the system to real-world, atmospheric-like neutron radiation using the ChipIr facility in Oxfordshire, UK. We also conducted timing and energy measurements for performance analysis. Our experiments with C-SMART for inference with a neural network revealed a reliability boost against soft errors by more than 26% while improving performance by more than 35%. We foresee these benefits in various COTS devices by integrating C-SMART with compilers and neural network generators.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"173 ","pages":"Article 115859"},"PeriodicalIF":1.6,"publicationDate":"2025-07-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144670373","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Microstructure and diffusion mechanisms in nano-Cu sintered joints during aging: Effects of joint size, porosity, and aging atmosphere","authors":"Shuaiqi Wang ,&nbsp;Guisheng Zou ,&nbsp;Jinpeng Huo ,&nbsp;Rongbao Du ,&nbsp;Lei Liu","doi":"10.1016/j.microrel.2025.115863","DOIUrl":"10.1016/j.microrel.2025.115863","url":null,"abstract":"<div><div>Sintering bonding by nano-Cu is receiving great interests in die bonding of both power electronics and integrated circuits (IC) due to its low cost compared with nano-Ag/Au. However, oxidation of sintered Cu joints, having nanoporous microstructure, remains a concern for the reliability. This study systematically studied the effects of joint size, porosity, and aging atmosphere on the oxidation mechanisms of sintered Cu. An abnormal void growth was observed for the first time in low-porosity (4.27 %) Cu bumps (60 μm diameter) during high-temperature ambient aging, which was not observed in large-area sintered Cu (3 × 3 mm²). A hypothesis was proposed based on diffusion driven by oxidization. It indicated that the microscale bump size caused high chemical potential gradient between the nanoporous Cu and the Cu₂O surface oxide, leading to a massive Cu atom diffusion through grain boundaries. Vacuum aging showed Ostwald ripening in bump center and vacancies in bump edge diffusing out of bumps, which was totally different from ambient condition. For high-porosity (17.12 %) Cu bumps, oxide was directly formed inside voids due to the penetration of O₂ through the connected voids. The findings revealed the oxidation mechanisms in microscale sintered Cu interconnects, which was essential for the advanced packaging of both IC and power electronics.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"173 ","pages":"Article 115863"},"PeriodicalIF":1.6,"publicationDate":"2025-07-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144623338","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Monitoring method for bond wire aging in IGBT modules based on gate voltage ringing frequency","authors":"Mingxing Du,&nbsp;Jinlin Zhou,&nbsp;Jianxiong Yang,&nbsp;Haiqing Gu","doi":"10.1016/j.microrel.2025.115842","DOIUrl":"10.1016/j.microrel.2025.115842","url":null,"abstract":"<div><div>Aging monitoring of IGBT modules in power converters not only effectively improves system operational reliability, but also significantly reduces maintenance costs. This paper proposes a novel method for monitoring bond wire aging in IGBT modules based on the ringing frequency characteristics of the turn-on gate voltage. Initially, based on the turn-on characteristics of IGBT module and equivalent circuit model, this paper systematically analyzes the reasons for turn-on gate voltage ringing, and points out that the ringing frequency can be used as an indicator to reflect the aging of bond wires. Then, experimental validation of the proposed monitoring strategy was conducted on a buck converter testbed, with comprehensive analysis of operational impacts induced by DC-link voltage variations, gate resistance selection, and junction temperature fluctuations. Finally, this work presents a bond wire degradation monitoring scheme based on gate ringing frequency threshold analysis. The experimental results show that the voltage ringing frequency at the gate Miller plateau of the IGBT module decreases with the aging of the bond wires. The method is non-invasive, and achieves decoupling of the junction temperature using a set threshold.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"173 ","pages":"Article 115842"},"PeriodicalIF":1.6,"publicationDate":"2025-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144588048","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Investigation of DFF cells SEU effect for 14 nm bulk silicon FinFET technology irradiated by heavy ions","authors":"Hai-song Li,&nbsp;Bin Wang,&nbsp;Yi-hu Jiang,&nbsp;Bo Yang,&nbsp;Li-jun Gao,&nbsp;Hong-ju Yue","doi":"10.1016/j.microrel.2025.115857","DOIUrl":"10.1016/j.microrel.2025.115857","url":null,"abstract":"<div><div>A single-event effect test circuit was implemented in 14 nm bulk silicon FinFET technology, incorporating five flip-flop configurations: a standard D-type flip-flop (DFF), a logic depth DFF (LOG-DFF), a compact triple modular redundancy DFF (TMR-DFF), an interleaved TMR-DFF (INTER-TMR-DFF), and a dual interlocked storage cell DFF (DICE-DFF). Radiation testing was performed using heavy ion accelerator facilities with four ion species (F, Cl, Ge, and Ta). Experimental results demonstrated that the INTER-TMR-DFF achieved optimal single-event upset (SEU) resistance, although with area overhead, higher propagation delay, and greater power consumption compared to the baseline DFF. Both TMR-DFF and DICE-DFF exhibited effective radiation hardening at low linear energy transfer (LET) values, but showed degraded performance at higher LET levels. Notably, the DICE-DFF displayed a 40.7% increase in saturation cross-section relative to the standard DFF at LET values equal to 83.8 MeV·cm²/mg. This performance degradation under high-LET conditions correlates with technology scaling effects in advanced nanoscale processes: reduced feature sizes and increased transistor density exacerbate charge sharing phenomena. These parasitic charge redistribution effects fundamentally influence SEU mechanisms, compromising the radiation hardening benefits of both TMR-DFF and DICE-DFF architectures. Comprehensive comparative analysis evaluated all five flip-flop designs across multiple metrics: area occupation, propagation delay, power consumption, transistor count, and SEU resistance performance.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"173 ","pages":"Article 115857"},"PeriodicalIF":1.6,"publicationDate":"2025-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144588025","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A physics-based electromigration model for advanced interconnects","authors":"Wangyong Chen ,&nbsp;Binyu Yin ,&nbsp;Linlin Cai ,&nbsp;Yi Wan","doi":"10.1016/j.microrel.2025.115862","DOIUrl":"10.1016/j.microrel.2025.115862","url":null,"abstract":"<div><div>Electromigration (EM) prediction is becoming more significant for advanced back-end-of-line. In this work, we propose a physics-based EM model to achieve the high-accuracy and high-efficiency assessment for time-to-failure (TTF). The void evolution is considered during the EM degradation which includes the resistivity model, temperature model and activation energy correction model. The proposed model enables to depict the resistance degradation curves over time which agrees well with the experiment data. The influence of dimension, grain size, temperature, and current density on TTF of interconnects can be analyzed by the model, showing a potential application for fast EM prediction in high-density integration, especially for the advanced interconnects.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"173 ","pages":"Article 115862"},"PeriodicalIF":1.6,"publicationDate":"2025-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144588049","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Thermal-mechanical coupling analysis of Micro-LED bonding based on copper pillar bump","authors":"Hao Fu ,&nbsp;Zhu Yang ,&nbsp;Xinhui Meng ,&nbsp;Hong Fan ,&nbsp;Xiuzhen Lu ,&nbsp;Luqiao Yin ,&nbsp;Jianhua Zhang","doi":"10.1016/j.microrel.2025.115858","DOIUrl":"10.1016/j.microrel.2025.115858","url":null,"abstract":"<div><div>With the rapid development of automotive electronics and near-eye display, more stringent requirements are put forward for the heterogeneous integration technology of Micro-LED, especially in interconnect structure. The copper pillar bumps with better electrical conductivity, thermal conductivity and mechanical properties can meet the packaging requirements of higher density and smaller pitch for application of Micro-LED array. The application of copper bumps in small pitch interconnect structures have been discussed in many studies while the application of copper pillar bumps in Micro-LED interconnection is currently rare. An equivalent model method of simulation combined with sub-model technique is proposed in this paper. The feasibility and accuracy of the equivalent method was investigated. Simulation of Micro-LED bonding process based on copper pillar bumps with equivalent method was performed. Low-temperature (40 °C) and high-temperature (280 °C) were applied to the upper bonding interface respectively to investigate the influence of bonding temperature on the stress of the device. Micro-LED bonding experiment was performed to validate the results of bonding simulation.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"173 ","pages":"Article 115858"},"PeriodicalIF":1.6,"publicationDate":"2025-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144580279","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}