Gate oxide lifetime modeling of vertical SiC-MOS under accelerated reverse bias (ARB)

Abstract

Robustness under reverse bias is a pivotal reliability metric for MOS based SiC power devices. Accelerated reverse bias (ARB) stressing, typically involving multiple V_DS stress values beyond the rated drain bias but below the avalanche voltage, is deemed optimal for assessing the device lifetime in the blocking mode. However, generating adequate failure statistics within a feasible timeframe during ARB tests can be arduous, particularly for devices engineered to undergo avalanche breakdown at lower drain voltages than those necessary to induce gate oxide wear-out failures within a reasonable time. This paper presents an innovative, streamlined alternative modeling approach, where qualification-like high temperature reverse bias (HTRB) or ARB test at a singular stress voltage for a suitable stress duration can be utilized to predict gate oxide lifetimes under blocking conditions, obviating the need for any prolonged testing.