Microelectronics Reliability最新文献

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Understanding improved pitting corrosion resistance under high temperature application leading to a newly developed palladium coated copper wire
IF 1.6 4区 工程技术
Microelectronics Reliability Pub Date : 2025-03-14 DOI: 10.1016/j.microrel.2025.115696
Noritoshi Araki , Motoki Eto , Shinya Azuma , Robert Klengel , Sandy Klengel , Takashi Yamada
{"title":"Understanding improved pitting corrosion resistance under high temperature application leading to a newly developed palladium coated copper wire","authors":"Noritoshi Araki ,&nbsp;Motoki Eto ,&nbsp;Shinya Azuma ,&nbsp;Robert Klengel ,&nbsp;Sandy Klengel ,&nbsp;Takashi Yamada","doi":"10.1016/j.microrel.2025.115696","DOIUrl":"10.1016/j.microrel.2025.115696","url":null,"abstract":"<div><div>As the application of palladium coated copper (PCC) wire in automotive semiconductor sector increases, its reliability under high temperature is a topic of frequent discussion ever in the industry. One of the reliability concerns for PCC wire is pitting corrosion at ball bond and wedge bond contact areas. Pitting corrosion is a unique issue for PCC wire that could become prominent at high temperature (≥175 °C) in a sulfur containing environment. To overcome this issue, we developed a new PCC wire that has exceptionally high resistance against pitting corrosion by introducing the corrosion inhibitor inside the Pd coating layer. This paper discusses the reliability performance of the new wire, including the results of high temperature storage life test at elevated temperatures (up to 250 °C) and the investigation of the improving mechanism by high resolution microstructural analysis.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"168 ","pages":"Article 115696"},"PeriodicalIF":1.6,"publicationDate":"2025-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143620392","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Current balancing of parallel-connected silicon carbide (SiC) MOSFET power devices using peak detection via PCB sensors
IF 1.6 4区 工程技术
Microelectronics Reliability Pub Date : 2025-03-14 DOI: 10.1016/j.microrel.2025.115688
Ravi Nath Tripathi , Ichiro Omura
{"title":"Current balancing of parallel-connected silicon carbide (SiC) MOSFET power devices using peak detection via PCB sensors","authors":"Ravi Nath Tripathi ,&nbsp;Ichiro Omura","doi":"10.1016/j.microrel.2025.115688","DOIUrl":"10.1016/j.microrel.2025.115688","url":null,"abstract":"<div><div>The parallelling of power semiconductor devices is essential for desired current ratings and the system is prone to the current unbalancing due to parameter variations. SiC devices with significant variable threshold voltage due to manufacturing yield and temperature distribution have a consequential possibility of dynamic current unbalancing. This paper presents the peak detection-based current balancing of parallel-connected SiC devices to minimize the turn-on and turn-off current unbalancing. PCB current sensors are used for the measurement and feedback of the signal for this peak detection-based current balancing mechanism.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"168 ","pages":"Article 115688"},"PeriodicalIF":1.6,"publicationDate":"2025-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143620394","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Optimization of the drain-side configuration in ESD-protection SCR-LDMOS for high holding-voltage applications
IF 1.6 4区 工程技术
Microelectronics Reliability Pub Date : 2025-03-13 DOI: 10.1016/j.microrel.2025.115664
L. Zunarelli , S. Rotorato , E. Gnani , S. Reggiani , R. Sankaralingam , M. Dissegna , G. Boselli
{"title":"Optimization of the drain-side configuration in ESD-protection SCR-LDMOS for high holding-voltage applications","authors":"L. Zunarelli ,&nbsp;S. Rotorato ,&nbsp;E. Gnani ,&nbsp;S. Reggiani ,&nbsp;R. Sankaralingam ,&nbsp;M. Dissegna ,&nbsp;G. Boselli","doi":"10.1016/j.microrel.2025.115664","DOIUrl":"10.1016/j.microrel.2025.115664","url":null,"abstract":"<div><div>A conventional silicon-controlled rectifier integrated into a laterally diffused MOSFET (SCR-LDMOS) is studied through 2D TCAD simulations in order to obtain the maximum holding voltage without increasing the area consumption or degrading the power-to-failure robustness. A reference device with 150V trigger voltage, 3V holding voltage and an approximate thermal breakdown at 30 mA/<span><math><mrow><mi>μ</mi><mi>m</mi></mrow></math></span> is adopted. Different configurations of the drain-side region are compared, with the best solution showing a 5x improvement on the holding condition without a significant variation on the other figures of merit.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"168 ","pages":"Article 115664"},"PeriodicalIF":1.6,"publicationDate":"2025-03-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143611533","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Toward understanding the impacts of dynamic Ron on the efficiency in GaN-based AC-DC flyback converter
IF 1.6 4区 工程技术
Microelectronics Reliability Pub Date : 2025-03-13 DOI: 10.1016/j.microrel.2025.115692
Chih-Yao Chang , Hsing-Hua Hsieh , Cheng-Tsung Ho , Tsung-Hsiu Wu , Ming-Chang Tsou , Chih-Wen Hsiung , Ming-Nan Chuang , Tian-Li Wu
{"title":"Toward understanding the impacts of dynamic Ron on the efficiency in GaN-based AC-DC flyback converter","authors":"Chih-Yao Chang ,&nbsp;Hsing-Hua Hsieh ,&nbsp;Cheng-Tsung Ho ,&nbsp;Tsung-Hsiu Wu ,&nbsp;Ming-Chang Tsou ,&nbsp;Chih-Wen Hsiung ,&nbsp;Ming-Nan Chuang ,&nbsp;Tian-Li Wu","doi":"10.1016/j.microrel.2025.115692","DOIUrl":"10.1016/j.microrel.2025.115692","url":null,"abstract":"<div><div>In this work, the dynamic R<sub>on</sub> effects on the efficiency and conduction loss in GaN-based AC-DC flyback converter was evaluated. Compared to the static on-resistance, the dynamic R<sub>on</sub> of single p-GaN gate HEMT shows a significant increase under hard switching via a double pulse test. In addition, the dynamic R<sub>on</sub> shows a further increase when the pulse time increases, indicating that the real dynamic R<sub>on</sub> in the continuous switching system may not be totally revealed by a single pulse test. On the other hand, the combo IC operated in the system indicates that the substantial increase of dynamic R<sub>on</sub> (&gt;188 % increases) in p-GaN gate HEMTs have the limited impacts on 1) the conduction loss (&lt;9 %) in p-GaN gate HEMTs and 2) the system efficiency (&gt;92 %) in GaN-based AC-DC flyback converter.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"168 ","pages":"Article 115692"},"PeriodicalIF":1.6,"publicationDate":"2025-03-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143611534","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Solder joint reliability - glass core substrate versus organic core substrate
IF 1.6 4区 工程技术
Microelectronics Reliability Pub Date : 2025-03-13 DOI: 10.1016/j.microrel.2025.115701
John H. Lau, Ning Liu, Mike Ma, Tzyy-Jang Tseng
{"title":"Solder joint reliability - glass core substrate versus organic core substrate","authors":"John H. Lau,&nbsp;Ning Liu,&nbsp;Mike Ma,&nbsp;Tzyy-Jang Tseng","doi":"10.1016/j.microrel.2025.115701","DOIUrl":"10.1016/j.microrel.2025.115701","url":null,"abstract":"<div><div>The thermal-fatigue reliability of flip chip micro solder joints on glass core build-up package substrate and C4 (controlled collapse chip connection) or BGA (ball grid array) solder joints on printed circuit board (PCB) is investigated. Emphasis is placed on the deformation of the structure and the accumulated inelastic strain at the critical locations of the micro and C4 solder joints. Some recommendations are also provided.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"168 ","pages":"Article 115701"},"PeriodicalIF":1.6,"publicationDate":"2025-03-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143611577","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Heterogeneity-induced thermal mismatch in BGA interconnects: Insights from mechanical-thermal finite element modeling
IF 1.6 4区 工程技术
Microelectronics Reliability Pub Date : 2025-03-13 DOI: 10.1016/j.microrel.2025.115703
Liu Chu , Jiajia Shi , Xu Long
{"title":"Heterogeneity-induced thermal mismatch in BGA interconnects: Insights from mechanical-thermal finite element modeling","authors":"Liu Chu ,&nbsp;Jiajia Shi ,&nbsp;Xu Long","doi":"10.1016/j.microrel.2025.115703","DOIUrl":"10.1016/j.microrel.2025.115703","url":null,"abstract":"<div><div>Thermal expansion mismatch due to the heterogeneous materials in ball grid array (BGA) interconnects of electronic packaging structures often results in localized strain concentration, leading to creep, fatigue, or potential failure. Modeling BGA solder balls independently, without considering connected and contacting components, fails to comprehensively monitor the system's state. In this study, a mechanical-thermal finite element model (FEM) comprising solder balls, a printed circuit board (PCB), chips, and underfill is systematically developed. Time-dependent nonlinear analysis is performed on Sn-Ag-Cu (SAC) solder-bumped flip chips in PCB assemblies subjected to thermal cycling. Thermal gradient contours illustrate inhomogeneous in-plane and vertical thermal diffusion within the components. The Garofalo model is employed in the FEM to simulate visco-plastic behavior. The results reveal significant thermal gradient mismatches due to the intrinsic properties of heterogeneous components, which are often overlooked in independent material studies. Additionally, the central region of the BGA exhibits more pronounced creep strain compared to edge solder balls. These findings provide valuable insights for optimizing BGA geometric design. This work also offers a comprehensive framework to quantify thermal mismatches and simulate creep behavior under thermal cycling based on FEM.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"168 ","pages":"Article 115703"},"PeriodicalIF":1.6,"publicationDate":"2025-03-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143611535","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Fast reverse engineering of chips using lasers, Focused Ion Beams, and confocal and scanning electron microscopy
IF 1.6 4区 工程技术
Microelectronics Reliability Pub Date : 2025-03-13 DOI: 10.1016/j.microrel.2025.115697
Matthew Maniscalco , Hongbin Choi , Adrian Phoulady , Alexander Blagojevic , Toni Moore , Mohammad Taghi Mohammadi Anaei , Parisa Mahyari , Nicholas May , Sina Shahbazmohamadi , Pouya Tavousi
{"title":"Fast reverse engineering of chips using lasers, Focused Ion Beams, and confocal and scanning electron microscopy","authors":"Matthew Maniscalco ,&nbsp;Hongbin Choi ,&nbsp;Adrian Phoulady ,&nbsp;Alexander Blagojevic ,&nbsp;Toni Moore ,&nbsp;Mohammad Taghi Mohammadi Anaei ,&nbsp;Parisa Mahyari ,&nbsp;Nicholas May ,&nbsp;Sina Shahbazmohamadi ,&nbsp;Pouya Tavousi","doi":"10.1016/j.microrel.2025.115697","DOIUrl":"10.1016/j.microrel.2025.115697","url":null,"abstract":"<div><div>This study presents novel methodologies for the reverse engineering and failure analysis of semiconductor devices, focusing on overcoming the limitations of traditional Focused Ion Beam (FIB) techniques. Central to our approach are two innovative methods: high-precision volumetric imaging via 3D reconstruction from laser-delayered surface profiles and a hybrid delayering technique combining ultrashort pulsed laser removal with FIB polishing. These methods address the challenges of slow delayering processes and uneven layer exposure by enabling faster material removal, minimizing thermal damage, and ensuring precise surface preparation for imaging. The effectiveness of these approaches is demonstrated through detailed imaging of embedded chip circuitry in two advanced technology chips. Our findings highlight significant advancements in the speed, accuracy, and efficiency of semiconductor device analysis, promising to streamline reverse engineering efforts and enhance failure analysis processes.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"168 ","pages":"Article 115697"},"PeriodicalIF":1.6,"publicationDate":"2025-03-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143611536","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Resonant fatigue test performance of battery pack connections using wire bonding
IF 1.6 4区 工程技术
Microelectronics Reliability Pub Date : 2025-03-13 DOI: 10.1016/j.microrel.2025.115705
Xing Wei, Junko Takahashi, Kohei Tatsumi
{"title":"Resonant fatigue test performance of battery pack connections using wire bonding","authors":"Xing Wei,&nbsp;Junko Takahashi,&nbsp;Kohei Tatsumi","doi":"10.1016/j.microrel.2025.115705","DOIUrl":"10.1016/j.microrel.2025.115705","url":null,"abstract":"<div><div>Reliable interconnections in electric vehicle (EV) battery packs are critical for performance and safety. Wire bonding enables joining dissimilar materials with minimal heat input but suffers from limited joint strength under vibrational stress. Existing testing standards focus on entire battery packs, lacking direct assessment of bonding wire reliability. This study proposes a novel resonance-based fatigue testing method to evaluate the fatigue resistance of aluminum (Al), silver (Ag), and copper (Cu) bonding wires (200 μm in diameter). Results show that Ag and Cu wires significantly outperform Al wire under high-frequency vibration. At 1 mm amplitude, Al wire failed immediately, while Ag and Cu wires survived ∼200,000 and ∼ 300,000 cycles, respectively. In a 10-million-cycle test at 0.6 mm amplitude, Ag and Cu wires exhibited excellent fatigue resistance, whereas Al wire fractured before 60,000 cycles. SEM analysis revealed severe cracking in Al wire after 30,000 cycles, while Ag and Cu wires showed only minor cracks after 10 million cycles. Although Cu wire demonstrated the highest fatigue resistance, its higher bonding temperature is a limitation, making Ag wire a promising alternative. The proposed method offers an effective approach to assessing bonding wire reliability, aiding material selection for enhanced EV battery durability.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"168 ","pages":"Article 115705"},"PeriodicalIF":1.6,"publicationDate":"2025-03-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143620391","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Electronics authentication using electrical measurements and machine learning
IF 1.6 4区 工程技术
Microelectronics Reliability Pub Date : 2025-03-12 DOI: 10.1016/j.microrel.2025.115652
S. Carta , A. Urru , M. Musa , P. Andronico , G. Mura
{"title":"Electronics authentication using electrical measurements and machine learning","authors":"S. Carta ,&nbsp;A. Urru ,&nbsp;M. Musa ,&nbsp;P. Andronico ,&nbsp;G. Mura","doi":"10.1016/j.microrel.2025.115652","DOIUrl":"10.1016/j.microrel.2025.115652","url":null,"abstract":"<div><div>The problem of counterfeiting in electronics is not recent but still critical today. Identifying counterfeit devices can be a complex task since not all suspicious items are necessarily inauthentic. The paper deals with the non-destructive detection of counterfeiting in electronics by using only electrical measurements. This approach paves the way for machine learning classification-assisted counterfeit detection through electrical measurements. Physical de-processing provides the final confirmation.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"168 ","pages":"Article 115652"},"PeriodicalIF":1.6,"publicationDate":"2025-03-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143611529","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
RRAMulator: An efficient FPGA-based emulator for RRAM crossbar with device variability and energy consumption evaluation
IF 1.6 4区 工程技术
Microelectronics Reliability Pub Date : 2025-03-12 DOI: 10.1016/j.microrel.2025.115630
Jianan Wen , Fabian Luis Vargas , Fukun Zhu , Daniel Reiser , Andrea Baroni , Markus Fritscher , Eduardo Perez , Marc Reichenbach , Christian Wenger , Milos Krstic
{"title":"RRAMulator: An efficient FPGA-based emulator for RRAM crossbar with device variability and energy consumption evaluation","authors":"Jianan Wen ,&nbsp;Fabian Luis Vargas ,&nbsp;Fukun Zhu ,&nbsp;Daniel Reiser ,&nbsp;Andrea Baroni ,&nbsp;Markus Fritscher ,&nbsp;Eduardo Perez ,&nbsp;Marc Reichenbach ,&nbsp;Christian Wenger ,&nbsp;Milos Krstic","doi":"10.1016/j.microrel.2025.115630","DOIUrl":"10.1016/j.microrel.2025.115630","url":null,"abstract":"<div><div>The in-memory computing (IMC) systems based on emerging technologies have gained significant attention due to their potential to enhance performance and energy efficiency by minimizing data movement between memory and processing unit, which is especially beneficial for data-intensive applications. Designing and evaluating systems utilizing emerging memory technologies, such as resistive RAM (RRAM), poses considerable challenges due to the limited support from electronics design automation (EDA) tools for rapid development and design space exploration. Additionally, incorporating technology-dependent variability into system-level simulations is critical to accurately assess the impact on system reliability and performance. To bridge this gap, we propose RRAMulator, a field-programmable gate array (FPGA) based hardware emulator for RRAM crossbar array. To avoid the complex device models capturing the nonlinear current–voltage (IV) relationships that degrade emulation speed and increase hardware utilization, we propose a device and variability modeling approach based on device measurements. We deploy look-up tables (LUTs) for device modeling and use the multivariate kernel density estimation (KDE) method to augment existing data, extending data variety and avoiding repetitive data usage. The proposed emulator achieves cycle-accurate, real-time emulations and provides information such as latency and energy consumption for matrix mapping and vector–matrix multiplications (VMMs). Experimental results show a significant reduction in emulation time compared to conventional behavioral simulations. Additionally, an RRAM-based discrete Fourier transform (DFT) accelerator is analyzed as a case study featuring a range of in-depth system assessments.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"168 ","pages":"Article 115630"},"PeriodicalIF":1.6,"publicationDate":"2025-03-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143611531","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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