Microelectronics Reliability最新文献_第6页

Degradation prediction of IGBT module based on CNN-LSTM network

IF 1.6 4区工程技术

Microelectronics Reliability Pub Date : 2025-03-07 DOI: 10.1016/j.microrel.2025.115639

Liangjun Bai, Meng Huang, Shangzhi Pan, Kang Li, Xiaoming Zha

{"title":"Degradation prediction of IGBT module based on CNN-LSTM network","authors":"Liangjun Bai, Meng Huang, Shangzhi Pan, Kang Li, Xiaoming Zha","doi":"10.1016/j.microrel.2025.115639","DOIUrl":"10.1016/j.microrel.2025.115639","url":null,"abstract":"<div><div>The reliability of insulated gate bipolar transistor (IGBT) directly affects the safe and stable operation of power electronic system. Based on the IGBT accelerated aging open data set provided by NASA PCoE, the peak collector-emitter voltage during IGBT shutdown is selected as the failure characteristic parameter. Convolutional neural network and long short-term memory network (CNN-LSTM) model is used to predict IGBT failure precursor parameters and estimate the degradation behavior of IGBT modules in this paper. The sliding window method is employed to construct input and output data. When the window width is 3, the prediction model works best. By running the proposed model many times, the average values of MAPE, MAE, MSE and RMSE of the CNN-LSTM network proposed in this paper are 0.0038,0.0468,0.0059,0.0600, which have higher accuracy than other networks. At the same time, the four indicators of the CNN-LSTM model are the most stable and the prediction credibility is higher through the box plot analysis. This prediction method provides a new idea for IGBT degradation behavior prediction.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"168 ","pages":"Article 115639"},"PeriodicalIF":1.6,"publicationDate":"2025-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143562348","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Investigation of humidity protection behavior of protective coatings on PCB with components

IF 1.6 4区工程技术

Microelectronics Reliability Pub Date : 2025-03-06 DOI: 10.1016/j.microrel.2025.115672

Ioannis Mantis , Anish Rao Lakkaraju , Mike Bixenman , Kapil Kumar Gupta , Rajan Ambat

{"title":"Investigation of humidity protection behavior of protective coatings on PCB with components","authors":"Ioannis Mantis , Anish Rao Lakkaraju , Mike Bixenman , Kapil Kumar Gupta , Rajan Ambat","doi":"10.1016/j.microrel.2025.115672","DOIUrl":"10.1016/j.microrel.2025.115672","url":null,"abstract":"<div><div>In this work, humidity performance of two types of protective coatings was investigated on a PCB with typical components with the aim of understanding synergistic effect of coating/process and board design. Coatings are 2-component Polyurethane (PU, mixture of Ether and Ester polyols) and ultra-thin Plasma enhanced chemical vapor deposition (PECVD) coating. Test PCB used for testing consisted of components such as a Quad flat no‑lead package (QFN), Ball grid array (BGA), and Pin connector. The performance of coated PCB was evaluated in terms of process-induced no-clean flux residues introduced during reflow and wave soldering of components. The test profile used was constant humidity (95 %) condition with temperature cycling (40°C–65°C). Moisture permeation through the coatings and its effects on component performance was evaluated using electrochemical AC impedance and subsequent DC potentiostatic measurement under climatic exposure. Coating-PCB-Components interfaces were analyzed using Scanning electron microscopy (SEM) and Energy dispersive spectroscopy (EDS) before and after testing. The study revealed that the PCBA cleanliness after a soldering process is a major factor determining the coating performance, component geometrical shape and standoff height affected uniformity of coating and under-filling affecting humidity performance.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"168 ","pages":"Article 115672"},"PeriodicalIF":1.6,"publicationDate":"2025-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143561561","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

New statistical analysis methodology to forecast the memory cell behavior before reliability test

IF 1.6 4区工程技术

Microelectronics Reliability Pub Date : 2025-03-06 DOI: 10.1016/j.microrel.2025.115659

S. Perrin , V. Della Marca , T. Kempf , M. Bocquet , L. Welter , J.M. Moragues , A. Regnier , J.M. Portal

引用次数: 0

Lifetime prediction for power modules in wind-energy converters based on temperature variations in a large area substrate solder connection

IF 1.6 4区工程技术

Microelectronics Reliability Pub Date : 2025-03-06 DOI: 10.1016/j.microrel.2025.115665

Nils Zöllner , Oliver Schilling , David Übelacker , Tobias Heise , Hans-Günter Eckel , University of Rostock

{"title":"Lifetime prediction for power modules in wind-energy converters based on temperature variations in a large area substrate solder connection","authors":"Nils Zöllner , Oliver Schilling , David Übelacker , Tobias Heise , Hans-Günter Eckel , University of Rostock","doi":"10.1016/j.microrel.2025.115665","DOIUrl":"10.1016/j.microrel.2025.115665","url":null,"abstract":"<div><div>Accurately modelling the lifetime of a power module is a major concern in wind power applications. Their lifetime is typically modelled via empirical laws fitted to data, e.g. from power cycling tests. Often, those models are parametrized with respect to junction temperatures due to its measurability and failure mechanisms occurring close to the chip. Nevertheless, some module types are limited by their large area substrate solder between the baseplate and substrate metallization. They motivate to choose the substrate solder temperatures for a lifetime model instead. Furthermore, transient effects are conceivable which lead to an ambiguous relation between substrate solder and junction temperatures. Thus, for such a model, a substitution of junction temperatures with substrate solder temperatures is carried out to derive a model based on substrate solder temperatures. Afterwards, the influence on lifetime estimation is investigated. For this purpose, the thermal behavior of a PrimePack™2.XT during power cycling is studied, utilizing reduced order models. Lifetime calculations with a junction and a substrate solder temperature-based model on a mission profile from a wind application show that the latter yields a significantly higher lifetime. A shift in the ratio between substrate solder temperature and junction temperature during operation towards a lower regime compared to the power cycling test is identified as the root cause for this. It is shown that from a physical perspective, this result is realistic and a lifetime modelling with respect to substrate solder temperatures increases the accuracy of lifetime prediction in this case.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"168 ","pages":"Article 115665"},"PeriodicalIF":1.6,"publicationDate":"2025-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143561560","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A failure mechanism of 1.2 kV/20 A 4H-SiC Schottky barrier diodes under humidity and high reverse bias voltage

IF 1.6 4区工程技术

Microelectronics Reliability Pub Date : 2025-03-06 DOI: 10.1016/j.microrel.2025.115674

Fanpeng Zeng , Xinyu Wang , Tianlu Wang , Yingxin Cui , Kuan Yew Cheong , Handoko Linewih , Jisheng Han

{"title":"A failure mechanism of 1.2 kV/20 A 4H-SiC Schottky barrier diodes under humidity and high reverse bias voltage","authors":"Fanpeng Zeng , Xinyu Wang , Tianlu Wang , Yingxin Cui , Kuan Yew Cheong , Handoko Linewih , Jisheng Han","doi":"10.1016/j.microrel.2025.115674","DOIUrl":"10.1016/j.microrel.2025.115674","url":null,"abstract":"<div><div>SiC power devices have higher blocking voltage, lower on-resistance, and higher operating temperature than Si-based devices, which can be widely used in electric vehicles, rail transit, and high-voltage power transmission. However, the more severe application environments put higher demands on their reliability. In this paper, 1.2 kV/20 A SiC Schottky Barrier Diodes (SBDs) were evaluated after subjected to a series of reliability tests, including high-temperature storage (HTS), low-temperature storage (LTS), high-temperature reverse bias (HTRB) and high voltage, high humidity, high temperature reverse biased (HV-H<sup>3</sup>TRB) test. All devices passed the HTS, LTS and HTRB tests, but only 80 % of the devices passed the HV-H<sup>3</sup>TRB, which was mainly caused by pre-breakdown before 1200 V. Failure analysis showed that the breakdown point was located at the edge of the termination with cracks and delamination of the passivation layer were observed. Of 80 % of the failed devices after HV- H<sup>3</sup>TRB, almost all showed failure mode of passivation layer damage. With the root cause, the failure mechanism has been identified. This indicates that the passivation layer plays a critical role to determine the reliability of a SiC SBD device.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"168 ","pages":"Article 115674"},"PeriodicalIF":1.6,"publicationDate":"2025-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143552903","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Evidence of resistive switching in SiNx thin films for MEMS capacitors: The role of metal contacts

IF 1.6 4区工程技术

Microelectronics Reliability Pub Date : 2025-03-06 DOI: 10.1016/j.microrel.2025.115661

J. Theocharis, S. Gardelis, G. Papaioannou

引用次数: 0

System in package: Advanced FA techniques to minimize analysis time and cost

IF 1.6 4区工程技术

Microelectronics Reliability Pub Date : 2025-03-06 DOI: 10.1016/j.microrel.2025.115675

K. Szász, D. Luca

{"title":"System in package: Advanced FA techniques to minimize analysis time and cost","authors":"K. Szász, D. Luca","doi":"10.1016/j.microrel.2025.115675","DOIUrl":"10.1016/j.microrel.2025.115675","url":null,"abstract":"<div><div>Over the years packaging types of semiconductor devices have continued to evolve. One of the more complex package types in the Renesas portfolio is the System in Package or SIP. The SIP package presented in this paper features copper pillars, a three Cu layer substrate, passive components, it is overmolded and has a thin, exposed die. The large number of interfaces and components can lead to numerous potential failure locations. The failures addressed in this study are a result of humidity-related qualification processes. Due to the intricacies of the SIP package, following the failure analysis (FA) procedure of standard integrated circuit packages the analysis was fully destructive. These investigations were not only labour-intensive but also costly and could last up to a period of 2–3 weeks. As a result, an altogether new failure analysis approach, adjusted to the complexities of SiP packages was necessary to improve efficiency and accuracy.</div><div>In this case study, an innovative FA workflow is proposed, that includes advanced techniques including Lock-In Thermography and Computed Tomography scans. With the implementation of these methods, the analysis duration and cost were significantly reduced without compromising diagnostic accuracy. This work demonstrates the necessity of adapting FA methodologies to address the unique challenges of advanced packaging systems.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"168 ","pages":"Article 115675"},"PeriodicalIF":1.6,"publicationDate":"2025-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143562346","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Vertical scale-down of Cu/low-k interconnect development for BEOL reliability improvement of 12nm DRAM

IF 1.6 4区工程技术

Microelectronics Reliability Pub Date : 2025-03-06 DOI: 10.1016/j.microrel.2025.115650

J.H. Lee, B.W. Woo, Y.M. Lee, N.H. Lee, Y.Y. Lee, Y.S. Lee, S.B. Ko, S. Pae

引用次数: 0

Effect of 2DEG density and Drain/Source Field Plate design on dynamic-RON of 650 V AlGaN/GaN HEMTs

IF 1.6 4区工程技术

Microelectronics Reliability Pub Date : 2025-03-05 DOI: 10.1016/j.microrel.2025.115666

M. Cioni , G. Giorgino , A. Chini , N. Zagni , G. Cappellini , S. Principato , C. Miccoli , T. Wakrim , M.E. Castagna , A. Constant , F. Iucolano

{"title":"Effect of 2DEG density and Drain/Source Field Plate design on dynamic-RON of 650 V AlGaN/GaN HEMTs","authors":"M. Cioni , G. Giorgino , A. Chini , N. Zagni , G. Cappellini , S. Principato , C. Miccoli , T. Wakrim , M.E. Castagna , A. Constant , F. Iucolano","doi":"10.1016/j.microrel.2025.115666","DOIUrl":"10.1016/j.microrel.2025.115666","url":null,"abstract":"<div><div>The effect of 2DEG density and Drain/Source Field Plate design on dynamic-R<sub>ON</sub> of 650 V p-GaN gate AlGaN/GaN HEMTs is investigated in this work. Devices presenting three different AlGaN barrier and p-GaN layer design have been tested by means of Capacitance-Voltage measurements, Static V<sub>DS</sub> stress and Pulsed I-V characterization. C<img>V measurements allowed the extraction of 2DEG density, while Static V<sub>DS</sub> stress and Pulsed I-V put in evidence the partial recovery of the dynamic-R<sub>ON</sub> at high V<sub>DS,stress</sub>, potentially explained by a field-driven hole generation mechanism that partially compensates negatively ionized Carbon acceptors in the GaN Buffer. This hypothesis is in line with the trends observed for different 2DEG density and different drain field-plate designs, suggesting that a higher electric field under the drain terminal can significantly reduce R<sub>ON</sub>-degradation at high voltages, due to an easier holes generation. Furthermore, Pulsed I-V tests under resistive load switching mode have been addressed, highlighting the impact of the distance between source field plate and drain field plate on the dynamic-R<sub>ON</sub> degradation in conventional switch mode operations.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"168 ","pages":"Article 115666"},"PeriodicalIF":1.6,"publicationDate":"2025-03-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143552894","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Sorption getter characterization under wafer-level packaging (WLP) conditions

IF 1.6 4区工程技术

Microelectronics Reliability Pub Date : 2025-03-05 DOI: 10.1016/j.microrel.2025.115677

H. Duchemin, D. Bouchu

引用次数: 0