Microelectronics Reliability最新文献_第6页

Efficient long-term reliability assessment of planar InGaAs/InP avalanche photodiodes using accelerated step-stress test 利用加速阶跃应力试验评估平面InGaAs/InP雪崩光电二极管的长期可靠性

IF 1.6 4区工程技术

Microelectronics Reliability Pub Date : 2025-04-15 DOI: 10.1016/j.microrel.2025.115739

Yunseok Han , Sunho Kim , Ilgu Yun

引用次数: 0

OFF-state breakdown and threshold voltage stability of vertical GaN-on-Si trench MOSFETs 垂直GaN-on-Si沟槽mosfet的关断击穿和阈值电压稳定性

IF 1.6 4区工程技术

Microelectronics Reliability Pub Date : 2025-04-14 DOI: 10.1016/j.microrel.2025.115716

M. Fregolent , F. Bergamin , D. Favero , C. De Santi , Andrea Cester , C. Huber , G. Meneghesso , E. Zanoni , M. Meneghini

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On the electrical properties of ALD HfO2 dielectric films for MEMS capacitive switches MEMS电容开关用ALD HfO2介电膜电学性能研究

IF 1.6 4区工程技术

Microelectronics Reliability Pub Date : 2025-04-14 DOI: 10.1016/j.microrel.2025.115737

J. Theocharis , J.P. Martins , A. Mahjoub , E. Eustache , A. Ziaei , G. Papaioannou

{"title":"On the electrical properties of ALD HfO2 dielectric films for MEMS capacitive switches","authors":"J. Theocharis , J.P. Martins , A. Mahjoub , E. Eustache , A. Ziaei , G. Papaioannou","doi":"10.1016/j.microrel.2025.115737","DOIUrl":"10.1016/j.microrel.2025.115737","url":null,"abstract":"<div><div>This work investigates the electrical properties of thin HfO<sub>2</sub> dielectric films grown by Atomic Layer Deposition (ALD) for application in RF-MEMS capacitive switches. The motivation arises from the need to optimize dielectric performance in these devices, particularly concerning dielectric charging, breakdown behavior, and conduction mechanisms. A key challenge addressed is the influence of deposition temperature on the structural and electrical behavior of the films, which transitions from amorphous to polycrystalline with temperature. The study utilizes a wide range of techniques including current-voltage measurements, impedance spectroscopy, Kelvin Probe potential decay, and Thermally Stimulated Depolarization Currents (TSDC) on Metal–Insulator-Metal (MIM) devices. The key findings indicate that grain boundary formation in polycrystalline films significantly alters the breakdown voltage, charge transport, and trapping mechanisms. It is worth noting that, films deposited at 100–150 °C exhibit hopping conduction and lower leakage, while those at 200–250 °C demonstrate ohmic or Space Charge Limited Current (SCLC) behavior due to crystallization. These results provide insight for selecting suitable deposition parameters to engineer dielectric materials for reliable MEMS switch operation.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"169 ","pages":"Article 115737"},"PeriodicalIF":1.6,"publicationDate":"2025-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143825915","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Impact of aging on temperature measurements performed using a resistive temperature sensor with sensor-to-microcontroller direct interface 老化对使用具有传感器-微控制器直接接口的电阻式温度传感器进行温度测量的影响

IF 1.6 4区工程技术

Microelectronics Reliability Pub Date : 2025-04-14 DOI: 10.1016/j.microrel.2025.115729

Marco Grossi, Martin Omaña, Cecilia Metra

{"title":"Impact of aging on temperature measurements performed using a resistive temperature sensor with sensor-to-microcontroller direct interface","authors":"Marco Grossi, Martin Omaña, Cecilia Metra","doi":"10.1016/j.microrel.2025.115729","DOIUrl":"10.1016/j.microrel.2025.115729","url":null,"abstract":"<div><div>Temperature measurements play a critical role in guaranteeing system's reliability, for a widespread variety of applications, such as automotive, avionics, etc. Temperature measurements can be conveniently performed at low cost using resistive temperature sensors connected to a microcontroller using sensor-to-microcontroller direct interface (SMDI). However, temperature measurements performed using SMDI may be affected by aging phenomena, such as Bias Temperature Instability (BTI), which may compromise its operation in the field.</div><div>Based on these considerations, in this paper we address the case of temperature measurements performed by a resistive temperature sensor connected to a microcontroller by SMDI. We analyze the impact of BTI on the accuracy of the temperature measurements performed using SMDI. We will show that BTI can seriously degrade the accuracy of such measurements, with possible consequences for system's reliability. We then describe a possible strategy to compensate such a degraded accuracy in temperature measurements, thus avoiding its impact on system's reliability.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"169 ","pages":"Article 115729"},"PeriodicalIF":1.6,"publicationDate":"2025-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143825916","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Study of electrical and thermal performance in single-event burnout of partial-SOI LDMOS transistors 部分soi型LDMOS晶体管单燃坏的电学和热学性能研究

IF 1.6 4区工程技术

Microelectronics Reliability Pub Date : 2025-04-12 DOI: 10.1016/j.microrel.2025.115736

Yanfei Gong , Xingtong Chen , Qiang Zhao , Zhensong Li , Yueqin Li , Jieqing Fan , Jianhong Hao , Fang Zhang , Zhiwei Dong

{"title":"Study of electrical and thermal performance in single-event burnout of partial-SOI LDMOS transistors","authors":"Yanfei Gong , Xingtong Chen , Qiang Zhao , Zhensong Li , Yueqin Li , Jieqing Fan , Jianhong Hao , Fang Zhang , Zhiwei Dong","doi":"10.1016/j.microrel.2025.115736","DOIUrl":"10.1016/j.microrel.2025.115736","url":null,"abstract":"<div><div>For the first time, this paper investigates the single-event burnout (SEB) of partial-silicon-on-insulator (partial-SOI) lateral power MOSFET (LDMOS) devices using TCAD simulation, taking into account the self-heating effect. By analyzing the internal parameters of the device, this paper examines the specific operational conditions of the two key factors (avalanche breakdown of the drain and activation of the source parasitic NPN transistor) that induce SEB in the device, providing a deeper understanding of the physical mechanisms behind the SEB effect. The occurrence mechanism of SEB in PSOI-LDMOS is essentially a thermal runaway issue caused by highly localized current. By analyzing the spatial distribution of lattice temperature, the regions of thermal burnout within the device are predicted. The changes in these thermal burnout regions over time are analyzed in detail, and the corresponding physical reasons are provided. Meanwhile, a hardening design that can significantly enhance the device's anti-SEB performance is proposed by optimizing the doping concentration of the P-layer. Additionally, the effects of heavy ion strikes on SEB in LDMOS devices with different structures were investigated, along with the influence of the BOX layer thickness in PSOI-LDMOS devices on SEB. In summary, the relevant research in this paper can provide important references for understanding the failure mechanism and hardening design of PSOI-LDMOS devices in harsh radiation environments.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"169 ","pages":"Article 115736"},"PeriodicalIF":1.6,"publicationDate":"2025-04-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143824093","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Performance analysis of MTJ-based SNN under resistive open and short defects 基于mtj的SNN在电阻性开路和短路缺陷下的性能分析

IF 1.6 4区工程技术

Microelectronics Reliability Pub Date : 2025-04-11 DOI: 10.1016/j.microrel.2025.115724

Jesus Gamez , Leonardo Miceli , Elena Ioana Vatajelu , Victor Champac

{"title":"Performance analysis of MTJ-based SNN under resistive open and short defects","authors":"Jesus Gamez , Leonardo Miceli , Elena Ioana Vatajelu , Victor Champac","doi":"10.1016/j.microrel.2025.115724","DOIUrl":"10.1016/j.microrel.2025.115724","url":null,"abstract":"<div><div>Spiking Neural Networks (SNNs), inspired by biological neural systems, offer significant potential for energy-efficient artificial intelligence. However, implementing hardware-based SNNs using emerging devices, such as Magnetic Tunnel Junctions (MTJs), introduces vulnerabilities to manufacturing defects. This work investigates the impact of resistive open and short defects on the performance of an MTJ-based SNN through comprehensive circuit-level simulations. A fundamental SNN architecture was implemented, and targeted defects were introduced to evaluate network resilience under realistic operating conditions. Input spike patterns were applied to assess the network's ability to maintain correct functionality in the presence of these defects. Furthermore, the sensitivity of defective SNNs to timing variations within neuron integration and leakage windows was explored. Our findings demonstrate the critical influence of manufacturing defects on SNN reliability and provide quantitative insights into the relationship between defect characteristics and network performance degradation. These results are essential for developing robust fault models and generating effective test vectors, facilitating the development of reliable and scalable hardware SNNs.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"169 ","pages":"Article 115724"},"PeriodicalIF":1.6,"publicationDate":"2025-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143816126","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Synergistic effect of total ionizing dose and electromagnetic interference in SRAM using 22 nm FDSOI technology 利用22 nm FDSOI技术研究SRAM中总电离剂量和电磁干扰的协同效应

IF 1.6 4区工程技术

Microelectronics Reliability Pub Date : 2025-04-10 DOI: 10.1016/j.microrel.2025.115740

Yinyin Shang , Chenhe Gao , Xing Zhao , Binhong Li , Jianzhong Li , Wei Zhu , Jianfei Wu , Hongli Zhang , Jun Luo , Tianchun Ye , Jun Li , Changhua Hu

{"title":"Synergistic effect of total ionizing dose and electromagnetic interference in SRAM using 22 nm FDSOI technology","authors":"Yinyin Shang , Chenhe Gao , Xing Zhao , Binhong Li , Jianzhong Li , Wei Zhu , Jianfei Wu , Hongli Zhang , Jun Luo , Tianchun Ye , Jun Li , Changhua Hu","doi":"10.1016/j.microrel.2025.115740","DOIUrl":"10.1016/j.microrel.2025.115740","url":null,"abstract":"<div><div>In the space environment, electronic devices suffer from performance degradation or failure not only due to radiation but also to electromagnetic interference (EMI). Even worse, the combined effects of various interference exacerbate the impact. In this paper, the synergistic effect of TID and EMI in SRAM with three hardened memory cell architectures (8 T, DICE, double DICE) is investigated. The experimental results show that the SRAM with 8 T structure has the best reliability against electromagnetic and radiated interference compared with DICE and double DICE circuits. After the TID experiment, the level of electromagnetic immunity varies differently for different pins. The electromagnetic immunity level of the power pin and the address pin are reduced respectively after irradiation, while the write enable pin shows little change. In addition, by applying an appropriate back-gate bias or room temperature annealing or a combination of both methods, the degradation of electromagnetic immunity of the chip can be recovered. Finally, based on the analysis results, we propose some optimization methods to improve the robustness of the circuit.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"169 ","pages":"Article 115740"},"PeriodicalIF":1.6,"publicationDate":"2025-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143807696","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Revised CV characterization technique for interface state evaluation in SiN/n-GaN MIS capacitors: Effects of extraction time, temperature and UV illumination 改进的CV表征技术用于评价SiN/n-GaN MIS电容器的界面状态：提取时间、温度和紫外光照的影响

IF 1.6 4区工程技术

Microelectronics Reliability Pub Date : 2025-04-10 DOI: 10.1016/j.microrel.2025.115741

A.M. Hofer , C. Koller , N. Modolo , D. Pogany , C. Ostermaier

{"title":"Revised CV characterization technique for interface state evaluation in SiN/n-GaN MIS capacitors: Effects of extraction time, temperature and UV illumination","authors":"A.M. Hofer , C. Koller , N. Modolo , D. Pogany , C. Ostermaier","doi":"10.1016/j.microrel.2025.115741","DOIUrl":"10.1016/j.microrel.2025.115741","url":null,"abstract":"<div><div>Interface defects at dielectrics/III-nitride interfaces can lead to significant threshold voltage shifts in GaN-based MIS or MOS FETs and dynamic <em>R</em><sub>DS,</sub><sub>on</sub> in HEMTs. Currently, the interface state density, <em>D</em><sub>it</sub>, is often quantified by deviations in the measured capacitance of a stressed curve in relation to an ideal reference curve. However, the influence of measurement parameters, such as sweeping rate and stress conditions, on extracted <em>D</em><sub>it</sub> values remains poorly understood. This study presents an improved method for characterizing interface state densities in dielectric/n-GaN MIS capacitors, were we derive quasi-static CV curves from transient measure-stress-measure measurements at room temperature and elevated temperatures and apply the photo-assisted HF CV technique. Using the Terman method, we extract time-dependent changes in interface charges and show that the extracted <em>D</em><sub>it</sub> distribution depends on the exact choice of extraction time, temperature and UV intensity. We demonstrate that the derived <em>D</em><sub>it</sub> can vary by an order of magnitude and peak positions can shift by 0.4 eV depending on the voltage and measurement conditions, which should be chosen according to the capture/emission dynamics of defects.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"169 ","pages":"Article 115741"},"PeriodicalIF":1.6,"publicationDate":"2025-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143816125","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Ultimate thermal stress reliability evaluation of 3D packaged memory 三维封装存储器极限热应力可靠性评价

IF 1.6 4区工程技术

Microelectronics Reliability Pub Date : 2025-04-10 DOI: 10.1016/j.microrel.2025.115702

Shuai Zhou , Kaixue Ma , Yugong Wu , Shoufu Liu , Chi Ma

引用次数: 0

A virtual test bench oriented to power module evaluation for hybrid traction systems 用于评估混合动力牵引系统动力模块的虚拟测试台

IF 1.6 4区工程技术

Microelectronics Reliability Pub Date : 2025-04-09 DOI: 10.1016/j.microrel.2025.115726

Massimo Sabato , Matteo Ermini , Enrico Stalio , Maurizio Tranchero , Federico Brusiani , Marco Colapietro , Anastasios Nanakos , Thierry Baritaud

{"title":"A virtual test bench oriented to power module evaluation for hybrid traction systems","authors":"Massimo Sabato , Matteo Ermini , Enrico Stalio , Maurizio Tranchero , Federico Brusiani , Marco Colapietro , Anastasios Nanakos , Thierry Baritaud","doi":"10.1016/j.microrel.2025.115726","DOIUrl":"10.1016/j.microrel.2025.115726","url":null,"abstract":"<div><div><em>Hybrid Electric Vehicle</em> (HEV) are becoming widespread and uses devices such as <em>Power Converter</em> (PC). Due to their importance, these devices have attracted the interest of researchers, thus innovative solutions have been developed in recent years. The current study aims to present an electro-thermal simulation tool able to help in the design of a PC. It allows the evaluation of any multilevel PC and the analysis of different operating conditions at low computational cost and avoids expensive tests. The tool is accurately validated against experiments and literature results. In this work, the losses of different PC architectures are evaluated, these include both 2-Level and 3-Level <em>Power Converters</em> (PCs), using IGBT3, EDT2 and MOSFET as power modules. An exhaustive comparison between the dissipation of each typology is proposed and the presented virtual test bench is shown to be efficient and accurate in helping the design of a power converter.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"169 ","pages":"Article 115726"},"PeriodicalIF":1.6,"publicationDate":"2025-04-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143800513","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0