Long-term positive and negative gate bias stress tests on parallel connected SiC MOSFETs at −40 °C and 175 °C

Bias temperature instability (BTI) is known to adversely impact the performance of parallel connected SiC MOSFETs. The short circuit robustness of SiC modules is known to reduce with increased threshold voltage (V_TH) variation within the parallel devices due to poor current sharing. In this paper, 400-h positive BTI (V_GS = 25 V) and negative BTI (V_GS = −10 V) stress tests at both −40 °C and 175 °C have been performed on 5 parallel connected SiC MOSFETs. Both the individual V_TH shift for each of the 5 devices and the module V_TH shift have been measured alongside the V_TH range (highest V_TH minus lowest V_TH). Bipolar preconditioning has been performed before V_TH measurement to record both the peak V_TH (measured before bipolar preconditioning) and permanent V_TH (measured after bipolar preconditioning). The results show that p-BTI stress yields 21 % higher peak module V_TH shift compared to n-BTI at −40 °C and 29 % higher at 175 °C. The measured V_TH range was unchanged by the BTI tests if permanent V_TH shift is assessed. However, the peak V_TH range was higher after stressing thereby indicating increased variability in the injected temporary charge. The peak V_TH range also exhibits a positive temperature coefficient indicating that temperature increases variability of the injected charge. If V_TH range is taken as an indicator of short circuit robustness in parallel connected devices, the measurements presented show that bipolar preconditioning ensures that the short circuit performance of the module would likely be unaffected by the stress tests since ΔV_TH shift is uniform.