Thermo-electrical reliability of power MOSFETs influenced by packaging architecture in stack-die and single-die configurations

Abstract

As the demand for high-power semiconductor devices continues to grow, wide bandgap (WBG) MOSFETs are being increasingly adopted across diverse power electronic applications. Compared to conventional Si-based MOSFETs, however, the reliability characteristics of WBG devices, particularly those employing cascode GaN configurations, remain inadequately explored from a packaging standpoint. This study presents a comparative investigation of degradation mechanisms and failure modes in a 650 V vertical Si MOSFET with a single-die package and a cascode GaN FET integrated with a Si MOSFET in a stack-die configuration. A Highly Accelerated Life Test (HALT) combining temperature and power cycling was implemented, with the Coffin-Manson model yielding an acceleration factor of 1.66, thereby reducing the total test time by 14 h. In parallel, gate bias stress was evaluated using Weibull distribution modeling, which identified 30 V as a critical threshold for initiating accelerated degradation without immediate device breakdown.

The results demonstrate that packaging architecture significantly influences solder joint degradation and overall thermal performance. The findings also confirm the value of the proposed HALT methodology in efficiently identifying failure mechanisms, providing actionable insights into the packaging reliability of 650 V power MOSFETs under harsh operating conditions.