Design of an energy-efficient soft error resilient RHBD SRAM cell with high read stability and minimum write errors

Abstract

This article proposes an energy-efficient, soft-error tolerant, read-stability improved SRAM cell with less Write Error Rate (WER). The proposed S8P9N has 8 PMOS and 9 NMOS transistors including access transistors. This SRAM cell has only two sensitive nodes, achieved by surrounding the nodes with the same type of transistors. The proposed cell is immune to all Single Event Upsets (SEUs) at sensitive nodes and shows 83.3% and 50% tolerance to Double Node Upsets (DNUs) and Triple Node Upsets (TNUs) respectively. The four access transistors in the S8P9N cell reduce write delay, and WER. Additionally, the proposed SRAM cell achieves the lowest dynamic power dissipation of 1.25 $\mu$W, high read stability of 320 mW, and low read and write energy of 0.83 aJ and 0.07 fJ, respectively. All designs are implemented using UMC 65 nm technology, operating at a supply voltage of 1.2 V and at a temperature of 27 °$C$. Reliability is analyzed through 5000-point Monte Carlo (MC) simulation under various Process Voltage Temperature (PVT) conditions. The proposed design has a critical charge, Qc of $>$ 90 fC . The S8P9N RHBD SRAM cell has a minimum soft error occurrence probability (P${}_S$) of 1.6%. The combination of low power consumption, low energy, high read stability, less write error rate of $<$ 0.1%, and improved reliability makes the S8P9N design suitable for low-power cache in aerospace applications.