Reliability analysis of dopingless vertical nanowire TFET with interface trap charges for ring-oscillator circuit implementation

Abstract

This manuscript is presenting a dopingless (DL) vertical nanowire tunnel FET (V-NW-TFET) with gate all around (GAA) structure with the effect of Interface-Trap-Charges (ITCs). By implanting the metal with the required work function, the charge plasma method induces the required doping in the source and drain. The ITCs' effects on the dopingless device are comprehensively discussed along with the linearity performance parameters such as higher order harmonic distortions (HDs), intermodulation distortions (IMDs), and interception points. According to the different findings, negative ITCs degrade the device performance, whereas positive ITCs can aid in enhancing device attributes and characteristics. With the positive trap charges, the ratio of ON to OFF current goes up along with the enhancement of the ON-state current by about 50 %. Positive ITCs enhance the ITC-DL-V-NW-TFET's driving capabilities, making it a better choice for analog applications. The proposed device has shown increased cut-off frequency and reduced threshold voltage for higher positive ITCs. A wide temperature ranges from 200 K to 400 K is applied to check the reliability of the device, but only a minor change in different device characteristics can be observed. In this paper, for the first time the dopingless vertical nanowire tunnel FET with ITC effect is utilized for ring-oscillator circuit implementation, where three inverters are used to design the three-stage ring-oscillator. The proposed ring-oscillator circuit exhibits reduced delay and power consumption as compared to MOSFET based ring-oscillator circuit.