Accurate and efficient simulation of PCB warpage during manufacturing processes using partitioned equivalent model

During the complex manufacturing processes of printed circuit boards (PCBs), residual stresses inevitably accumulate, leading to warpage and stress concentration that can damage solder joints and interfaces, ultimately compromising the long-term reliability of electronic systems. To address these issues, this study proposes a partitioned equivalent model based on the multiscale finite element method, and comprehensively simulates the effects of lamination, etching and surface treatments (hot air solder leveling and solder mask coating) on PCB warpage. A key feature of this model is the integration of a post-processing strategy, which uses the correlation between copper content and coating thickness of the surface wiring layer to improve the prediction accuracy of PCB surface flatness and warpage. Additionally, the model incorporates specific boundary conditions for each wiring layer to more accurately calculate the equivalent material properties, under realistic manufacturing conditions. The multiscale simulation results are compared with the warpage and displacement curves obtained from both the shadow Moiré experiments and the finite element model with fully detailed wiring. The comparisons reveal a high level of agreement in warpage morphology, with the accuracy for warpage values of the partitioned equivalent model after surface treatments exceeding 75 %. Besides, this model shows significant advantages in computational efficiency, with simulation time reduced by up to 80 % compared to the fully detailed wiring model. Therefore, the proposed modeling approach can serve as an effective tool for optimizing PCB manufacturing processes, structural designs, and material selection, thereby enhancing the reliability and performance of electronic products.