Microelectronics Journal最新文献_第5页

A 0.029-mm2 11.5-ENOB 8.05-kHz BW voltage Fold-Shrink SAR ADC for cochlear implant 一种用于人工耳蜗的0.029 mm2 11.5-ENOB 8.05 khz BW电压折叠收缩SAR ADC

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-09-10 DOI: 10.1016/j.mejo.2025.106885

Hongbo Gu , Wei Zhang , Lei Liao , Zhihui Qin

{"title":"A 0.029-mm2 11.5-ENOB 8.05-kHz BW voltage Fold-Shrink SAR ADC for cochlear implant","authors":"Hongbo Gu , Wei Zhang , Lei Liao , Zhihui Qin","doi":"10.1016/j.mejo.2025.106885","DOIUrl":"10.1016/j.mejo.2025.106885","url":null,"abstract":"<div><div>This work introduces a voltage Fold-Shrink Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC). It is characterized by an all-resistor divider Digital-to-Analog Converter (DAC) which keeps a proportional voltage for the Most Significant Bit (MSB) sub-Digital-to-Analog Converter (subDAC). In addition, it utilizes scaling capacitors to execute a fold-and-shrink technique for the Least Significant Bit (LSB) subDAC, thereby yielding the combined output of the DAC. A 12-bit SAR ADC prototype has been developed using a 90 nm CMOS process. It occupies an area of 0.029 mm<sup>2</sup> and is designed for Cochlear Implant applications. Operating at 1 V with a sampling rate of 1 MS/s, this ADC demonstrates an effective number of bits (ENOB) of 11.5, a signal-to-noise-and-distortion ratio (SNDR) of 71.22 dB, a bandwidth of 8.05 kHz, and a power consumption of 0.85 μW. Both MSB and LSB subDACs are configured as 6-bit with a 16-fold scaling capacitor for LSB voltage shrinkage. A newly developed low-power dynamic comparator (CMP) augmented by placing a capacitor at the output of MSB subDAC is utilized to minimize kick-back noise, which highlights the design's focus on both power efficiency and noise suppression.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"166 ","pages":"Article 106885"},"PeriodicalIF":1.9,"publicationDate":"2025-09-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145050206","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A 56 Gb/s PAM4 slope-sampling CDR with simultaneous four-output phase interpolator 一个56 Gb/s的PAM4斜率采样CDR，带同步四输出相位插值器

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-09-09 DOI: 10.1016/j.mejo.2025.106870

Zekai Yang , Xiaoteng Zhao , Huajin Sun , Xianting Su , Zhicheng Dong , Yilong Dong , Yukui Yu , Hongzhi Liang , Shubin Liu

引用次数: 0

A power-iteration-based beamformer for large-scale antenna arrays 一种用于大规模天线阵列的功率迭代波束形成器

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-09-09 DOI: 10.1016/j.mejo.2025.106868

Ting Huang, Ziyu Guo, Bo Hu, Xu Cheng, Jun Han, Xiaoyang Zeng

{"title":"A power-iteration-based beamformer for large-scale antenna arrays","authors":"Ting Huang, Ziyu Guo, Bo Hu, Xu Cheng, Jun Han, Xiaoyang Zeng","doi":"10.1016/j.mejo.2025.106868","DOIUrl":"10.1016/j.mejo.2025.106868","url":null,"abstract":"<div><div>Beamforming with a large-scale antenna array is one of the enabling techniques for communications in high frequencies. The related computational overhead, which arises from the sharply increased complexity of algorithmic computation and control logic due to the higher dimension of the spatial covariance matrix, is a major impediment to scaling up the antenna array and thereby improving beamforming performance. This paper presents the power-iteration-based beamforming algorithm and the hardware implementation that are well suited for the applications to large-scale antenna arrays. In general, the power iteration method converges slowly. However, we find that the slow convergence has minimal effect on the beamforming performance. This fact enables convergence-less termination of the beamforming algorithm, and hence contributes to significant reduction in the computational complexity. To deal with large-scale antenna arrays, the inherent data Hermitian symmetry property is also utilized for memory compression, reducing the memory cost nearly by half. In the meantime, the dedicated addressing scheme is provided for parallel data access without memory conflict. Our design is layouted in a 22-nm CMOS technology, supporting 32 to 1024 antenna elements, integrating 6277K gates in an area of 4.97 mm<sup>2</sup>, and dissipating 159 mW at 600MHz. It outperforms the state-of-the-art results in the scalability to support large-scale antenna arrays, and can achieve high energy efficiency, too.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"166 ","pages":"Article 106868"},"PeriodicalIF":1.9,"publicationDate":"2025-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145027499","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A high-speed level shifter with adaptive positive dV/dt noise blanker for GaN-based buck converters 一种用于氮化镓降压变换器的具有自适应正dV/dt噪声抑制的高速电平移位器

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-09-08 DOI: 10.1016/j.mejo.2025.106876

Chengzhi Xu , Peiyuan Fu , Gefu Wang , Xufeng Liao , Lianxi Liu

引用次数: 0

A linear chirp generator with 2nd DPD technique based on a Type-III SPLL 基于iii型SPLL的二阶DPD线性啁啾发生器

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-09-06 DOI: 10.1016/j.mejo.2025.106871

Chao Gu , Ruixue Ding , Yuan Gao , Guodong Huang , Depeng Sun , Shubin Liu

引用次数: 0

A 7-bit 8 GHz phase interpolator with eight-phase output using a linear weighting scheme using only 50 % interpolation units 一个7位8 GHz相位插补器，8相位输出，采用线性加权方案，仅使用50%的插补单元

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-09-06 DOI: 10.1016/j.mejo.2025.106874

Jie Liu, Xianting Su, Zekai Yang, Zhicheng Dong, Chenxi Han, Xiaoteng Zhao, Shubin Liu

{"title":"A 7-bit 8 GHz phase interpolator with eight-phase output using a linear weighting scheme using only 50 % interpolation units","authors":"Jie Liu, Xianting Su, Zekai Yang, Zhicheng Dong, Chenxi Han, Xiaoteng Zhao, Shubin Liu","doi":"10.1016/j.mejo.2025.106874","DOIUrl":"10.1016/j.mejo.2025.106874","url":null,"abstract":"<div><div>This paper proposes a 7-bit four-phase-input, eight-phase-output phase interpolator (PI) that adopts an improved linear weighting scheme to fully utilize the interpolation units and avoid area waste. To improve nonlinearity, the approach leverages the fact that adjacent signals among the eight-phase signals exhibit opposite integral nonlinearity (INL) characteristics using linear weighting. The adjacent signals are first regulated to the same amplitude and then combined to improve the INL of the summation signal. The PI, implemented in a 28 nm CMOS process, is designed to operate at 8 GHz. Post-layout simulation results demonstrate that the PI achieves a peak-to-peak integral nonlinearity (INL<sub>pp</sub>) of 2.05 LSB and a peak-to-peak differential nonlinearity (DNL<sub>pp</sub>) of 0.48 LSB at 8 GHz, with a power consumption of 30.84 mW, and an area of 0.006 mm<sup>2</sup>. The proposed PI maintains robust performance across PVT, with INL<sub>pp</sub> below 2.47LSB and DNL<sub>pp</sub> below 0.61LSB. The overall system achieves a jitter of 60.3 fs<sub>rms</sub> integrated from 10 kHz to 1 GHz.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"166 ","pages":"Article 106874"},"PeriodicalIF":1.9,"publicationDate":"2025-09-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145027497","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Load-driven inductive peaking design for broad band continuous-time linear equalizer 负载驱动的宽带连续时间线性均衡器电感峰值设计

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-09-05 DOI: 10.1016/j.mejo.2025.106873

Miao Zhang , Ruidong Li , Xiaoteng Zhao , Xianting Su , Zhicheng Dong , Zekai Yang , Hongyu Su , Hongzhi Liang , Yukui Yu , Shubin Liu

{"title":"Load-driven inductive peaking design for broad band continuous-time linear equalizer","authors":"Miao Zhang , Ruidong Li , Xiaoteng Zhao , Xianting Su , Zhicheng Dong , Zekai Yang , Hongyu Su , Hongzhi Liang , Yukui Yu , Shubin Liu","doi":"10.1016/j.mejo.2025.106873","DOIUrl":"10.1016/j.mejo.2025.106873","url":null,"abstract":"<div><div>This article presents modeling and analysis of several wideband current-mode logic (CML) continuous-time linear equalizers (CTLEs), including series peaking, shunt peaking, T-coil peaking, and bridged-shunt T-coil peaking architectures. Theoretical analysis reveals the peaking gain-bandwidth product (PGBW) of each structure. The series peaking configuration achieves the highest PGBW when the parasitic capacitance <em>C</em><sub><em>D</em></sub> is comparable to the load capacitance <em>C</em><sub><em>L</em></sub>, corresponding to larger input transistor sizes. In contrast, the bridged-shunt T-coil peaking structure delivers superior PGBW performance when <em>C</em><sub><em>D</em></sub> is significantly smaller than <em>C</em><sub><em>L</em></sub>. Based on these modeling insights, an analog front-end (AFE) circuit is designed in 28-nm CMOS technology for a 112-Gb/s PAM-4 medium-reach (MR) receiver (RXs), targeting scenarios where <em>C</em><sub><em>D</em></sub> is relatively small. The proposed AFE adopts a bridged-shunt T-coil peaking structure to extend the bandwidth. Post-layout simulations demonstrate that the proposed AFE achieves a boost gain of up to 21.5-dB dissipating 43.8 mW at a 0.9-V supply, achieving larger than 28-GHz bandwidth within the area of 0.06 mm<sup>2</sup>.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"166 ","pages":"Article 106873"},"PeriodicalIF":1.9,"publicationDate":"2025-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145027498","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Authentication scheme resistant to machine learning based on obfuscation of multiple PUF responses 基于多PUF响应混淆的抗机器学习认证方案

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-09-04 DOI: 10.1016/j.mejo.2025.106867

Tianming Ni , Hao Wu , Fei Li , Mu Nie , Yun Liu , Ang Hu , Jingchang Bian

{"title":"Authentication scheme resistant to machine learning based on obfuscation of multiple PUF responses","authors":"Tianming Ni , Hao Wu , Fei Li , Mu Nie , Yun Liu , Ang Hu , Jingchang Bian","doi":"10.1016/j.mejo.2025.106867","DOIUrl":"10.1016/j.mejo.2025.106867","url":null,"abstract":"<div><div>Traditional authentication protocols leveraging Physical Unclonable Functions (PUFs) face vulnerabilities to modeling attacks, this paper proposes multi-Arbiter-PUF obfuscation PUF (MAO PUF) architecture. This architecture incorporates <span><math><mrow><mi>n</mi></mrow></math></span> Arbiter PUFs (APUFs) and a <span><math><mrow><mi>k</mi></mrow></math></span>-stage Linear Feedback Shift Register (LFSR), where the responses from n APUFs are employed to obfuscate the LFSR's configuration parameters, thereby enhancing resistance against machine learning-based modeling attacks. The (n,k)-MAO PUF architecture was implemented on a Xilinx Virtex-7 Field Programmable Gate Array (FPGA) platform, demonstrating that the (5,3)-MAO PUF achieves an optimal balance between resource overhead and performance metrics. The (5,3)-MAO PUF depends on responses from five APUFs to obfuscate both the initial seed and feedback coefficients of a 3-stage LFSR. This approach reduces the prediction accuracy of three mainstream machine learning attacks to nearly 50 %, while maintaining statistical characteristics close to ideal values. Furthermore, based on the structural characteristics of (n,k)-MAO PUF, we further propose a novel highly secure authentication protocol which is particularly suitable for the Internet of Things (IoT) systems.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"166 ","pages":"Article 106867"},"PeriodicalIF":1.9,"publicationDate":"2025-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145020598","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A second-order CIFF delta-sigma modulator with wide input voltage range using double feedback integration 采用双反馈积分的二阶CIFF宽输入电压范围δ - σ调制器

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-09-03 DOI: 10.1016/j.mejo.2025.106869

Neungin Jeon , Juncheol Kim , Seong Bok , Young-Chan Jang

{"title":"A second-order CIFF delta-sigma modulator with wide input voltage range using double feedback integration","authors":"Neungin Jeon , Juncheol Kim , Seong Bok , Young-Chan Jang","doi":"10.1016/j.mejo.2025.106869","DOIUrl":"10.1016/j.mejo.2025.106869","url":null,"abstract":"<div><div>A second-order delta-sigma modulator (DSM) with a wide input voltage range is proposed for sensor applications. To achieve the characteristics of high resolution and small area, it uses a cascaded-of-integrators feedforward (CIFF) architecture and a successive approximation register (SAR) analog-to-digital converter (ADC) for a 3-bit quantizer. To implement a wide input voltage range, the first integrator of the proposed DSM performs double feedback integration for each sampled input. This makes the proposed DSM, which uses a single power supply, to use the reference voltage from the internal reference driver and have an analog input voltage range twice the reference voltage range without the use of additional capacitors. The second-order DSM is implemented using a 130 nm CMOS process with a supply voltage of 1.5 V. When the sample frequency and oversampling ratio (OSR) are 500 kHz and 125, respectively. The measured SNDR of the implemented DSM is approximately 85.49 dB of SNDR for an input signal of 353 Hz. The active area and power consumption are 0.095 mm<sup>2</sup> and 315.45 μW, respectively.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"165 ","pages":"Article 106869"},"PeriodicalIF":1.9,"publicationDate":"2025-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145003974","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A snapback-free and fast reverse recovery capability RC IGBT with passive trench MOS and trench shield SBD 具有无源战壕MOS和战壕屏蔽SBD的无反弹和快速反向恢复能力的RC IGBT

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-09-03 DOI: 10.1016/j.mejo.2025.106865

Wei Li , Haifeng Qin

{"title":"A snapback-free and fast reverse recovery capability RC IGBT with passive trench MOS and trench shield SBD","authors":"Wei Li , Haifeng Qin","doi":"10.1016/j.mejo.2025.106865","DOIUrl":"10.1016/j.mejo.2025.106865","url":null,"abstract":"<div><div>A Snapback-Free and fast reverse recovery capability RC IGBT featuring the Passive Trench MOS and trench shield SBD is proposed and investigated by simulation. The PT-MOS is introduced at the Collector. The gate and the source of PT-MOS was shorted by the N-buffer layer, which realizes the reverse conduction ability without additional input signal. Additionally, the Schottky Barrier Diode (SBD) is integrated at Emitter. The SBD is shield by dual trench gates. Thus, the breakdown voltage will not be affected by the SBD. During forward-conduction stage, the PT-MOS is off-state. The snapback is eliminated by the P-well electron barrier. During backward-conduction stage, the PT-MOS and SBD are turn-on automatically to achieve reverse conducting ability. During reverse recovery stage, the SBD can effectively suppress hole injection from the body diode, thereby significantly reducing the reverse recovery charge. The simulation results indicate that, compared with conventional RC IGBT and FPL IGBT, the Proposed IGBT achieves a 67 % and 76.5 % reduction in reverse recovery charge, respectively. At the same turn-off loss <em>E</em><sub>OFF</sub> of 29 mJ/cm<sup>2</sup>, the on-state voltage <em>V</em><sub>ON</sub> of the Pro IGBT is reduced by 40 % and 11 % compared to the Con IGBT and FPL IGBT, respectively.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"165 ","pages":"Article 106865"},"PeriodicalIF":1.9,"publicationDate":"2025-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145018410","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0