Microelectronics Journal最新文献_第5页

Design and investigation of electrostatic doped heterostructure vertical Si(1-x)Gex/Si nanotube TFET 静电掺杂异质结构垂直硅（1-x）Gex/硅纳米管 TFET 的设计与研究

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2024-09-13 DOI: 10.1016/j.mejo.2024.106417

Soumya Sen, Mamta Khosla, Ashish Raman

{"title":"Design and investigation of electrostatic doped heterostructure vertical Si(1-x)Gex/Si nanotube TFET","authors":"Soumya Sen, Mamta Khosla, Ashish Raman","doi":"10.1016/j.mejo.2024.106417","DOIUrl":"10.1016/j.mejo.2024.106417","url":null,"abstract":"<div>Researchers are inclining toward heterostructures suitable lattice matching, in Tunnel FETs to eliminate the difficulties of decreased On-Current, subthreshold swings, and ambipolar behavior. Nowadays, Electrostatic doping (ED) is a scrutinized substitute device for creating areas with a high electron or hole density to the conventional doped devices. This manuscript proposes an Electrostatic Doped Heterostructure Vertical Si(1-x)Gex/Si Nanotube Tunnel Field Effect with performance scanned by analyzing the different device parameters, considering the energy band diagram, concentrations of electrons, holes, potential, and electric field. In comparison to the Nanowire TFETs, the area, and rate of tunneling of the proposed device stand superior with a better ION/IOFF ratio of 1.56∗1013 and a lower OFF-current of about ∼10−18A/μm. The device exhibits a Drain current (IDS) of 2.39∗105A/μm. The architecture of the suggested device possessing Si(1-x)Gex/Si structure exhibits enhanced characteristics like improved steepness of the sub-threshold slope, ION/IOFF ratio, drain current, and lowered OFF-current.</div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142233589","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Miniaturized bandpass filter with ultrawide-stopband and high selectivity using glass-based IPD technology 利用玻璃基 IPD 技术实现超宽截止带和高选择性的微型带通滤波器

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2024-09-12 DOI: 10.1016/j.mejo.2024.106402

Jianye Wang, Yazi Cao, Wei Wu, Gaofeng Wang

{"title":"Miniaturized bandpass filter with ultrawide-stopband and high selectivity using glass-based IPD technology","authors":"Jianye Wang, Yazi Cao, Wei Wu, Gaofeng Wang","doi":"10.1016/j.mejo.2024.106402","DOIUrl":"10.1016/j.mejo.2024.106402","url":null,"abstract":"<div>A miniaturized bandpass filter (BPF) with ultrawide-stopband and high selectivity performance is proposed by virtue of glass-based integrated passive devices (IPD) technology. The proposed BPF consists of two modified second-order units and an impedance inverter. In the modified second-order units, two capacitors are added to the traditional second-order Chebyshev bandpass filter, which can generate two additional transmission zeros locating in the lower and upper bands, respectively. Moreover, these two modified second-order units are cascaded to improve the selectivity and achieve the ultrawide-stopband of the proposed BPF. In addition, the cascaded impedance inverter is introduced to further improve impedance matching of the proposed BPF. The proposed BPF is fabricated using glass-based IPD technology and measured by on-wafer probing. The fabricated BPF has a compact size of 1.0 mm × 1.0 mm × 0.35 mm. The measured results show that the fabricated BPF can cover the wide operating band from 3.3 GHz to 5.0 GHz with an insertion loss of 1.4 dB, a return loss better than 17.5 dB in the passband, and an upper stopband suppression better than 21.6 dB up to 43.5 GHz (10.48f0). In addition, the fabricated BPF can achieve a good frequency selectivity with a rectangular coefficient of 1.33. The simulated and measured results exhibit good agreements.</div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142243649","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

High-precision vernier-type optoelectronic integrated chip design 高精度游标型光电集成芯片设计

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2024-09-12 DOI: 10.1016/j.mejo.2024.106400

Yingxu Zhou, Wei Zhang, Tingting Wu, Wangping Chen, Shuang Du, Dongning Hao

引用次数: 0

Design of a miniaturized multi resonance resonator based highly selective dual wideband bandpass filter 设计基于微型多谐振共振器的高选择性双宽带带通滤波器

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2024-09-11 DOI: 10.1016/j.mejo.2024.106411

Muhammad Abdul Rehman , Bilal Mushtaq , Sohail Khalid , Mujeeb Ur Rehman

{"title":"Design of a miniaturized multi resonance resonator based highly selective dual wideband bandpass filter","authors":"Muhammad Abdul Rehman , Bilal Mushtaq , Sohail Khalid , Mujeeb Ur Rehman","doi":"10.1016/j.mejo.2024.106411","DOIUrl":"10.1016/j.mejo.2024.106411","url":null,"abstract":"<div>This paper presents the design of a highly selective dual-wideband bandpass filter. The filter is designed by using multi-resonance resonator consisting of two stub-loaded step impedance resonators separated by an inter-digital capacitor. The inter-digital capacitor generates capacitive coupling, resulting in multiple resonating modes. The proposed filter generates two passband frequencies centered at 5.75 GHz and 11.5 GHz. Experimental measurements show that the maximum insertion loss in the passbands is 0.83 dB and 0.87 dB, while the reflection losses are better than 10.8 dB and 12.6 dB, respectively. The resonant frequencies can be adjusted by changing the length of the loaded stubs. The proposed dual-wideband bandpass filter offers improved out-of-band rejection and selectivity by generating seven transmission poles and seven transmission zeros around both passbands. The experimental results confirm the effectiveness of the proposed filter. Furthermore, the filter has a compact size of <math><mrow><mrow><mo>(</mo><mn>0</mn><mo>.</mo><mn>61</mn><mo>×</mo><mn>0</mn><mo>.</mo><mn>66</mn><mo>)</mo></mrow><msub><mrow><mi>λ</mi></mrow><mrow><mi>g</mi></mrow></msub></mrow></math>, making it suitable for integration into microwave sensing devices.</div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://www.sciencedirect.com/science/article/pii/S1879239124001152/pdfft?md5=4818d63dafffd47325c9ae13d3aa4482&pid=1-s2.0-S1879239124001152-main.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142172726","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Step thickness drift region automatic design of SOI LDMOS using physics-inspired constrained simulated annealing algorithm 利用物理学启发的约束模拟退火算法自动设计 SOI LDMOS 的阶跃厚度漂移区

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2024-09-07 DOI: 10.1016/j.mejo.2024.106410

Jing Chen, Jiajun Guo, Qing Yao, Kemeng Yang, Jun Zhang, Jiafei Yao, Yufeng Guo

{"title":"Step thickness drift region automatic design of SOI LDMOS using physics-inspired constrained simulated annealing algorithm","authors":"Jing Chen, Jiajun Guo, Qing Yao, Kemeng Yang, Jun Zhang, Jiafei Yao, Yufeng Guo","doi":"10.1016/j.mejo.2024.106410","DOIUrl":"10.1016/j.mejo.2024.106410","url":null,"abstract":"<div>The introduction of the step thickness drift region (ST) technique has increased the design complexity of silicon-on-insulator (SOI) lateral double-diffused metal-oxide-semiconductor (LDMOS). This paper proposes a physics-inspired automatic optimization method for the ST structure of SOI LDMOS using constrained simulated annealing algorithm. Since breakdown voltage (BV) and specific on-resistance (Ron,sp) need to be optimized simultaneously, an optimization function based on Baliga's Figure of Merit (BFOM) is introduced. Besides, constraints are introduced to ensure that BV is greater than the initial BV and Ron,sp is less than the initial Ron,sp. Results demonstrate that the BFOM values increase by an average of 134.9 %, 163.6 %, and 113.8 % when the breakdown occurs at the N+N junction, PN junction, and in-the-body after optimizing the ST structure, respectively. Besides, introducing constraints during the automatic design process allows for the simultaneous optimization of both the BV and Ron,sp. Furthermore, the proposed method is also efficient, with 86 % of the optimization design processes completed within 18 seconds.</div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142148724","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

An LC-tank based DCO for low-power high-speed applications using full-custom nMOS-type varactors 使用全定制 nMOS 型变容器的基于 LC 罐的 DCO，适用于低功耗高速应用

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2024-09-06 DOI: 10.1016/j.mejo.2024.106398

Pablo Jiménez-Fernández , Alberto Rodríguez-Pérez , Enrique Prefasi , Francisco Sierra , Rocío del Río , Óscar Guerra

{"title":"An LC-tank based DCO for low-power high-speed applications using full-custom nMOS-type varactors","authors":"Pablo Jiménez-Fernández , Alberto Rodríguez-Pérez , Enrique Prefasi , Francisco Sierra , Rocío del Río , Óscar Guerra","doi":"10.1016/j.mejo.2024.106398","DOIUrl":"10.1016/j.mejo.2024.106398","url":null,"abstract":"<div><math><mrow><mi>L</mi><mi>C</mi></mrow></math>-tank based Digital Controlled Oscillators (<math><mrow><mi>L</mi><mi>C</mi></mrow></math>-DCOs) are widely used in digital assisted high-speed data communication systems due to their high quality factor (<math><mi>Q</mi></math>). Typically, <math><mrow><mi>L</mi><mi>C</mi></mrow></math>-DCOs incorporate digital-controlled varactors for frequency control. The varactor structure significantly influences oscillator <math><mi>Q</mi></math> and phase noise performance. In this paper we propose using full-custom varactors built with digitally connected nMOS-type transistors to enhance the varactor <math><mi>Q</mi></math> by reducing its length. However, parasitic resistance from varactor array interconnection with the <math><mrow><mi>L</mi><mi>C</mi></mrow></math>-tank can impact the overall oscillator performance. This paper presents a methodology to systematically include the proposed varactor array and its parasitic effects into <math><mrow><mi>L</mi><mi>C</mi></mrow></math>-DCO design flow. Following the proposed method, an optimal combination of the inductor and varactor array can be accurately determined. As a proof of concept, we designed and manufactured a 23.5-GHz <math><mrow><mi>L</mi><mi>C</mi></mrow></math>-DCO using 28-nm CMOS RF process. The oscillator exhibits a maximum phase noise of −90.1 dBc/Hz at 1-MHz offset with a power consumption of only 1.71 mW at 1-V supply.</div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-09-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142229125","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A temperature compensation technique for constant current LED driver 恒流 LED 驱动器的温度补偿技术

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2024-09-06 DOI: 10.1016/j.mejo.2024.106396

Shih-Chang Hsia, Wei-Cun Chen

引用次数: 0

A 62.5 kHz-BW 92 dB-SNDR noise-shaping SAR ADC with NS-CAL method 采用 NS-CAL 方法的 62.5 kHz-BW 92 dB-SNDR 噪声整形 SAR ADC

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2024-09-05 DOI: 10.1016/j.mejo.2024.106401

Jianzheng Li , Yuchen Zhao , Weimin Hu , Jinghan Yao , Ziwei Liu , Yajie Qin

引用次数: 0

A 28-nm 9T SRAM-based CIM macro with capacitance weighting module and redundant array-assisted ADC 基于 28 纳米 9T SRAM 的 CIM 宏，带电容加权模块和冗余阵列辅助 ADC

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2024-09-03 DOI: 10.1016/j.mejo.2024.106397

Zhiting Lin , Runru Yu , Da Huo, Qingchuan Zhu, Miao Long, Yongqi Qin, Yanchun Liu, Lintao Chen, Simin Wang, Ting Wang, Yousheng Xing, Zeshi Wen, Yu Liu, Xin Li, Chenghu Dai, Qiang Zhao, Chunyu Peng, Xiulong Wu

{"title":"A 28-nm 9T SRAM-based CIM macro with capacitance weighting module and redundant array-assisted ADC","authors":"Zhiting Lin , Runru Yu , Da Huo, Qingchuan Zhu, Miao Long, Yongqi Qin, Yanchun Liu, Lintao Chen, Simin Wang, Ting Wang, Yousheng Xing, Zeshi Wen, Yu Liu, Xin Li, Chenghu Dai, Qiang Zhao, Chunyu Peng, Xiulong Wu","doi":"10.1016/j.mejo.2024.106397","DOIUrl":"10.1016/j.mejo.2024.106397","url":null,"abstract":"<div>In the emerging field of Computing-in-Memory (CIM), this study introduces a 28-nm CMOS-based Static Random Access Memory (SRAM) CIM macro capable of various computational modes, potentially offering a solution to the Von Neumann bottleneck. Beyond traditional SRAM read and write operations, to enhance the flexibility of the CIM macro, a 9T cell is proposed for performing AND, OR, and XNOR operations; a new capacitive weighting module is introduced to reduce the area of conventional ladder capacitors; and a redundant array-assisted Analog-to-Digital Converter (ADC) is proposed to improve linearity during ADC quantization. The proposed architecture can achieve multi-bit multiplication and accumulation (MAC), OR accumulation (ORA), and XNOR accumulation (XNORA). Simulated using a 28-nm CMOS process, the architecture demonstrated a minor standard deviation in BL voltage of 16.27 mV at the SS process corner, as evidenced by Monte Carlo simulation. At the TT process corner, the energy expenditure for MAC, XNORA, and ORA operations was 5.76, 5.85, and 5.82 fJ/op, respectively.</div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142148723","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

An energy-efficient 16 MS/s 10-bit SAR ADC with MSB-block switching scheme 采用 MSB 块切换方案的高能效 16 MS/s 10 位 SAR ADC

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2024-09-02 DOI: 10.1016/j.mejo.2024.106369

Mingkang Wan, Yuwei Zhang, Xian Tang

引用次数: 0