Microelectronics Journal最新文献_第5页

E-band T/R MMIC for 5G millimeter wave applications 用于5G毫米波应用的e波段T/R MMIC

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-06-14 DOI: 10.1016/j.mejo.2025.106758

Zhenbei Li, Nan Guo, Huanhuan Guan, Jian Zhang, Qiuze Yu

{"title":"E-band T/R MMIC for 5G millimeter wave applications","authors":"Zhenbei Li, Nan Guo, Huanhuan Guan, Jian Zhang, Qiuze Yu","doi":"10.1016/j.mejo.2025.106758","DOIUrl":"10.1016/j.mejo.2025.106758","url":null,"abstract":"<div><div>This paper presents a T/R MMIC operating in the 66–76 GHz frequency range, designed utilizing 0.10-<span><math><mi>μ</mi></math></span>m GaAs pHEMT technology. In transmit (Tx) mode, a four-stage cascaded power amplifier with a four-way power combining architecture is implemented, utilizing T-junctions and a Lange coupler for efficient power synthesis. A compact bus-fed power supply structure is adopted to minimize chip area. In receive (Rx) mode, a four-stage cascaded low-noise amplifier (LNA) is integrated with a compact size. A low insertion loss single-pole double-throw (SPDT) switch with a parallel structure enables Tx/Rx switching and exhibits high power-handling capability. Measurement results indicate that the T/R MMIC achieves a gain of 15.7–16.2 dB and an output 1 dB compression point (OP1 dB) of 17.3–19.2 dBm in Tx mode. In Rx mode, the circuit provides a gain of 18.9–21.2 dB with a noise figure ranging from 6.5 dB to 7.5 dB. Occupying a compact size of 2.3 ×2.8 mm<span><math><msup><mrow></mrow><mrow><mn>2</mn></mrow></msup></math></span>, the proposed MMIC demonstrates strong potential for 5G millimeter wave applications.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"163 ","pages":"Article 106758"},"PeriodicalIF":1.9,"publicationDate":"2025-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144313787","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Design and analysis of a ring-VCO based low jitter PLL 基于环形压控振荡器的低抖动锁相环的设计与分析

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-06-13 DOI: 10.1016/j.mejo.2025.106771

Wei Zou , Jionghui Zhang , Zhengwang Cheng , Mei Wang , Li Zhang , Xuecheng Zou

引用次数: 0

A PLL-based capacitance-to-voltage (C-to-V) converter for permittivity measurement sensors 基于锁相环的电容-电压（c -v）转换器，用于介电常数测量传感器

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-06-13 DOI: 10.1016/j.mejo.2025.106754

Surya Varchasvi Devaraj , Reddygari Bhupal Dheeraj , Khalid Shaikh, Parth Makode, Monika, Laxmeesha Somappa, Maryam Shojaei Baghini

{"title":"A PLL-based capacitance-to-voltage (C-to-V) converter for permittivity measurement sensors","authors":"Surya Varchasvi Devaraj , Reddygari Bhupal Dheeraj , Khalid Shaikh, Parth Makode, Monika, Laxmeesha Somappa, Maryam Shojaei Baghini","doi":"10.1016/j.mejo.2025.106754","DOIUrl":"10.1016/j.mejo.2025.106754","url":null,"abstract":"<div><div>A fully integrated sensing system is proposed for a wide-band capacitive-to-voltage converter (C2V). The system utilizes a differential delay cell voltage-controlled oscillator (VCO) incorporated in a phase-locked loop (PLL). The PLL controls the VCO operation frequency, and the PLL’s control voltage varies with the capacitance across the VCO. This control voltage is sensed to extract the capacitance and the corresponding permittivity. In comparison to the existing techniques, the proposed PLL C2V converter offers digital programmability with a wide operating frequency of 0.1 GHz–1 GHz, a low power consumption of 9.78 mW, a 20 ms response time, and a capacitance range of 0.3 pF–30 pF with an offset of 4.5 pF. The fully integrated PLL C2V converter is fabricated in 65 nm MM CMOS and occupies 0.0173 <span><math><msup><mrow><mi>mm</mi></mrow><mrow><mn>2</mn></mrow></msup></math></span> of active area. The PLL C2V converter is tested with a digitally tunable RF capacitor PE64102 emulating the sensor capacitor and can accurately measure capacitance with an error of <span><math><mo>±</mo></math></span> <span><math><mrow><mi>1.98</mi><mtext>%</mtext></mrow></math></span>. The PLL C2V ASIC is further integrated with a capacitive soil moisture sensor and is demonstrated for soil moisture sensing applications. The soil moisture measurements with the proposed system showed it can accurately estimate the moisture content with an error of −1.08% to 2.51%.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"163 ","pages":"Article 106754"},"PeriodicalIF":1.9,"publicationDate":"2025-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144313788","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A 12-bit 2GS/s current-steering DAC with 27 mW power consumption in 28 nm CMOS 一个12位2GS/s电流转向DAC，功耗为27mw，采用28nm CMOS

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-06-12 DOI: 10.1016/j.mejo.2025.106756

Beiqi Duan , Junyan Bi , Hao Xu , Guoyu Li , Yechen Tian , Na Yan

引用次数: 0

Research on fuzzy control based background calibration of pipelined ADCs 基于模糊控制的流水线adc背景标定研究

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-06-10 DOI: 10.1016/j.mejo.2025.106748

Luotian Wu, Honghui Deng, Jiashen Li, Muqi Li, Long Li, Runhui Chen, Yongsheng Yin

{"title":"Research on fuzzy control based background calibration of pipelined ADCs","authors":"Luotian Wu, Honghui Deng, Jiashen Li, Muqi Li, Long Li, Runhui Chen, Yongsheng Yin","doi":"10.1016/j.mejo.2025.106748","DOIUrl":"10.1016/j.mejo.2025.106748","url":null,"abstract":"<div><div>This article proposes a rapid and novel background calibration algorithm employing fuzzy control to address nonlinear errors in pipelined analog-to-digital converters (ADCs). The algorithm employs a fuzzy controller, which is designed by analyzing the relationship between the sub-ADC quantization codes of the pipelined ADCs and the corresponding errors. The fuzzy rule base is initialized in two-stage and dynamically updated during runtime, thereby fully leveraging the fitting capabilities of the fuzzy controller. The adoption of a symmetric structure for the fuzzy rule base has been shown to reduce the quantity of rules by half, thereby simplifying structural complexity and accelerating the construction process. The fuzzy control is implemented in Xilinx Kintex-7 FPGA and applied to the online calibration of a 14-bit 61 MS/s pipelined ADC. The simulation results demonstrate that the SNDR is enhanced by 29.4 dB and SFDR is improved by 40.3 dB after calibration. Furthermore, the construction of the fuzzy rule base requires only 1,000 samples to complete.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"163 ","pages":"Article 106748"},"PeriodicalIF":1.9,"publicationDate":"2025-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144270990","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Design and analysis of an ultra-wideband quad-mode quad-core oscillator with mode ambiguity elimination 一种模式模糊消除的超宽带四模四核振荡器设计与分析

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-06-10 DOI: 10.1016/j.mejo.2025.106767

Ge Wang , Ruixue Ding , Dingtao Zeng , Feng Bu , Yuan Gao , Depeng Sun , Shubin Liu

引用次数: 0

A 2 MHz-BW 80.6 dB-SNDR 95.9 dB-SFDR 2nd-order noise-shaping SAR using open-loop Gm-R amplifier 采用开环Gm-R放大器的2 MHz-BW 80.6 dB-SNDR 95.9 dB-SFDR二阶噪声整形SAR

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-06-10 DOI: 10.1016/j.mejo.2025.106749

Hao Xu , Congyang Sun , Shuai Liu , Guoyu Li , Yechen Tian , Na Yan

引用次数: 0

Analysis of leakage mechanisms in Fully Depleted Silicon-on-Insulator (FD SOI) devices 全耗尽绝缘体上硅（FD SOI）器件泄漏机理分析

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-06-10 DOI: 10.1016/j.mejo.2025.106769

Manoj Kumar Paramasivam

引用次数: 0

A 76.05 dB SNDR 0.303 mW Noise-Shaping SAR ADC with data weighted averaging in 40 nm CMOS 基于40 nm CMOS的76.05 dB SNDR 0.303 mW降噪SAR ADC

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-06-10 DOI: 10.1016/j.mejo.2025.106750

Zhijie Yang, Jie Sun

引用次数: 0

A transformer-based current reuse CMOS Armstrong VCO using gm-boosted technique 一种基于变压器的电流复用CMOS阿姆斯阿姆斯特朗压控振荡器

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-06-09 DOI: 10.1016/j.mejo.2025.106753

Tao Tan, Xiuping Li, Yubing Li, Shuai Wu, Bohai Fang, Changkai Zhang, Yujian Qin

{"title":"A transformer-based current reuse CMOS Armstrong VCO using gm-boosted technique","authors":"Tao Tan, Xiuping Li, Yubing Li, Shuai Wu, Bohai Fang, Changkai Zhang, Yujian Qin","doi":"10.1016/j.mejo.2025.106753","DOIUrl":"10.1016/j.mejo.2025.106753","url":null,"abstract":"<div><div>This paper presents a low power LC Armstrong VCO based on current reuse structure and <span><math><msub><mrow><mi>g</mi></mrow><mrow><mi>m</mi></mrow></msub></math></span>-boosted technique with a 5-port 3-coil transformer. The applied current reuse structure converts the traditional parallel cross-coupled transistor pair into a series PMOS-NMOS pair, reducing the overall power consumption. Moreover, the phase-shifted between <span><math><msub><mrow><mi>i</mi></mrow><mrow><mi>d</mi><mi>s</mi></mrow></msub></math></span> and <span><math><msub><mrow><mi>V</mi></mrow><mrow><mi>d</mi><mi>s</mi></mrow></msub></math></span> of the transistors reduces power dissipated in the devices by leveraging the large language model optimization results. The proposed <span><math><msub><mrow><mi>g</mi></mrow><mrow><mi>m</mi></mrow></msub></math></span>-boosted technique is employed by two transistors in series and capacitors in parallel. With the proposed topology, the negative conductance, oscillation amplitude, and the Perturbation Projection Vector (PPV) are improved, thus better phase noise performance. The 5-port 3-coil transformer integrates all inductors to minimizing the area. Fabricated in GlobalFoundries 0.11-<span><math><mi>μ</mi></math></span>m CMOS technology, the VCO achieves a power consumption of 2 mW at a 1.2 V supply voltage, with a phase noise of −114.5 dBc/Hz @1MHz offset at 11.2 GHz.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"163 ","pages":"Article 106753"},"PeriodicalIF":1.9,"publicationDate":"2025-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144270991","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0