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High-throughput true random number generator based on a dual-input oscillation circuit 基于双输入振荡电路的高吞吐量真随机数发生器
IF 1.9 3区 工程技术
Microelectronics Journal Pub Date : 2024-08-11 DOI: 10.1016/j.mejo.2024.106367
{"title":"High-throughput true random number generator based on a dual-input oscillation circuit","authors":"","doi":"10.1016/j.mejo.2024.106367","DOIUrl":"10.1016/j.mejo.2024.106367","url":null,"abstract":"<div><p>The rapid development in the fields of information encryption, key generation, and algorithm initialization requires an increasing rate of true random numbers, making it necessary to design a fast true random number generator. In this work, a dual-mode conversion high throughput true random number generator (TRNG) based on a dual input oscillating XOR circuit (DIO-XOR) is proposed, which is designed using DIO-XOR, combined with a MUX selects the feedback mode of the whole circuit: self-feedback/mutual feedback. It is verified by automatic layout and routing on Xilinx Artix-7 and Kintex-7 FPGAs with a throughput rate of 650Mbps, which is achieved with low hardware overhead, and passes the entropy estimation test suite, NIST SP800-90B, as well as TESTU01 with high entropy, the sequences generated in the temperature-voltage fluctuation test pass the NIST SP800-22 test with good robustness.</p></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-08-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141979399","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
High-k2eff AlSc0.095N-based two-dimensional coupled mode resonators with transducer design toward 5G application 基于 AlSc0.095N 的高 k2eff 二维耦合模式谐振器与面向 5G 应用的换能器设计
IF 1.9 3区 工程技术
Microelectronics Journal Pub Date : 2024-08-09 DOI: 10.1016/j.mejo.2024.106364
{"title":"High-k2eff AlSc0.095N-based two-dimensional coupled mode resonators with transducer design toward 5G application","authors":"","doi":"10.1016/j.mejo.2024.106364","DOIUrl":"10.1016/j.mejo.2024.106364","url":null,"abstract":"<div><p>This paper presents the two-dimensional coupled mode resonators (TCMRs) based on 9.5 % scandium-doped aluminum nitride (AlScN) films. We report the design, fabrication, and characterization of 770 nm-thick AlSc<sub>0.095</sub>N TCMRs, which utilize the <em>e</em><sub>31</sub> and <em>e</em><sub>33</sub> piezoelectric coefficients to jointly excite the coupled mode with high electromechanical coupling coefficient (<em>k</em><sup>2</sup><sub><em>eff</em></sub>). The TCMRs with different electrical boundary conditions (TCMR-I and TCMR-II) are proposed, and the dependence of the resonant mode on the electrode period was studied. The effect of electrode duty factor (<em>DF</em>) on the resonator performance was explored, and both TCMR-Ⅰ and TCMR-II with <em>DF</em> = 0.5 exhibit the maximum <em>k</em><sup>2</sup><sub><em>eff</em></sub> value. Through measured characterization and simulation analysis, the effect of interdigitated transducer (IDT) thickness on resonator performance was studied. In addition, the equivalent electrical parameters of the prepared resonator were extracted using the MBVD equivalent circuit model. The <em>Q</em><sub><em>s</em></sub> values of TCMR-Ⅰ and TCMR-II fabricated in this paper can reach 1134 and 165, and the <em>k</em><sup>2</sup><sub><em>eff</em></sub> values can reach 3.5 % and 7.86 %, respectively.</p></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141953685","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Ohmic contacts to n-type SiC: Influence of Au and Ta intermediate layers 与 n 型碳化硅的欧姆接触：金和钽中间层的影响
IF 1.9 3区 工程技术
Microelectronics Journal Pub Date : 2024-08-08 DOI: 10.1016/j.mejo.2024.106361
{"title":"Ohmic contacts to n-type SiC: Influence of Au and Ta intermediate layers","authors":"","doi":"10.1016/j.mejo.2024.106361","DOIUrl":"10.1016/j.mejo.2024.106361","url":null,"abstract":"<div><p>In this study, the optimization of metal-semiconductor contacts to reduce the contact resistance of ohmic contacts on n-type 4H-SiC. The commonly used Ni/Au metal scheme served as a reference. We introduced two novel metal schemes: (i) incorporating a thin interfacial Au layer (2 nm) into Ni/Au, resulting in Au/Ni/Au, and (ii) introducing a thin intermediate barrier layer of Ta (20 nm) into Ni/Au, resulting in Ni/Ta/Au. Rapid thermal annealing (RTA) is performed at different temperatures and durations and the electrical characteristics of the contacts are measured. X-ray diffraction analysis was employed to investigate the intermediate phases formed during annealing. In the Au/Ni/Au metal scheme, the presence of Au at the interface promoted the formation of additional phases of nickel-silicide (Ni<sub>3</sub>Si and Ni<sub>3</sub>Si<sub>2</sub>). Compared to the traditional Ni/Au scheme, the modified metal schemes led to lower surface roughness and reduced contact resistance. Specific contact resistivity values are calculated, 2.2 × 10<sup>−5</sup> Ω-cm<sup>2</sup> for Ni/Au, 1.37 × 10<sup>−5</sup> Ω-cm<sup>2</sup> for Au/Ni/Au, and 4.84 × 10<sup>−5</sup> Ω-cm<sup>2</sup> for Ni/Ta/Au. This research offers valuable insights for the selection of metal schemes in designing ohmic contacts on n-type SiC, with potential applications in various semiconductor device technologies.</p></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141953389","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Power-efficient wideband programmable pseudo differential ring oscillator CP-PLL 高能效宽带可编程伪差分环振荡器 CP-PLL
IF 1.9 3区 工程技术
Microelectronics Journal Pub Date : 2024-08-08 DOI: 10.1016/j.mejo.2024.106365
{"title":"Power-efficient wideband programmable pseudo differential ring oscillator CP-PLL","authors":"","doi":"10.1016/j.mejo.2024.106365","DOIUrl":"10.1016/j.mejo.2024.106365","url":null,"abstract":"<div><p>A power-efficient, wide-band, programmable pseudo-differential ring-oscillator charge-pump phase-locked loop (CP-PLL) is proposed. The ring-VCO, characterized by its low power consumption and broadband, is achieved based on a feedforward pseudo-differential configuration. The linearity of ring-VCO is improved by using the source negative feedback topology. Through the rail-to-rail operatingamplifier clamping current source, the current matching accuracy is improved to realize a high-performance CP circuit. The results show that the output frequency range of the phase-locked loop is 0.6–6 GHz at a 1.2 V supply voltage, and the power consumption is 1.372 mW at 5 GHz with a lock-up time of 1.72 μs and RMS jitter of 9.3 ps. The power consumption is as low as 0.643 mW at 2.5 GHz and 1.067 mW at 4 GHz, and the final layout area is 0.00716 mm<sup>2</sup>. The implemented CP-PLL can be used effectively in wireless RF communication system of NB-IoT and intelligent edge computing scenario.</p></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141993708","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Machine learning driven global optimisation framework for analog circuit design 机器学习驱动的模拟电路设计全局优化框架
IF 1.9 3区 工程技术
Microelectronics Journal Pub Date : 2024-08-06 DOI: 10.1016/j.mejo.2024.106362
{"title":"Machine learning driven global optimisation framework for analog circuit design","authors":"","doi":"10.1016/j.mejo.2024.106362","DOIUrl":"10.1016/j.mejo.2024.106362","url":null,"abstract":"<div><p>We propose a machine learning-driven optimisation framework for analog circuit design in this paper. Machine learning based global offline surrogate models, with the circuit design parameters as the input, are built in the design space for the analog circuits under study and are used to guide the optimisation algorithm towards an optimal circuit design, resulting in faster convergence and reduced number of spice simulations. Multi-layer perceptron and random forest regressors are employed to predict the required design specifications of the analog circuit. Multi-layer perceptron classifiers are used to predict the saturation condition of each transistor in the circuit. We validate the proposed framework using three circuit topologies—a bandgap reference, a folded cascode operational amplifier, and a two-stage operational amplifier. The simulation results show better optimum values and lower standard deviations for fitness functions after convergence, with a reduction in spice calls by 56%, 59%, and 83% when compared with standard approaches in the three test cases considered in the study.</p></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-08-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141979398","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 40 mV cold-start circuit with bootstrap clock booster for thermoelectric energy harvesting 用于热电能量采集的带自举时钟助推器的 40 mV 冷启动电路
IF 1.9 3区 工程技术
Microelectronics Journal Pub Date : 2024-08-06 DOI: 10.1016/j.mejo.2024.106360
{"title":"A 40 mV cold-start circuit with bootstrap clock booster for thermoelectric energy harvesting","authors":"","doi":"10.1016/j.mejo.2024.106360","DOIUrl":"10.1016/j.mejo.2024.106360","url":null,"abstract":"<div><p>In this paper, a cold-start circuit with bootstrap clock booster for thermoelectric energy harvesting is proposed. The relationship between enhancing the clock swing amplitude and lowering the input voltage for a cross-coupled charge pump (CCCP) is analyzed. Based on the existing one-shot start-up mechanism, a series-parallel bootstrap clock booster (SP-BCB) for boosting the clock amplitude is proposed to lower the cold start voltage. Besides, a dynamic threshold MOS (DTMOS) technique for dynamically changing the threshold voltage of MOS transistors is used to achieve better conduction and leakage current suppression. The complete circuit is simulated in a 0.18-μm CMOS process. The simulated results demonstrate that using DTMOS technique and enhancing the clock swing amplitude can contribute to lowering the input voltage. The SP-BCB-based CCCP can boost the input voltage from 40 mV to 668 mV for a 500 MΩ load in 100 m s, which meets the requirement for one-shot start-up mechanism, realizing 40-mV integrated cold start for thermoelectric energy harvesting (TEH).</p></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-08-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142044934","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A PVT-robust Gm-R-based residue amplifier with folded positive feedback technique 采用折叠正反馈技术的基于 PVT 的 Gm-R 残差放大器
IF 1.9 3区 工程技术
Microelectronics Journal Pub Date : 2024-08-06 DOI: 10.1016/j.mejo.2024.106352
{"title":"A PVT-robust Gm-R-based residue amplifier with folded positive feedback technique","authors":"","doi":"10.1016/j.mejo.2024.106352","DOIUrl":"10.1016/j.mejo.2024.106352","url":null,"abstract":"<div><p>This paper presents a process, voltage and temperature (PVT) robust Gm-R-based residue amplifier (RA). The proposed folded positive feedback (FPF) technique facilitates a high open-loop gain of 49.2 dB and gain bandwidth of 30.6<!--> <!-->GHz without employing multiple cascading stages or cascode devices, consuming only 8.2<!--> <!-->mW. The PVT robustness of the proposed RA is self-adapted, addressing the requirement of bias-generating circuitry. Transistor level design and simulations are implemented based on a 28 nm CMOS process. Configured in closed-loop, the proposed RA demonstrates a relative gain variation smaller than 5% and a fast settling time of 400<!--> <!-->ps. The simulated gain linearity exceeds 9<!--> <!-->bit with a 440<!--> <!-->m<span><math><msub><mrow><mi>V</mi></mrow><mrow><mi>p</mi><mi>p</mi></mrow></msub></math></span> output swing, yielding an improved trade-off between speed and accuracy in nanoscale RA designs.</p></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-08-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141963225","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A demultiplexer-based dual-path switching true random number generator 基于解复用器的双路径切换真随机数发生器
IF 1.9 3区 工程技术
Microelectronics Journal Pub Date : 2024-08-06 DOI: 10.1016/j.mejo.2024.106363
{"title":"A demultiplexer-based dual-path switching true random number generator","authors":"","doi":"10.1016/j.mejo.2024.106363","DOIUrl":"10.1016/j.mejo.2024.106363","url":null,"abstract":"<div><p>This paper presents a demultiplexer (DEMUX) based dual-path switching true random number generator (TRNG). Unlike the classical single chain TRNG, the proposed TRNG utilizes DEMUXs to separate the cumulative jitter and occurrence of metastability in two paths. It also uses Ring Oscillator (RO) to increase the uncertainty of path switching time. Therefore, two sources of entropy are skilfully combined and no post-processing circuitry is required. The proposed structure is implemented on Xilinx Virtex-7 FPGA development board. The experimental results show that the proposed structure is able to achieve a high throughput of 500 Mbps with 33 Look-up Tables (LUTs) and 4 Flip-Flops (FFs). This effectively improves the throughput with high quality entropy and low hardware overhead.</p></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-08-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142001904","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Performance enhancement of 4H-SiC superjunction trench MOSFET with extended high-K dielectric 采用扩展高介电质的 4H-SiC 超结沟槽 MOSFET 的性能提升
IF 1.9 3区 工程技术
Microelectronics Journal Pub Date : 2024-08-05 DOI: 10.1016/j.mejo.2024.106359
{"title":"Performance enhancement of 4H-SiC superjunction trench MOSFET with extended high-K dielectric","authors":"","doi":"10.1016/j.mejo.2024.106359","DOIUrl":"10.1016/j.mejo.2024.106359","url":null,"abstract":"<div><p>This paper proposes a 4H-SiC superjunction trench MOSFET with extended high-K dielectric under metal gate (EHK SJ-TMOS). The characteristics of EHK SJ-TMOS include the use of the high-K (HK) dielectric as the gate dielectric and the extension of the HK dielectric as a deep trench into the N-type drift region. The extended HK trench effectively modulates the electric field distribution in the SJ drift region, which improves the breakdown voltage (<em>BV</em>). The introduction of HK dielectric also assists in depleting the SJ drift region, which enables the drift region of EHK SJ-TMOS to use a higher doping concentration, thereby reducing <em>R</em><sub><em>on,sp</em></sub>. Furthermore, the application of high-K gate dielectric alleviates the high gate oxide electric field problem in conventional SiC superjunction trench MOSFETs (SiC SJ-TMOS). The simulation results demonstrate that EHK SJ-TMOS exhibits a 59.2 % reduction in <em>R</em><sub><em>on,sp</em></sub>, a 2.4 % increase in <em>BV</em>, and a 156.5 % improvement in the <em>FOM</em> (<em>FOM</em> = <em>BV</em><sup><em>2</em></sup>/<em>R</em><sub><em>on,sp</em></sub>) compared to the SiC SJ-TMOS, indicating enhanced performance.</p></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-08-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141962710","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 1–6.5 Gbps dual-loop CDR design with Coarse-fine Tuning VCO and modified DQFD 采用粗微调 VCO 和改进型 DQFD 的 1-6.5 Gbps 双环 CDR 设计
IF 1.9 3区 工程技术
Microelectronics Journal Pub Date : 2024-08-05 DOI: 10.1016/j.mejo.2024.106355
{"title":"A 1–6.5 Gbps dual-loop CDR design with Coarse-fine Tuning VCO and modified DQFD","authors":"","doi":"10.1016/j.mejo.2024.106355","DOIUrl":"10.1016/j.mejo.2024.106355","url":null,"abstract":"<div><p>A dual-loop CDR (Clock and Data Recovery) is presented to recover digital data from 1 to 6.5 Gbps. The presented frequency acquisition technique is based on full rate clock architecture. By utilizing modified Digital Quadri-correlator Frequency Detector (DQFD) and Frequency Increment/Decrement Control circuit, the lock-in range is improved. Furthermore, the issue of state loss during wide frequency range detection is successfully mitigated. The inclusion of two control wires in the Coarse-fine Tuning VCO enables the utilization of separate loop filters in the dual loops, resulting in a more effective reduction of noise and jitter. Utilizing a 40-nm CMOS process, the presented CDR design has been implemented. The post-layout simulation results at 6.5 Gbps shows a P2P and root-mean-square jitter values are 17.1 ps and 5.79 ps, respectively, for the retimed data.</p></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-08-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141953388","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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