Microelectronics Journal最新文献_第5页

A linearized PVT-robust FVF input buffer with triode transconductance feedback achieving SFDR > 90 dB at 500-MHz input 具有三极管跨导反馈的线性化pvt鲁棒FVF输入缓冲器，在500-MHz输入时实现SFDR > 90 dB

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-07-22 DOI: 10.1016/j.mejo.2025.106802

Junye Su, Shubin Liu, Haolin Han

{"title":"A linearized PVT-robust FVF input buffer with triode transconductance feedback achieving SFDR > 90 dB at 500-MHz input","authors":"Junye Su, Shubin Liu, Haolin Han","doi":"10.1016/j.mejo.2025.106802","DOIUrl":"10.1016/j.mejo.2025.106802","url":null,"abstract":"<div><div>This paper presents a high-linearity input buffer leveraging triode-transconductance feedback (TTF) flipped voltage followers for RF sampling data converters. The proposed source follower incorporates a triode-biased transistor to enhance linearity by cancelling the third harmonic distortion (HD3). Under a 1-GS/s sampling rate, the buffer achieves SFDR of 90.4 dB and SNDR of 74.6 dB at Nyquist frequency. A dedicated constant-<span><math><msub><mrow><mi>g</mi></mrow><mrow><mi>m</mi></mrow></msub></math></span> current source and channel split bias circuits are also introduced in this work to accommodate process, voltage, and temperature (PVT) conditions. Simulated under 5corners, −40 to125  <span><math><mo>±</mo></math></span> 2.5<span><math><mtext>%</mtext></math></span>, the prototype buffer designed in 28-nm CMOS maintains SFDR <span><math><mo>≥</mo></math></span> 80 dB, improved by approximately 30 dB. With a power consumption of 23.54mW, the proposed buffer attains a figure of merit (FoM) of 173.0 dB, demonstrating an excellent trade-off among linearity, bandwidth and power consumption.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"164 ","pages":"Article 106802"},"PeriodicalIF":1.9,"publicationDate":"2025-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144686336","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A bit-level loosely coupled computing-in-memory macro with early termination 具有提前终止的位级松散耦合内存计算宏

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-07-21 DOI: 10.1016/j.mejo.2025.106796

Junchuan Gu , Yang Chen , Wenwei Wang , Akash Kumar , Salim Ullah , Kejie Huang , Haibin Shen

{"title":"A bit-level loosely coupled computing-in-memory macro with early termination","authors":"Junchuan Gu , Yang Chen , Wenwei Wang , Akash Kumar , Salim Ullah , Kejie Huang , Haibin Shen","doi":"10.1016/j.mejo.2025.106796","DOIUrl":"10.1016/j.mejo.2025.106796","url":null,"abstract":"<div><div>Computing-in-memory (CIM) has emerged as a promising solution for artificial intelligence (AI) edge devices. However, conventional bit-slicing CIM designs necessitate the availability of all input bits prior to the computation process. This tight coupling between input and output bits results in a substantial need for temporary storage and leads to significant output delays. In this article, we propose a bit-level loosely coupled (BLC) computation scheme for CIM macros, which reduces the bit widths of temporary data to 1 bit, thereby saving register demand. Accuracy and computational efficiency is further enhanced by zero detection scheme and early termination scheme. A CIM macro is designed to implement BLC multiply and accumulate (MAC) computation. Compared with the 8-bit quantized model, our proposed scheme incurs only 0.29% and 0.52% accuracy loss on AlexNet and ResNet20 (CIFAR-10 dataset), respectively. In a 40-nm process, the power consumption of our CIM macro is 3.54 mW (256 x 256 at 8-bit) and the computing-power ratio is 37.01 TOPS/W.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"164 ","pages":"Article 106796"},"PeriodicalIF":1.9,"publicationDate":"2025-07-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144724499","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A 12.5–50 GHz frequency synthesizer for Software-Defined Radios in 40-nm CMOS 用于40纳米CMOS软件定义无线电的12.5-50 GHz频率合成器

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-07-18 DOI: 10.1016/j.mejo.2025.106806

Yanhui Wu , Shize Duan , Zhenrong Li , Jianbo Qiu , Jiayi Li , Xi Ji , Jinsong Tu , Jie Li , Cong Li , Gangzi Chen , Qiong Li

{"title":"A 12.5–50 GHz frequency synthesizer for Software-Defined Radios in 40-nm CMOS","authors":"Yanhui Wu , Shize Duan , Zhenrong Li , Jianbo Qiu , Jiayi Li , Xi Ji , Jinsong Tu , Jie Li , Cong Li , Gangzi Chen , Qiong Li","doi":"10.1016/j.mejo.2025.106806","DOIUrl":"10.1016/j.mejo.2025.106806","url":null,"abstract":"<div><div>In this paper, we propose a dual-channel SDR frequency synthesizer based on a fractional CP-PLL architecture, designed to achieve continuous frequency coverage from 12.5 to 50 GHz. An <em>LC</em>-VCO array is used to generate fundamental frequency signals ranging from 12.5 to 25 GHz, and a frequency doubler extends the frequency range to 25 to 50 GHz. An inductive biasing technique is introduced to eliminate phase noise deterioration due to resistive thermal noise while supporting implicit common-mode resonance to further optimize phase noise performance. The chip is fabricated using 40-nm CMOS technology. Measurement results indicate a phase noise of −109.7 dBc/Hz at a 1 MHz offset from the 12.5 GHz carrier, while the integrated jitter (from 12 kHz to 20 MHz) is less than 100 fs over the entire frequency range. The chip consumes 80.5 mW of power with a 1.1 V supply and occupies an area of 3.7 mm × 3 mm. In addition, the chip integrates an RF power amplifier to amplify fundamental and octave signals, improving driving capability.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"165 ","pages":"Article 106806"},"PeriodicalIF":1.9,"publicationDate":"2025-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144772613","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Design of quasi-reflectionless filter based on hybrid absorption architecture 基于混合吸收结构的准无反射滤波器设计

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-07-16 DOI: 10.1016/j.mejo.2025.106810

Zichen Guo , Zhiyu Wang , Junjie Xie , Xinyu Wang , Siyuan Ma , Annan Xu , Minyi Yang , Xi Guo , Jiongjiong Mo , Faxin Yu

{"title":"Design of quasi-reflectionless filter based on hybrid absorption architecture","authors":"Zichen Guo , Zhiyu Wang , Junjie Xie , Xinyu Wang , Siyuan Ma , Annan Xu , Minyi Yang , Xi Guo , Jiongjiong Mo , Faxin Yu","doi":"10.1016/j.mejo.2025.106810","DOIUrl":"10.1016/j.mejo.2025.106810","url":null,"abstract":"<div><div>In this paper, a quasi-reflectionless (QRL) filter based on hybrid absorption architecture is proposed and analyzed. The filter adopts a modular design philosophy, comprising a quasi-complementary diplexer (QCD) network formed by conventional filters with frequency complementarity and a reflection-absorption compensation (RAC) network integrating phase shifters and lossy power combiners<u>.</u> The incorporation of the RAC network enhances the reflectionless frequency range of QCD network. This enables conventional complementary bandpass and bandstop filters to be rapidly transformed into QRL filters with ultra-wideband absorption capabilities, without strict complementary responses or designated feeding structure designs<u>.</u> To demonstrate this approach, a 24–28 GHz quasi-reflectionless bandpass filter (QRL-BPF) consisting of multi-mode microstrip resonators is simulated and fabricated using GaAs integrated passive device (IPD) process. Measured results show that the proposed QRL-BPF achieves a reflectionless relative bandwidth (RFBW) of 150 % with reflection absorption level approaching −10dB.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"164 ","pages":"Article 106810"},"PeriodicalIF":1.9,"publicationDate":"2025-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144702543","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A pre-congestion-aware deterministic-adaptive hybrid routing (PcaDAHR) algorithm for network-on-chip 片上网络的预拥塞感知确定性自适应混合路由（PcaDAHR）算法

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-07-16 DOI: 10.1016/j.mejo.2025.106811

Ning Ji, Yintang Yang

引用次数: 0

Comprehensive analysis of gate voltage and temperature stresses induced threshold voltage instability for 1200V DT SiC MOSFET through experiment and simulation 通过实验和仿真，综合分析了栅极电压和温度应力对1200V DT SiC MOSFET阈值电压不稳定的影响

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-07-14 DOI: 10.1016/j.mejo.2025.106807

Tao Liu , Hui Li , Rongyao Ma , Zhiyu Wang , Qian Liu , Hao Wu , Jian Shen , Juan Luo , Hao Zhong , Shengdong Hu

{"title":"Comprehensive analysis of gate voltage and temperature stresses induced threshold voltage instability for 1200V DT SiC MOSFET through experiment and simulation","authors":"Tao Liu , Hui Li , Rongyao Ma , Zhiyu Wang , Qian Liu , Hao Wu , Jian Shen , Juan Luo , Hao Zhong , Shengdong Hu","doi":"10.1016/j.mejo.2025.106807","DOIUrl":"10.1016/j.mejo.2025.106807","url":null,"abstract":"<div><div>Gate voltage and temperature stresses induced threshold voltage (<em>V</em><sub>TH</sub>) shifts on double trench (DT) SiC MOSFET are comprehensively investigated by experiment and TCAD simulation. Measured results show that the maximum <em>V</em><sub>TH</sub> shift is approximately 660.17 mV with a gate voltage (<em>V</em><sub>GS</sub>) of 20 V and a temperature (<em>T</em>) of 150 °C at a stress duration of 11280 s. Comprehensive simulated results uncover the quantitative relationships among <em>V</em><sub>TH</sub> shifts, trap energy levels, and densities. A simulation model considering both oxide electron traps and hole traps is developed. Based on the model, the simulated <em>V</em><sub>TH</sub> shift is 535.25 mV with <em>V</em><sub>GS</sub> = 20 V and <em>T</em> = 150 °C. The relative errors between the simulated and experimental results are −18.9 % (<em>V</em><sub>GS</sub> = 20 V, <em>T</em> = 150 °C), −10 % (<em>V</em><sub>GS</sub> = 20 V, <em>T</em> = 50 °C), −1.9 % (<em>V</em><sub>GS</sub> = 7 V, <em>T</em> = 125 °C), and 3.3 % (<em>V</em><sub>GS</sub> = 7 V, <em>T</em> = 50 °C) at the stress time of 11280 s, respectively.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"164 ","pages":"Article 106807"},"PeriodicalIF":1.9,"publicationDate":"2025-07-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144686337","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

An efficient dehazing accelerator by fusing dark channel prior and guided filter 一种融合暗通道先验和引导滤波器的高效除雾加速器

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-07-12 DOI: 10.1016/j.mejo.2025.106782

Tianyi Lv , Wei Mao , Zhenmin Li, Gaoming Du, Xiaolei Wang, Wei Ni, Duoli Zhang

{"title":"An efficient dehazing accelerator by fusing dark channel prior and guided filter","authors":"Tianyi Lv , Wei Mao , Zhenmin Li, Gaoming Du, Xiaolei Wang, Wei Ni, Duoli Zhang","doi":"10.1016/j.mejo.2025.106782","DOIUrl":"10.1016/j.mejo.2025.106782","url":null,"abstract":"<div><div>Real-time dehazing can enhance the applicability of machine vision in practical applications in rainy and foggy weather conditions. Existing real-time dehazing methods suffer from incomplete dehazing and slow processing speeds for high-definition video dehazing. This paper proposed an efficient dehazing accelerator based on the fusion of two modular components. One is the proposed edge-based adaptive guided filtering module, which can enhance image edges. By classifying the edge types of the fog map, different sizes of filter windows are used correspondingly, thereby reducing the halo phenomenon caused by the previous guided filter and high-boost filter. The other is Hardware-friendly Dark Channel Prior (H-DCP) designed for hardware deployment, which can restore the color of the defogged image and reduce chromatic aberration with less resources consumption. The proposed fast accelerator can meet the requirements of real-time defogging, using multiplexing modules and custom divider circuits to reduce resource occupation and improve operating speed. It can achieve defogging processing of 1920 × 1080 images at a frame rate of 40.0.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"164 ","pages":"Article 106782"},"PeriodicalIF":1.9,"publicationDate":"2025-07-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144702542","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A new concept high-k GaN FinFET with integrated SBD breaking the unipolar limit of GaN and realizing excellent reverse recovery performance 集成SBD的新概念高k GaN FinFET打破了GaN的单极极限，实现了优异的反向恢复性能

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-07-11 DOI: 10.1016/j.mejo.2025.106798

Moufu Kong , Qizhi Feng , Hongfei Deng , Zhaoyu Ai , Mingliang Yang , Ning Yu , Bingke Zhang , Bo Yi , Hongqiang Yang

{"title":"A new concept high-k GaN FinFET with integrated SBD breaking the unipolar limit of GaN and realizing excellent reverse recovery performance","authors":"Moufu Kong , Qizhi Feng , Hongfei Deng , Zhaoyu Ai , Mingliang Yang , Ning Yu , Bingke Zhang , Bo Yi , Hongqiang Yang","doi":"10.1016/j.mejo.2025.106798","DOIUrl":"10.1016/j.mejo.2025.106798","url":null,"abstract":"<div><div>Conventional GaN Fin field-effect transistors (FinFETs) exhibit high specific on-resistance (<em>R</em><sub>on,sp</sub>), which imposes fundamental limitations on the development of high performance vertical GaN devices. Furthermore, the high ionization energy of p-type dopants and low impurity activation rates in GaN make superjunction (SJ) structures a significant challenge for GaN power devices. This work proposes a novel high-<em>k</em> GaN FinFET structure with an integrated Schottky barrier diode (SBD). By replacing the conventional p-GaN pillar in the superjunction (SJ) design with a high-<em>k</em> pillar, the proposed structure significantly increases the doping concentration in the drift region and optimizes the electric field distribution. As a result, it simultaneously achieves both high breakdown voltage (BV) and ultralow specific on-resistance (<em>R</em><sub>on,sp</sub>).TCAD simulations demonstrate that the proposed device achieves a high breakdown voltage of over 2000 V and a low <em>R</em><sub>on,sp</sub> of 0.34 mΩ cm<sup>2</sup>, which exhibits a remarkable 67 % reduction in <em>R</em><sub>on,sp</sub> compared with the conventional device while maintaining an equivalent breakdown voltage. This substantial improvement significantly enhances the figure of merit (FOM) of 11.7 GW/cm<sup>2</sup>, which breaks the “the Unipolar Limit of GaN”. The proposed high-<em>k</em> GaN FinFET provides a new paradigm for high-voltage GaN applications with significant potential. Compared to the conventional structure, this new concept device also achieves faster switching speeds, as well as realizing excellent reverse recovery characteristics.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"164 ","pages":"Article 106798"},"PeriodicalIF":1.9,"publicationDate":"2025-07-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144605657","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A low-latency event-trigger-circuit-shared pixel for synchronous dynamic vision sensor 一种用于同步动态视觉传感器的低延迟事件触发电路共享像素

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-07-11 DOI: 10.1016/j.mejo.2025.106781

Boyang Zheng, Xiaopei Shi, Kaiming Nie, Jiangtao Xu

{"title":"A low-latency event-trigger-circuit-shared pixel for synchronous dynamic vision sensor","authors":"Boyang Zheng, Xiaopei Shi, Kaiming Nie, Jiangtao Xu","doi":"10.1016/j.mejo.2025.106781","DOIUrl":"10.1016/j.mejo.2025.106781","url":null,"abstract":"<div><div>To reduce the pixel size in dynamic vision sensors (DVSs), this paper presents a low-latency pixel structure based on event trigger circuit sharing. It is achieved by sharing an event trigger circuit through a column of pixels. During row selection stage, the pixel circuit outputs the voltages of two different moments to the column-shared circuit under timing control. The voltages are differentially amplified and compared, thereby enabling event triggering and readout. Using a 110 nm 1P4M FSI process, the proposed pixel structure achieves a compact 15<span><math><mo>×</mo></math></span> 15 <span><math><mi>μ</mi></math></span>m<sup>2</sup> size with a fill factor of 36%. Compared to conventional DVS pixels in the same process, the pixel size is reduced by 60%. With the contrast threshold set at 16%, the DVS pixel operates in a detectable photocurrent range of 310 fA-310 nA by using a high quantum efficiency “P+/N+/N-well/P-sub” photodiode structure, providing a dynamic range of 120 dB. The event transmission latency ranges from 1.023 ms (0.1 lux) to 3.292 <span><math><mi>μ</mi></math></span>s (100k lux), with a reduction of 82% in low-light conditions.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"164 ","pages":"Article 106781"},"PeriodicalIF":1.9,"publicationDate":"2025-07-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144614720","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Active-matrix organic light-emitting diode pixel circuit with compensation for threshold voltage shift and IR-drop effect 有源矩阵有机发光二极管像素电路，补偿阈值电压偏移和红外下降效应

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-07-09 DOI: 10.1016/j.mejo.2025.106803

Hong Jiang , Han Wang , Feng Zhang , Xinguo Ma , Wei Wang , Fu Li

引用次数: 0