Microelectronics Journal最新文献_第5页

A 16-channel, multi-level Time-to-Digital Converter for high precision ToF measurement 用于高精度ToF测量的16通道，多级时间-数字转换器

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-04-12 DOI: 10.1016/j.mejo.2025.106669

Ziwei Zhao , Ran Zheng , Jia Wang , Xiaomin Wei , Feifei Xue , Ruiguang Zhao , Yongcai Hu

引用次数: 0

A 10–15 GHz four-antenna phased array beamforming receiver with eight-simultaneous beams in 55-nm CMOS Technology 基于55纳米CMOS技术的10-15 GHz四天线相控阵波束形成接收机

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-04-11 DOI: 10.1016/j.mejo.2025.106670

Bin Li , Shubo Dun , Qinghui Song , Haifu Zhang , Xiaodong Cui , Hanyang Luo , Geliang Yang

{"title":"A 10–15 GHz four-antenna phased array beamforming receiver with eight-simultaneous beams in 55-nm CMOS Technology","authors":"Bin Li , Shubo Dun , Qinghui Song , Haifu Zhang , Xiaodong Cui , Hanyang Luo , Geliang Yang","doi":"10.1016/j.mejo.2025.106670","DOIUrl":"10.1016/j.mejo.2025.106670","url":null,"abstract":"<div><div>This paper demonstrates a 10–15 GHz four-antenna phased array beamforming receiver with eight-simultaneous beams. The full-connected multibeam architecture is adopted to maximize the beamforming gain. To mitigate the design complexity and large chip area-consumption caused by the multibeam combination, a compact active multibeam combining technique is proposed, which features current-domain phase shifted signal combining and compact passive signal connection network. Implemented in a 55-nm CMOS process, the receiver consumes a current of 1100 mA with a 1.2 V supply. From 10 to 15 GHz, the receiver achieves a 360° phase shifting range with a 6-bit resolution, and the root mean square (RMS) phase is less than 3°. The 6-bit attenuator in each output channel achieves less than 0.4 dB root mean square (RMS) gain error. The receiver demonstrates a gain of 20 dB (20.5 dB), a 5.5 dB (7.6 dB) noise figure, and an input-referred 1 -dB gain compression point (IP<sub>1dB</sub>) of −20 dBm (−22 dBm) at 10 GHz (15 GHz), respectively. The chip size, including pads, is only 3.6 × 5.4 mm<sup>2</sup>.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"160 ","pages":"Article 106670"},"PeriodicalIF":1.9,"publicationDate":"2025-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143825961","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Algorithm of the inter-channel mismatches calibration in TIADC TIADC信道间失配校正算法

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-04-11 DOI: 10.1016/j.mejo.2025.106688

Chengjie Wang, Shengmin Yang, Yuhua Liang

{"title":"Algorithm of the inter-channel mismatches calibration in TIADC","authors":"Chengjie Wang, Shengmin Yang, Yuhua Liang","doi":"10.1016/j.mejo.2025.106688","DOIUrl":"10.1016/j.mejo.2025.106688","url":null,"abstract":"<div><div>To address the issues in existing algorithms related to calibration accuracy, hardware utilization, or the trade-off between calibration speed and accuracy, this paper proposes a fully digital background calibration method including parallel and serial architecture, which can reduce hardware utilization and supports the expansion to an arbitrary number of channels.</div><div>We performed board-level verification on an FPGA for the proposed algorithm. The results of the FPGA board-level verification match those of the MATLAB behavioral simulation. At an input frequency of 0.025 <span><math><mrow><msub><mi>f</mi><mi>s</mi></msub></mrow></math></span>, the SNDR and SFDR improved by 8.59 dB and 11.54 dB, respectively, and the effective number of bits (ENOB) increased by 1.42 bits. At an input frequency of 0.05 <span><math><mrow><msub><mi>f</mi><mi>s</mi></msub></mrow></math></span>, the SNDR and SFDR improved by 20.89 dB and 13.65 dB, respectively, and the ENOB increased by 2.27 bits. At an input frequency of 0.2 <span><math><mrow><msub><mi>f</mi><mi>s</mi></msub></mrow></math></span>, the SNDR and SFDR improved by 11.86 dB and 17.89 dB, respectively, and the ENOB increased by 1.97 bits. The output layout size was 500 μm × 550 μm.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"160 ","pages":"Article 106688"},"PeriodicalIF":1.9,"publicationDate":"2025-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143825962","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A 15.4 nW, 59 ppm/∘C CMOS voltage reference circuit with process and temperature compensation 15.4 nW， 59 ppm/ C的CMOS电压基准电路，带有工艺和温度补偿

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-04-10 DOI: 10.1016/j.mejo.2025.106664

Annan Wang , Yuchen Sun , Zhang Zhang

{"title":"A 15.4 nW, 59 ppm/∘C CMOS voltage reference circuit with process and temperature compensation","authors":"Annan Wang , Yuchen Sun , Zhang Zhang","doi":"10.1016/j.mejo.2025.106664","DOIUrl":"10.1016/j.mejo.2025.106664","url":null,"abstract":"<div><div>This article presents a low-power CMOS voltage reference circuit with process and temperature compensation. The design employs a current source circuit to generate a bias current that shows process and temperature variations complementary to those of the output voltage of the stacked diode connected MOS transistor (SDMT). By adjusting the transistor size and current mirror ratio, the bias current exhibits the opposite temperature coefficient (TC) and process skew to that of the SDMT, thus achieving process and temperature compensation. This voltage reference is implemented using a standard 65 nm CMOS process, with a core chip area of <span><math><mrow><mn>5500</mn><mspace></mspace><mi>μ</mi><msup><mrow><mi>m</mi></mrow><mrow><mn>2</mn></mrow></msup></mrow></math></span>. At room temperature, measurements were taken on 18 chips, with an average output reference voltage of 335.7 mV and a standard deviation of 1.02 mV (<span><math><mi>σ</mi></math></span>/<span><math><mi>μ</mi></math></span> = 0.31%). Over the temperature range of −40 °C to 120 °C, the average temperature coefficient is 59 ppm/<span><math><msup><mrow></mrow><mrow><mo>∘</mo></mrow></msup></math></span>C. Within the supply voltage range of 0.7 V–1.5 V, the line sensitivity is 0.21%/V, the power supply rejection ratio (PSRR) at 100 Hz is −50 dB, and the power consumption at 0.7 V is 15.4 nW.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"160 ","pages":"Article 106664"},"PeriodicalIF":1.9,"publicationDate":"2025-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143821089","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

An adaptive background light rejection technique with integrated laser interference filter for direct time-of-flight sensors 用于直接飞行时间传感器的集成激光干扰滤波器自适应背景光抑制技术

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-04-10 DOI: 10.1016/j.mejo.2025.106675

Huazhen Wang, Kaiming Nie, Jiangtao Xu

{"title":"An adaptive background light rejection technique with integrated laser interference filter for direct time-of-flight sensors","authors":"Huazhen Wang, Kaiming Nie, Jiangtao Xu","doi":"10.1016/j.mejo.2025.106675","DOIUrl":"10.1016/j.mejo.2025.106675","url":null,"abstract":"<div><div>To suppress the varying background light and laser interference in direct time-of-flight (DToF) sensors, this paper presents an adaptive pixel-to-pixel coincidence detection and smart time gating technique. Each pixel contains one single-photon avalanche diode and shares signals with surrounding pixels. The coincidence detection level is automatically adjusted based on the coincidence of the signal and noise. Time gating is generated based on the output of a time-to-digital converter. The technique is implemented through circuit design using a 110 nm process and validated through behavioral modeling and circuit simulations. Simulation results show the technique achieves success rates (SRs) exceeding 60% and signal-to-noise ratios (SNRs) above 3 under background light levels ranging from 10 to 100 klux. It maintains SRs exceeding 50% and SNRs above 2 for target distances ranging from 0.5 to 46.5 m. It ensures signal-to-interference ratios above 1 under laser interference. This technique enables DToF sensors to operate under varying background light levels and effectively filters out laser interference.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"160 ","pages":"Article 106675"},"PeriodicalIF":1.9,"publicationDate":"2025-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143821178","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Study of DRAM data failure mechanism and mitigation scheme under the combination of TID and row hammer TID和行锤联合作用下DRAM数据失效机理及缓解方案研究

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-04-10 DOI: 10.1016/j.mejo.2025.106689

Zhenlin Wu , Haibin Wang , Yujie Qian , Xiaofeng Huang , Xiaoshuai Peng , Hai Huang

{"title":"Study of DRAM data failure mechanism and mitigation scheme under the combination of TID and row hammer","authors":"Zhenlin Wu , Haibin Wang , Yujie Qian , Xiaofeng Huang , Xiaoshuai Peng , Hai Huang","doi":"10.1016/j.mejo.2025.106689","DOIUrl":"10.1016/j.mejo.2025.106689","url":null,"abstract":"<div><div>In this study, we utilize the TCAD simulation tool to investigate the combined impact of total ionizing dose (TID) and row hammer effects on dynamic random access memory (DRAM) data integrity. The results show that TID increases the device's leakage current and induces the formation of acceptor-type traps, which facilitate electron capture and release. We identify the gate oxide and the channel as key vulnerabilities in the failure process. The channel serves as the primary site for electron migration, while the gate oxide acts as the main source of positive charge. To address these vulnerabilities, we propose an innovative P-type uniform heavy doping strategy, which blocks electron leakage paths by heavy doping beneath the channel. Compared to traditional methods, this strategy not only avoids the expansion of the gate oxide area and the enhancement of the electric field but also significantly improves the reliability of DRAM in radiation environments, increasing the row hammer threshold (N<sub>RH</sub>) by a factor of four.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"160 ","pages":"Article 106689"},"PeriodicalIF":1.9,"publicationDate":"2025-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143821179","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Automated Solutions for CNN Model Acceleration on Mobile Platforms 移动平台上CNN模型加速的自动化解决方案

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-04-10 DOI: 10.1016/j.mejo.2025.106691

Yuhao Liu , Yanhua Ma

{"title":"Automated Solutions for CNN Model Acceleration on Mobile Platforms","authors":"Yuhao Liu , Yanhua Ma","doi":"10.1016/j.mejo.2025.106691","DOIUrl":"10.1016/j.mejo.2025.106691","url":null,"abstract":"<div><div>This paper presents an FPGA-based convolutional neural network (CNN) accelerator designed to enhance computational efficiency and flexibility for resource-constrained platforms. While FPGAs offer high energy efficiency and adaptability, large-scale CNN deployments face challenges such as computational intensity, diverse kernel sizes, and hardware limitations. To address these issues, we propose an accelerator optimized across four convolution loop dimensions, ensuring efficient resource utilization and streamlined data transmission. Our architecture incorporates three key innovations: (1) Loop-optimized computation framework, which dynamically balances parallelism between inner and outer loops, maximizing data reuse and preventing performance bottlenecks; (2) Customized data layout and memory management, mitigating bandwidth limitations and ensuring high computational efficiency under varying workloads; (3) Automated parameter optimization, integrating reinforcement learning with Python-based search algorithms to explore design configurations, optimizing performance for specific applications. The accelerator is validated on ZCU111 and ZCU102 FPGA platforms using ResNet-50, ResNet-152, and VGG-16. Results show that 69.9% of computations achieve ≥80% efficiency, 47.1% surpass 90%, and 19.2% exceed 95% efficiency, demonstrating superior performance over prior FPGA implementations. Compared to existing designs, our approach achieves a 64.0% increase in efficiency and a 36.5% boost in throughput, while maintaining flexibility across network architectures. These findings highlight the potential of automated optimization techniques in FPGA-based CNN acceleration.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"160 ","pages":"Article 106691"},"PeriodicalIF":1.9,"publicationDate":"2025-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143821177","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A 0.000159 mm2 2.9 μm-pitch 4.3fJ/Conv 6-bit SAR ADC for high throughput parallel readout of analog SRAM computing-in-memory 一个0.000159 mm2 2.9 μm-pitch 4.3fJ/Conv 6位SAR ADC，用于内存中模拟SRAM计算的高吞吐量并行读出

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-04-08 DOI: 10.1016/j.mejo.2025.106685

Lin Wu , Lichen Feng , Yunlong Liu , Libo Qian , Yinshui Xia , Zhangming Zhu

引用次数: 0

A broadband high gain driver amplifier with gain compensation for current-reuse 一种带增益补偿电流复用的宽带高增益驱动放大器

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-04-07 DOI: 10.1016/j.mejo.2025.106673

Tingwei Gong, Zhiqun Cheng, Xuefei Xuan, Chao Le, Zhiwei Zhang, Daopeng Li, Bangjie Zheng

{"title":"A broadband high gain driver amplifier with gain compensation for current-reuse","authors":"Tingwei Gong, Zhiqun Cheng, Xuefei Xuan, Chao Le, Zhiwei Zhang, Daopeng Li, Bangjie Zheng","doi":"10.1016/j.mejo.2025.106673","DOIUrl":"10.1016/j.mejo.2025.106673","url":null,"abstract":"<div><div>This paper proposes a broadband high-gain driver amplifier (DA) monolithic microwave integrated circuit (MMIC) for wireless communication. Current reuse and a new gain compensation method are applied in the design of proposed DA MMIC to achieve the performance of high gain, low in-band gain ripple, and high output power across a wide operational bandwidth. To ensure the power capability, both the output stage and the driver stage are designed based on load-pull analysis, which inevitably results in gain non-uniformity. However, with the application of the proposed gain compensation method to the first-stage amplification circuit, the gain non-uniformity of both the driver and output stages is ultimately compensated for. For verification, the proposed DA is fabricated in 0.15 μm gallium arsenide (GaAs) high electron mobility transistor (pHEMT) technology with a chip area of 4.2 mm<sup>2</sup>. The measured results demonstrate a small signal gain over 32 dB, a saturated output power over 26 dBm, a power gain greater than 30 dB, an power added efficiency (PAE) exceeding 25 %, and in-band gain ripple of approximately ±0.8 dB from 2 to 18 GHz. The proposed DA MMIC has a static power consumption of 0.95 W and dynamic power consumption less than 1.3 W.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"160 ","pages":"Article 106673"},"PeriodicalIF":1.9,"publicationDate":"2025-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143800188","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A 10-bit 4 GS/s Pipelined-SAR ADC based on loop-unrolled and partial-interleaving 一种基于环展开和部分交错的10位4gs /s管道sar ADC

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-04-07 DOI: 10.1016/j.mejo.2025.106683

Weimin Zhou , Zhe Li , Hongzhi Liang , Li Dang , Ruixue Ding , Shubin Liu , Zhangming Zhu

引用次数: 0