A 0.029-mm2 11.5-ENOB 8.05-kHz BW voltage Fold-Shrink SAR ADC for cochlear implant

IF 1.9 3区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronics Journal Pub Date : 2025-09-10 DOI:10.1016/j.mejo.2025.106885

Hongbo Gu , Wei Zhang , Lei Liao , Zhihui Qin

{"title":"A 0.029-mm2 11.5-ENOB 8.05-kHz BW voltage Fold-Shrink SAR ADC for cochlear implant","authors":"Hongbo Gu , Wei Zhang , Lei Liao , Zhihui Qin","doi":"10.1016/j.mejo.2025.106885","DOIUrl":null,"url":null,"abstract":"<div><div>This work introduces a voltage Fold-Shrink Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC). It is characterized by an all-resistor divider Digital-to-Analog Converter (DAC) which keeps a proportional voltage for the Most Significant Bit (MSB) sub-Digital-to-Analog Converter (subDAC). In addition, it utilizes scaling capacitors to execute a fold-and-shrink technique for the Least Significant Bit (LSB) subDAC, thereby yielding the combined output of the DAC. A 12-bit SAR ADC prototype has been developed using a 90 nm CMOS process. It occupies an area of 0.029 mm<sup>2</sup> and is designed for Cochlear Implant applications. Operating at 1 V with a sampling rate of 1 MS/s, this ADC demonstrates an effective number of bits (ENOB) of 11.5, a signal-to-noise-and-distortion ratio (SNDR) of 71.22 dB, a bandwidth of 8.05 kHz, and a power consumption of 0.85 μW. Both MSB and LSB subDACs are configured as 6-bit with a 16-fold scaling capacitor for LSB voltage shrinkage. A newly developed low-power dynamic comparator (CMP) augmented by placing a capacitor at the output of MSB subDAC is utilized to minimize kick-back noise, which highlights the design's focus on both power efficiency and noise suppression.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"166 ","pages":"Article 106885"},"PeriodicalIF":1.9000,"publicationDate":"2025-09-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Microelectronics Journal","FirstCategoryId":"5","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S1879239125003340","RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}

引用次数: 0

Abstract

This work introduces a voltage Fold-Shrink Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC). It is characterized by an all-resistor divider Digital-to-Analog Converter (DAC) which keeps a proportional voltage for the Most Significant Bit (MSB) sub-Digital-to-Analog Converter (subDAC). In addition, it utilizes scaling capacitors to execute a fold-and-shrink technique for the Least Significant Bit (LSB) subDAC, thereby yielding the combined output of the DAC. A 12-bit SAR ADC prototype has been developed using a 90 nm CMOS process. It occupies an area of 0.029 mm² and is designed for Cochlear Implant applications. Operating at 1 V with a sampling rate of 1 MS/s, this ADC demonstrates an effective number of bits (ENOB) of 11.5, a signal-to-noise-and-distortion ratio (SNDR) of 71.22 dB, a bandwidth of 8.05 kHz, and a power consumption of 0.85 μW. Both MSB and LSB subDACs are configured as 6-bit with a 16-fold scaling capacitor for LSB voltage shrinkage. A newly developed low-power dynamic comparator (CMP) augmented by placing a capacitor at the output of MSB subDAC is utilized to minimize kick-back noise, which highlights the design's focus on both power efficiency and noise suppression.

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一种用于人工耳蜗的0.029 mm2 11.5-ENOB 8.05 khz BW电压折叠收缩SAR ADC

本文介绍了一种电压折缩逐次逼近寄存器（SAR）模数转换器（ADC）。它的特点是一个全电阻分压器数模转换器（DAC），它为最高有效位（MSB）子数模转换器（子DAC）保持一个比例电压。此外，它利用缩放电容器对最低有效位（LSB）子DAC执行折叠和收缩技术，从而产生DAC的组合输出。采用90纳米CMOS工艺开发了一个12位SAR ADC原型。它占地面积为0.029平方毫米，专为人工耳蜗应用而设计。该ADC工作电压为1 V，采样率为1 MS/s，有效位数（ENOB）为11.5，信噪比（SNDR）为71.22 dB，带宽为8.05 kHz，功耗为0.85 μW。MSB和LSB子dac都配置为6位，带有16倍缩放电容器，用于LSB电压收缩。新开发的低功耗动态比较器（CMP）通过在MSB子dac的输出端放置电容来增强，以最大限度地减少回退噪声，这突出了该设计对功率效率和噪声抑制的关注。

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来源期刊

Microelectronics Journal 工程技术-工程：电子与电气

CiteScore

4.00

自引率

27.30%

发文量

222

审稿时长

43 days

期刊介绍： Published since 1969, the Microelectronics Journal is an international forum for the dissemination of research and applications of microelectronic systems, circuits, and emerging technologies. Papers published in the Microelectronics Journal have undergone peer review to ensure originality, relevance, and timeliness. The journal thus provides a worldwide, regular, and comprehensive update on microelectronic circuits and systems. The Microelectronics Journal invites papers describing significant research and applications in all of the areas listed below. Comprehensive review/survey papers covering recent developments will also be considered. The Microelectronics Journal covers circuits and systems. This topic includes but is not limited to: Analog, digital, mixed, and RF circuits and related design methodologies; Logic, architectural, and system level synthesis; Testing, design for testability, built-in self-test; Area, power, and thermal analysis and design; Mixed-domain simulation and design; Embedded systems; Non-von Neumann computing and related technologies and circuits; Design and test of high complexity systems integration; SoC, NoC, SIP, and NIP design and test; 3-D integration design and analysis; Emerging device technologies and circuits, such as FinFETs, SETs, spintronics, SFQ, MTJ, etc. Application aspects such as signal and image processing including circuits for cryptography, sensors, and actuators including sensor networks, reliability and quality issues, and economic models are also welcome.