Microelectronics Journal最新文献

Thermoreflectance property of gallium nitride 氮化镓的热反射特性

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2024-11-05 DOI: 10.1016/j.mejo.2024.106468

Yusa Chen , Meizhang Wu , Jianghui Mo , Yan Liu , Yuwei Zhai , Wengang Wu , Aihua Wu , Faguo Liang

{"title":"Thermoreflectance property of gallium nitride","authors":"Yusa Chen , Meizhang Wu , Jianghui Mo , Yan Liu , Yuwei Zhai , Wengang Wu , Aihua Wu , Faguo Liang","doi":"10.1016/j.mejo.2024.106468","DOIUrl":"10.1016/j.mejo.2024.106468","url":null,"abstract":"<div><div>Based on the principle of thermoreflectance (TR) and experimental data, we have determined the TR coefficients of GaN in the visible and near-ultraviolet spectrum range. The results indicate that the TR coefficient of GaN is larger, approximately <span><math><mrow><msup><mn>10</mn><mrow><mo>−</mo><mn>3</mn></mrow></msup><msup><mi>K</mi><mrow><mo>−</mo><mn>1</mn></mrow></msup></mrow></math></span> when the illumination wavelength falls within the near-ultraviolet range. However, within the visible spectrum, the TR coefficient is low, ranging between <span><math><mrow><msup><mn>10</mn><mrow><mo>−</mo><mn>5</mn></mrow></msup><msup><mi>K</mi><mrow><mo>−</mo><mn>1</mn></mrow></msup></mrow></math></span> to <span><math><mrow><msup><mn>10</mn><mrow><mo>−</mo><mn>6</mn></mrow></msup><msup><mi>K</mi><mrow><mo>−</mo><mn>1</mn></mrow></msup></mrow></math></span>. This suggests that GaN is more responsive to temperature changes within the near-ultraviolet spectrum. The paper provides a physics-mechanism-based explanation for this phenomenon. These results have implications for the thermal design and analysis of GaN-based microelectronic devices.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142593589","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

3-D impedance matching network (IMN) based on through-silicon via (TSV) for RF energy harvesting system 基于硅通孔 (TSV) 的三维阻抗匹配网络 (IMN)，用于射频能量采集系统

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2024-11-05 DOI: 10.1016/j.mejo.2024.106467

Xiao Shi, Tian Qiang, Mengye Cai, Yanfeng Jiang

{"title":"3-D impedance matching network (IMN) based on through-silicon via (TSV) for RF energy harvesting system","authors":"Xiao Shi, Tian Qiang, Mengye Cai, Yanfeng Jiang","doi":"10.1016/j.mejo.2024.106467","DOIUrl":"10.1016/j.mejo.2024.106467","url":null,"abstract":"<div><div>Radio Frequency Energy Harvesting (RFEH) system can harvest radio frequency (RF) energy from the natural environment, showing potential applications to play the role of the battery in specific settings, such as outdoors or human body, demonstrating vast potential applications on the scenarios with difficulty to renew the traditional battery. In the RFEH system, Impedance Matching Network (IMN) consumes substantial amounts of metal wire and chip area in standard CMOS process and is not easy to be integrated into the monolithic substrate. The planar structure shows the shortcoming of large area and prominent parasitic influences, limiting its integration in the REFH system. The development of 3-D integrated circuit technology based on Through-Silicon Vias (TSV) offers a possible solution for RF passive devices. In the paper, a novel TSV-based 3-D IMN is designed. The capacitor is implemented with the TSV structure, while the inductor is designed with Redistribution Layer (RDL) spiral pattern. The co-design of 3D LC matching circuit shows the merits of the proposed solution, including high performance and compact size. It can be used as a technical solution for the integration of IMN in a monolithic CMOS RFEH system.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142593590","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A new method for temperature field characterization of microsystems based on transient thermal simulation 基于瞬态热模拟的微系统温度场表征新方法

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2024-11-02 DOI: 10.1016/j.mejo.2024.106464

Yanrong Pei , Wenchang Li , Jian Liu , Tianyi Zhang

{"title":"A new method for temperature field characterization of microsystems based on transient thermal simulation","authors":"Yanrong Pei , Wenchang Li , Jian Liu , Tianyi Zhang","doi":"10.1016/j.mejo.2024.106464","DOIUrl":"10.1016/j.mejo.2024.106464","url":null,"abstract":"<div><div>Microsystems face challenges such as high heat flux density and localized hot spots in the temperature field, significantly impacting their thermal reliability. Accurately and comprehensively characterizing the temperature field is a challenging problem in current research. We present a general high-order finite difference (GHOFD) algorithm for the high-accuracy numerical solution of the two-dimensional transient heat conduction equations (THCEs). The 10th-order GHOFD algorithm is accurate up to 10<sup>−7</sup> °C. Secondly, we present a viable approach for characterizing microsystems' steady-state and transient heat conduction mechanisms. We introduce two new characterization parameters: the gradient modulus and the heat flux direction factor (HFDF). The gradient modulus can more clearly characterize the magnitude of the gradient vector and quantitatively analyze the spatial position of the temperature field change in the microsystem. The HFDF can dynamically display the heat conduction process in the temperature field. Finally, using temperature field simulation and microsystem characterization, we have validated the effectiveness of the proposed method and new parameters.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142586119","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Study on the influence mechanism of gate oxide degradation on DM EMI signals in SiC MOSFET 栅极氧化物降解对 SiC MOSFET 中 DM EMI 信号的影响机制研究

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2024-10-30 DOI: 10.1016/j.mejo.2024.106460

Chao Dong, Sai Gao, Yulin Liu, Gengji Wang, Jinliang Yin, Mingxing Du

引用次数: 0

A column bus self-acceleration circuit for large array CMOS image sensor 用于大型阵列 CMOS 图像传感器的列总线自加速电路

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2024-10-30 DOI: 10.1016/j.mejo.2024.106458

Yu Sun, Changju Liu, Quanmin Chen, Jiangtao Xu

引用次数: 0

An analytical I-V model of SiC double-gate junctionless MOSFETs 碳化硅双栅极无结 MOSFET 的 I-V 分析模型

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2024-10-26 DOI: 10.1016/j.mejo.2024.106445

Yi Li , Tao Zhou , Zixuan Guo , Yuqiu Yang , Junyao Wu , Huan Cai , Jun Wang , Jungang Yin , Wenqing Huang , Miao Zhang , Nianxing Hou , Qin Liu , Linfeng Deng

{"title":"An analytical I-V model of SiC double-gate junctionless MOSFETs","authors":"Yi Li , Tao Zhou , Zixuan Guo , Yuqiu Yang , Junyao Wu , Huan Cai , Jun Wang , Jungang Yin , Wenqing Huang , Miao Zhang , Nianxing Hou , Qin Liu , Linfeng Deng","doi":"10.1016/j.mejo.2024.106445","DOIUrl":"10.1016/j.mejo.2024.106445","url":null,"abstract":"<div><div>Silicon carbide(SiC) double gate junctionless metal oxide semiconductor field-effect transistors(DG JL MOSFETs) have attracted significant attention due to their ideal high temperature characteristics and radiation resistance. Therefore, it is meaningful to exploit an I-V model for SiC DG JL MOSFETs. In this article, we make a linear approximation to describe the relationship between the surface mobile charge density and the surface electron concentration of the device. Based on this approximation and using the one-dimensional Poisson’s equation, we solve for the potential distribution of a SiC DG JL MOSFET in the subthreshold region. From this solution, we derived a functional relationship between the surface mobile charge density in the channel and the channel quasi-Fermi potential. Then we successfully developed a unified I-V model for the SiC DG JL MOSFETs. Based on the drain to source current calculation formula, the calculation expressions for the device’s transconductance and output conductance are derived. By comparing our model with the results from the two-dimensional numerical simulation software Silvaco Atlas, our model’s calculations closely match the two-dimensional numerical simulation results from the subthreshold region to the accumulation region. This model has reference significance for SiC DG JL MOSFETs in the high temperature electronic circuit application field.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142552473","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

An improved 4H-SiC trench MOS barrier Schottky diode with current spreading layer and low resistance layer 带有电流扩散层和低阻层的改进型 4H-SiC 沟槽 MOS 势垒肖特基二极管

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2024-10-24 DOI: 10.1016/j.mejo.2024.106451

Hai-tao Ge , Wang-zi-xuan Zhen , Cheng-hao Yu , Masayuki yamamoto , Wen-sheng Zhao , Hao-min Guo , Xiao-dong Wu

{"title":"An improved 4H-SiC trench MOS barrier Schottky diode with current spreading layer and low resistance layer","authors":"Hai-tao Ge , Wang-zi-xuan Zhen , Cheng-hao Yu , Masayuki yamamoto , Wen-sheng Zhao , Hao-min Guo , Xiao-dong Wu","doi":"10.1016/j.mejo.2024.106451","DOIUrl":"10.1016/j.mejo.2024.106451","url":null,"abstract":"<div><div>This paper investigates an improved trench MOS barrier Schottky (TMBS) structure with extra double epitaxial layers (DE-TMBS) based on the conventional TMBS (C-TMBS) featuring a high-doped N-type current spreading layer (CSL) and a high-doped low resistance layer (LRL). Compared to the C-TMBS, the CSL in the improved structure is grown on the N-type drift region, and the LRL is extended on the CSL. According to the numerical simulations and analytical models, the specific on-resistance (<em>R</em><sub>on,sp</sub>) of DE-TMBS can be significantly reduced compared to the conventional one. This is primarily due to the high doping concentration in CSL, which effectively lowers both the JFET resistance and spreading resistance. Additionally, the increased doping concentration in LRL reduces the channel resistance and JFET resistance. Moreover, the doping concentration and thickness of CSL and LRL are optimized to maximize the figure of merit (FOM), that <em>R</em><sub>on,sp</sub> is reduced by 40.9 % and the FOM (<em>BV</em><sup><em>2</em></sup>/<em>R</em><sub>on,sp</sub>) is improved by 67.9 % compared to the C-TMBS structure.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142529350","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

An 11-bit two-step column-shared ADC based on Flash/SS architecture for CMOS image sensor 基于闪存/SS 架构的 11 位两步列共享 ADC，适用于 CMOS 图像传感器

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2024-10-24 DOI: 10.1016/j.mejo.2024.106444

Qiang Zhao , Jitao Xu , Chunhui Fan , Ziming Wang , Ruitong Hu , Xin Li , Zhigang Li , Licai Hao , Chunyu Peng , Zhiting Lin , Xiulong Wu

{"title":"An 11-bit two-step column-shared ADC based on Flash/SS architecture for CMOS image sensor","authors":"Qiang Zhao , Jitao Xu , Chunhui Fan , Ziming Wang , Ruitong Hu , Xin Li , Zhigang Li , Licai Hao , Chunyu Peng , Zhiting Lin , Xiulong Wu","doi":"10.1016/j.mejo.2024.106444","DOIUrl":"10.1016/j.mejo.2024.106444","url":null,"abstract":"<div><div>Traditional single-slope analog-to-digital converter (SS ADC) faces a speed limitation that constrains the exposure speed of CMOS image sensors (CIS). To enhance the conversion speed of SS ADCs used in high frame rate CIS, a two-step column-shared ADC based on Flash/SS architecture is proposed. The ADC design approach is based on the concepts of time compression and multi-column sharing. On one hand, a Flash ADC and differential ramps are introduced while two comparators are multiplexed to enhance the conversion speed. On the other hand, a multi-column shared design is employed in some circuits to reduce the average area and power consumption per column. Under a design environment of 256 × 256 pixel resolution, the simulation results show that the row time of ADC is <span><math><mrow><mn>5</mn><mo>.</mo><mn>4</mn><mspace></mspace><mi>μ</mi><mi>s</mi></mrow></math></span>, the column-level average power consumption is 129.5 <span><math><mi>μ</mi></math></span>W, and the FoMa is 527 fJ/step. Compared to the conventional 11-bit two-step SS ADC, the proposed ADC not only optimizes quantization speed but also simplifies the redundant calibration structure.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142552472","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A fast-switching and short-circuit enhanced SOI LIGBT with a Self-Driving P-MOS 采用自驱动 P-MOS 的快速开关和短路增强型 SOI LIGBT

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2024-10-24 DOI: 10.1016/j.mejo.2024.106447

Ao Wu , Weizhong Chen , Xiangwei Zeng , Zikai Wei , Haishi Wang , Zeheng Wang

{"title":"A fast-switching and short-circuit enhanced SOI LIGBT with a Self-Driving P-MOS","authors":"Ao Wu , Weizhong Chen , Xiangwei Zeng , Zikai Wei , Haishi Wang , Zeheng Wang","doi":"10.1016/j.mejo.2024.106447","DOIUrl":"10.1016/j.mejo.2024.106447","url":null,"abstract":"<div><div>A fast-switching and short-circuit enhanced LIGBT with integrated Self-Driving P-channel MOS, named SDP-LIGBT is demonstrated by the TCAD SENTAURUS. The SDP consists of P + Emitter (Drain), N-type Carrier Store (N-CS Substrate) and P-shield (Source), and the gate of the SDP (PG) is shortly connected with the P + Emitter, thus the V<sub>PG,S</sub> equals V<sub>DS</sub>. Consequently, the SDP can be triggered on with saturate state without extra control signal. At the forward conduction, the SDP is automatically turned on with the increased V<sub>CE</sub>, then the saturation current is remarkably decreased due to division of LIGBT part and SDP part. Moreover, the N-CS substrate of the SDP acts as the hole barrier, which further decreased the on-state voltage drop (V<sub>ON</sub>). At the turn-off process, the SDP is also automatically turned on to extract excessive carriers with the increased bus voltage V<sub>CE</sub>, thus the turn-off speed and turn-off energy loss (E<sub>OFF</sub>) is effectively reduced. As a result, the SDP-LIGBT achieves superior trade-off relationship between V<sub>ON</sub> and E<sub>OFF</sub>. Furthermore, the short-circuit property of SDP-LIGBT is also significantly enhanced.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142561423","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Symbolic-functional representation inference for gate-level power estimation 用于门级功率估算的符号-函数表示推理

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2024-10-23 DOI: 10.1016/j.mejo.2024.106443

Zejia Lyu, Jizhong Shen

{"title":"Symbolic-functional representation inference for gate-level power estimation","authors":"Zejia Lyu, Jizhong Shen","doi":"10.1016/j.mejo.2024.106443","DOIUrl":"10.1016/j.mejo.2024.106443","url":null,"abstract":"<div><div>We propose SyfriPow, a method for estimating the vectorless average power consumption of gate-level circuits using sparse symbolic matrix inference. SyfriPow employs a probability-based approach, utilizing signal and transition probability to assess power consumption across various nodes. We present a symbolic representation probabilistic model for reasoning signal and transition probability through polynomial-based symbolic inference, incorporating a polynomial approximation strategy for spatial correlations and functional mapping for quick secondary computation. The model is sparsified with GPU accelerated polynomial sparse arithmetic engine, achieving sparse symbolic inference and sparse functional mapping which are implemented on Pytorch. Experiments demonstrate that SyfriPow achieves node-level probabilistic accuracy and significantly improves power accuracy compared to industrial software and academic algorithms, with an average power error of less than 4%. SFM efficiently analyzes large-scale circuits, processing up to 250k nodes in 100 s. SyfriPow can also function as an independent logic prediction engine, surpassing state-of-the-art algorithms in accuracy and speed.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142552474","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0