Microelectronics Journal最新文献

{"title":"SiC trench IGBT with n-barrier layer to enhance conductivity modulation","authors":"Ruixue Mai ,&nbsp;Xiaoli Tian ,&nbsp;Yu Yang ,&nbsp;Wei Wei ,&nbsp;Chengzhan Li ,&nbsp;Yun Bai ,&nbsp;Chengyue Yang ,&nbsp;Kaikai Wang ,&nbsp;Yidan Tang","doi":"10.1016/j.mejo.2025.106919","DOIUrl":"10.1016/j.mejo.2025.106919","url":null,"abstract":"<div><div>A novel silicon carbide (SiC) P-shield trench-gate insulated gate bipolar transistor with an n-barrier layer (NBL-IGBT) is proposed and investigated using TCAD simulations in this article. The n-barrier layer effectively suppresses hole extraction through the P-shield region, thereby enhancing conductivity modulation and reducing the on-state voltage drop (<em>V</em>_F). The simulation results indicate that the <em>V</em>_F is reduced from 6.55 V of the conventional grounded P-shield trench IGBT (G-IGBT) to 5.49 V of the proposed structure, which is reduced by 16.2 % at the collector current of 30 A. A good gate oxide protection (<em>E</em>_OX &lt; 3 MV/cm) and the dynamic performance can also be obtained with the proposed structure, resulting in superior overall static and dynamic figure of merits (<em>FOMS</em>), compared with the conventional single trench IGBT (ST-IGBT) and the G-IGBT. In addition, electro-thermal short circuit simulations reveal that the NBL-IGBT withstands short circuit condition for up to 35 μs, meeting typical IGBT robustness requirements. Furthermore, the fabrication technology of the new NBL-IGBT is compatible with the conventional structures. Therefore, the proposed structure demonstrates a great potential to achieve a better performance.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"166 ","pages":"Article 106919"},"PeriodicalIF":1.9,"publicationDate":"2025-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145268525","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Exploiting ShiftRow vulnerabilities in addition-chain masked AES: A novel wireless side-channel attack approach","authors":"Bijia Cao,&nbsp;Huanyu Wang,&nbsp;Tuo Deng,&nbsp;Dalin He,&nbsp;Zitian Huang,&nbsp;Junnian Wang","doi":"10.1016/j.mejo.2025.106866","DOIUrl":"10.1016/j.mejo.2025.106866","url":null,"abstract":"<div><div>The novel Wireless Side-Channel Attack (WSCA, A contactless side-channel analysis method using unintended EM emissions from target devices.), also known as screaming channel, presents a significant threat to widely deployed IoT edge devices due to its non-contact nature. This attack method has already made significant progress on implementations of unprotected AES. However, when it comes to the case with the presence of masking, the latest research results show that WSCAs require an impractical number of traces (nearly 300K) to barely recover the AES key remotely, which may still be far away from the optimum. In this paper, we go one step further to propose a <em>ShiftRow</em>-based WSCA framework to bypass the theoretical strength of the addition-chain based masking approach. By exploring all potential attack points of AES-128 with Rivain-Prouff (RP, A countermeasure against high-order side-channel attacks based on additive chain technology.) masking scheme, our experiments show that targeting on the <em>ShiftRow</em> procedure can significantly reduce the protective impact of RP masking on the algorithm. By collaboratively employing two deep-learning models, we successfully compromise an nRF52 SoC implementation of RP-masked AES-128, achieving an attack that is around 80% more efficient than the current state-of-the-art methods. In addition, we further exploit to which extent different combinations of attack points can help the attack on RP-masked AES implementations.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"166 ","pages":"Article 106866"},"PeriodicalIF":1.9,"publicationDate":"2025-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145268527","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Compact fully-unrolled architectures for AES based on merging and combining of linear operations","authors":"Xiaoqiang Zhang ,&nbsp;Zhiwei Peng ,&nbsp;Yingjie Ma ,&nbsp;Tianming Ni ,&nbsp;Xinnan Lin ,&nbsp;Xinxing Zheng","doi":"10.1016/j.mejo.2025.106917","DOIUrl":"10.1016/j.mejo.2025.106917","url":null,"abstract":"<div><div>In this paper, compact fully-unrolled architectures for Advanced Encryption Standard(AES)are proposed. In the proposed architectures, the linear operations on the same path between multiplicative inverses are merged to reduce the critical path delay(CPD), and then the merged linear operations are combined to optimize the area jointly. Therefore, both area and CPD are reduced by the merging and combining of linear operations. The optimization design methods of linear operations in encryption and decryption are discussed, respectively. And the effectiveness of proposed design methods is evaluated by both theoretical calculations and integrated circuit(IC)synthesis. The evaluation results show that, after merging and combining, about 42.86 %∼61.54 % CPD and 12.07 %∼24.71 % area of linear operations are reduced in theoretical calculations, and 48.64 %∼62.11 % CPD and 8.88 %∼26.88 % area are reduced in IC implementations. The designs of fully-unrolled AES architecture are further divided into 11 pipeline stages, and they are also evaluated by IC synthesis. The evaluation results show that the proposed pipelined AES designs can reduce about 11.58 %∼12.24 % area and increase about 32.42 %∼39.90 % speed in hardware implementations. Compared with previous works, our proposed AES designs have higher throughput/area efficiency.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"166 ","pages":"Article 106917"},"PeriodicalIF":1.9,"publicationDate":"2025-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145268530","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Quasi-elliptic bandpass filter based on novel coupling scheme with wide stop-band suppression","authors":"Ke Gong ,&nbsp;Hang Qian ,&nbsp;Xuehui Hu ,&nbsp;Chunfeng Fan ,&nbsp;Qing Liu","doi":"10.1016/j.mejo.2025.106922","DOIUrl":"10.1016/j.mejo.2025.106922","url":null,"abstract":"<div><div>A novel design method for wide-stopband quasi-elliptic bandpass filters (BPF) is proposed, which is realized by combining a stepped impedance resonator (SIR) and a phase coupling scheme. Using two folded SIRs in conjunction with a feed structure, the phase coupling scheme of electrical coupling paths with different electrical lengths is realized, and a two-pole quasi-elliptic BPF is realized. Then, two mixed coupling schemes of the classical trisection and phase coupling schemes are proposed, and two different types of wide-stopband quasi-elliptical BPFs are realized. The finite frequency transmission zeros (FTZs) and bandwidth (BW) of the proposed BPF can be effectively controlled by adjusting the structural parameters. For demonstration, two filters are designed, fabricated, and measured. The measured result is consistent with the simulated result, thereby validating the feasibility and universality of the proposed method. The proposed filter has the advantages of compact size, wide-stopband, and high selectivity.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"166 ","pages":"Article 106922"},"PeriodicalIF":1.9,"publicationDate":"2025-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145268528","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A broadband tunable high-selectivity bandpass filter and filtering power amplifier with continuous tunability and high stopband suppression level","authors":"Leidan Pan ,&nbsp;Yongle Wu ,&nbsp;Weimin Wang ,&nbsp;Shaobo Li ,&nbsp;Anna Piacibello ,&nbsp;Vittorio Camarchia","doi":"10.1016/j.mejo.2025.106911","DOIUrl":"10.1016/j.mejo.2025.106911","url":null,"abstract":"<div><div>In this paper, an unequal-width-three-coupled line (UWTCL) is applied for the design of a broadband tunable bandpass filter and filtering power amplifier (PA) using varactor diodes. A continuous tunability is achieved in both cases, adopting a single varactor diode in the passive filter and a common-cathode diodes matrix in the filtering PA. High coupling coefficient of the UWTCL enables wideband filtering and high out-of-band suppression level. The implemented filter achieves the high-selectivity filtering and wideband tunable range (1.6–2.4 GHz). Based on the filter, the tunable PA is developed with wideband impedance matching network (IMN) and a high-selectivity tunable output matching network (OMN), which offers improved filtering performances and facilitated tuning process. Measurements demonstrate the capability of the PA for frequency tuning from 1.7 to 2.2 GHz with good filtering performances, high efficiency, and a stopband suppression level exceeding 60 dB.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"166 ","pages":"Article 106911"},"PeriodicalIF":1.9,"publicationDate":"2025-09-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145226993","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A new double-trench gate 4H-SiC LDMOS with heterojunction and buffer layer for improved single-event burnout tolerance","authors":"Liqun Wang,&nbsp;Panpan Tang,&nbsp;Tong Liu","doi":"10.1016/j.mejo.2025.106909","DOIUrl":"10.1016/j.mejo.2025.106909","url":null,"abstract":"<div><div>As an important aerospace power device, silicon carbide (SiC) Lateral Diffused Metal Oxide Semiconductor (LDMOS) is susceptible to single-event burnout (SEB), which causes catastrophic damage when exposed to space radiation. The current work employs the Sentaurus TCAD simulations to present the SEB hardening method for a 1.2-kV 4H-SiC LDMOS. A double-trench gate 4H-SiC LDMOS containing low specific on-resistance (<span><math><msub><mrow><mi>R</mi></mrow><mrow><mi>o</mi><mi>n</mi><mo>,</mo><mi>s</mi><mi>p</mi></mrow></msub></math></span>) is proposed, significantly improving the device’s SEB threshold voltage (<span><math><msub><mrow><mi>V</mi></mrow><mrow><mi>S</mi><mi>E</mi><mi>B</mi></mrow></msub></math></span>). The proposed hardening design integrates multi-buffer layer with a heterojunction, impressively mitigating the high electric field at the drain area while suppressing the parasitic bipolar junction transistor (BJT). Besides, the device’s resistance is significantly decreased by designing the double-trench gate and current spreading layer (CSL). Accordingly, the constructed device achieves a (498 ± 11)% increase in <span><math><msub><mrow><mi>V</mi></mrow><mrow><mi>S</mi><mi>E</mi><mi>B</mi></mrow></msub></math></span> while reducing the <span><math><msub><mrow><mi>R</mi></mrow><mrow><mi>o</mi><mi>n</mi><mo>,</mo><mi>s</mi><mi>p</mi></mrow></msub></math></span> by (41.8 ± 1.8)% compared with the traditional 4H-SiC LDMOS. This significantly enhances the device’s reliability in radiation environments.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"166 ","pages":"Article 106909"},"PeriodicalIF":1.9,"publicationDate":"2025-09-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145226992","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Improving small signal modeling of GaN HEMTs with vector fitting method","authors":"Shaowei Wang ,&nbsp;Hongliang Lu ,&nbsp;Silu Yan ,&nbsp;Lin Cheng ,&nbsp;Yanghui Hu ,&nbsp;Longxiang He ,&nbsp;Liu Wang ,&nbsp;Yuming Zhang","doi":"10.1016/j.mejo.2025.106912","DOIUrl":"10.1016/j.mejo.2025.106912","url":null,"abstract":"<div><div>In the paper, an improved small-signal equivalent circuit model for GaN HEMTs is proposed for effectively capturing the high-frequency behavior of the device. In order to simulate the gain flatness of the device at high frequencies, the intrinsic capacitive coupling noise characteristic at high frequencies is considered in the proposed model. Also, in order to consider the phase delay phenomenon present in the device at high frequency conditions, additional current sources are added to the proposed model to simulate the phenomenon. In addition, the parameter values in the model are obtained by analyzing the rational function poles, residuals, and constants extracted by vector fitting (VF), which accurately models the <em>Y</em>-parameter characteristics of the device at high frequencies. The proposed model can accurately model the main physical properties of the device with good physical consistency and parameter interpretability. With the help of the VF, the model realizes high-precision matching of the <em>Y</em>-parameters of the device in a wide frequency band while significantly reducing the complexity of parameter extraction.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"166 ","pages":"Article 106912"},"PeriodicalIF":1.9,"publicationDate":"2025-09-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145268526","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 4.5–37 GHz ultra-wideband amplifier with asymmetric T-coil matching network in 0.18-μm SiGe BiCMOS technology","authors":"Hao Jiang ,&nbsp;Zenglong Zhao ,&nbsp;Nengxu Zhu ,&nbsp;Keping Wang ,&nbsp;Fanyi Meng","doi":"10.1016/j.mejo.2025.106913","DOIUrl":"10.1016/j.mejo.2025.106913","url":null,"abstract":"<div><div>This paper presents an ultra-wideband silicon-based amplifier designed to overcome the limitations of traditional transformer-based and distributed amplifier designs. The pro-posed amplifier is implemented in a 0.18 μm SiGe BiCMOS process and operates over a frequency range of 4.5–37 GHz. It features a single-stage differential topology using a common-emitter/common-base (CE-CB) configuration, with a series RC network for negative feedback. An asymmetric differential T-coil structure is employed for broadband input and output matching. Simulation results show return losses better than −10 dB across the full frequency range. The amplifier achieves a peak small-signal gain of 10.2 dB, with gain flatness of ±0.9 dB. It consumes less than 10 mW of DC power and delivers an OP1dB between 6 and 12.7 dBm. The core occupies only 0.14 mm², making it suitable for compact and low-power broadband systems.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"166 ","pages":"Article 106913"},"PeriodicalIF":1.9,"publicationDate":"2025-09-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145158633","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"An integrated GaN PNP Bipolar Junction Transistor for ESD applications","authors":"Pengfei Zhang ,&nbsp;Zhijia Zhao ,&nbsp;Gaoqiang Deng ,&nbsp;Xiaorong Luo ,&nbsp;Shuxiang Sun ,&nbsp;Yuxi Wei ,&nbsp;Jie Wei","doi":"10.1016/j.mejo.2025.106905","DOIUrl":"10.1016/j.mejo.2025.106905","url":null,"abstract":"<div><div>In this paper, a novel ESD protection circuit incorporating GaN PNP BJT (Bipolar Junction Transistor) is proposed and simulated. Compared with the conventional diodes, resistive and capacitive GaN ESD clamp, the proposed new ESD circuit exhibits superior discharging capability on same chip area, and its clamping voltage is reduced by at least 5.1V under 1.5A TLP (transmission line pulsing) current. Meanwhile, the proposed ESD circuit reduces the overshoot voltage during its discharging channel opens. After that the characteristics of GaN BJT is also investigated. By introducing a p-GaN back barrier layer, new p-GaN HEMT's conduction characteristics and breakdown voltage are improved compared to the conventional p-GaN HEMT.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"166 ","pages":"Article 106905"},"PeriodicalIF":1.9,"publicationDate":"2025-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145268529","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Low-Power and Area-Efficient CIM: An SRAM-based fully-digital computing-in-memory hardware acceleration processor with approximate adder tree for multi-precision sparse neural networks","authors":"Zhendong Fang,&nbsp;Yi Wang,&nbsp;Yaohua Xu","doi":"10.1016/j.mejo.2025.106903","DOIUrl":"10.1016/j.mejo.2025.106903","url":null,"abstract":"<div><div>Emergent architecture called computing-in-memory (CIM) effectively alleviates the issue of insufficient memory bandwidth and reduces energy consumption when accessing the on-chip buffer and registers. Some analog CIM macros designed to accelerate the neural network inference process have demonstrated significant improvements in both throughput and energy efficiency. These analog CIM macros are primarily utilized for neural networks with fixed activation and weight precision, which poses challenges for widespread deployment on edge devices with limited resources. On the other hand, analog macros exhibit heightened sensitivity to variations in process, voltage, and temperature, and the overhead associated with data conversion between analog and digital domains is unavoidable during calculation. Furthermore, exploring the sparse scheme compatible with CIM architecture can be beneficial in enhancing the energy efficiency of sparse neural network models. This article presents an SRAM-based fully-digital CIM hardware acceleration processor named Low-Power and Area-Efficient CIM (LPAE CIM), which combines the memory and computing macro of fully-digital architecture with peripheral storage and control modules to form a relatively comprehensive systematic structure. First, the sparsity of weight data is effectively utilized through a structured pruning method, and successive rows of the macro are opened flexibly for processing the sparsity of input activation. Second, the proposed area-friendly approximate adder tree replaces partial full adders with OR gates, reducing transistor count and promoting high-density integration of system-on-chip. Third, the shift adder outside the macro features dynamically adjustable 1–8 bit input activation and reconfigurable 4/8 bit storage weight, providing flexibility for fixed hardware resources. It achieves 148.5 TOPS/W energy efficiency at 4-bit activation and weight precision, which shows at least a 1.32× improvement over prior works.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"166 ","pages":"Article 106903"},"PeriodicalIF":1.9,"publicationDate":"2025-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145158628","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}