Microelectronics Journal最新文献

Stress analysis and optimization of QFN solder joints under bending-torsion coupled conditions based on the SSA

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-04-01 DOI: 10.1016/j.mejo.2025.106661

Jisheng Wei, Chunyue Huang, Chao Gao, Gui Wang

引用次数: 0

A single-inductor multiple-output buck/boost DC–DC converter with both suppressed self-regulation and cross-regulation via an energy storage channel

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-03-28 DOI: 10.1016/j.mejo.2025.106655

Hui Tong, Meigui Wang, Zhijian Chen, Yanqi Zheng

{"title":"A single-inductor multiple-output buck/boost DC–DC converter with both suppressed self-regulation and cross-regulation via an energy storage channel","authors":"Hui Tong, Meigui Wang, Zhijian Chen, Yanqi Zheng","doi":"10.1016/j.mejo.2025.106655","DOIUrl":"10.1016/j.mejo.2025.106655","url":null,"abstract":"<div><div>A single-inductor multiple-output buck/boost DC–DC converter that utilizes an energy storage channel to effectively improve the performance in both self-regulation (SR) and cross-regulation (CR) is presented in this article. With the extra channel, the energy storage and distribution method (ESDM) suppresses CR by extending charge control and SR through parallel power delivery. Additionally, the converter facilitates a seamless transition between continuous conduction mode (CCM) and low power mode (LPM) based on load conditions, thereby enhancing load capacity and overall efficiency. The converter is implemented in a standard 0.18-<span><math><mi>μ</mi></math></span>m 1.8 V/3.3 V CMOS process. Simulation results indicate that the SR of the proposed design is less than 0.056 mV/mA, achieving a 15.9<span><math><mo>×</mo></math></span> reduction compared to the conventional charge control method, while CR is less than 0.027 mV/mA, with a 10.7<span><math><mo>×</mo></math></span> reduction. The converter achieves a peak efficiency of 92.3% and maintains an efficiency of 88.2% at a light load of 1 mW.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"159 ","pages":"Article 106655"},"PeriodicalIF":1.9,"publicationDate":"2025-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143739766","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Negative capacitance double-gate MOSFET for advanced low-power electronic applications

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-03-28 DOI: 10.1016/j.mejo.2025.106656

Amit Kumar , Saurabh Chaturvedi , Satyendra Kumar

{"title":"Negative capacitance double-gate MOSFET for advanced low-power electronic applications","authors":"Amit Kumar , Saurabh Chaturvedi , Satyendra Kumar","doi":"10.1016/j.mejo.2025.106656","DOIUrl":"10.1016/j.mejo.2025.106656","url":null,"abstract":"<div><div>The negative capacitance metal–oxide–semiconductor field-effect transistor (NC-MOSFET) has gained significant attention for its potential in low-power applications. This paper introduces a novel triple-material double-gate negative capacitance MOSFET (TM-DG-NC-MOSFET) architecture, analyzed through technology computer-aided design (TCAD) simulations to assess its DC, analog, linearity, and distortion performance characteristics. For comparison, a triple-material double-gate MOSFET (TM-DG-MOSFET) without the negative capacitance effect is also designed and simulated. Key device parameters are optimized for both architectures. TCAD simulation results at <span><math><msub><mrow><mi>V</mi></mrow><mrow><mi>D</mi><mi>S</mi></mrow></msub></math></span> = 0.1 V reveal that the TM-DG-NC-MOSFET achieves a subthreshold swing of 25 mV/decade, an on-state current of <span><math><mrow><mn>3</mn><mo>.</mo><mn>19</mn><mo>×</mo><mn>1</mn><msup><mrow><mn>0</mn></mrow><mrow><mo>−</mo><mn>3</mn></mrow></msup></mrow></math></span> A/<span><math><mrow><mi>μ</mi><mi>m</mi></mrow></math></span>, and a switching ratio of <span><math><mrow><mn>5</mn><mo>.</mo><mn>13</mn><mo>×</mo><mn>1</mn><msup><mrow><mn>0</mn></mrow><mrow><mn>7</mn></mrow></msup></mrow></math></span>, outperforming the baseline TM-DG-MOSFET, which exhibits a subthreshold swing of 77 mV/decade, an on-state current of <span><math><mrow><mn>0</mn><mo>.</mo><mn>83</mn><mo>×</mo><mn>1</mn><msup><mrow><mn>0</mn></mrow><mrow><mo>−</mo><mn>3</mn></mrow></msup></mrow></math></span> A/<span><math><mrow><mi>μ</mi><mi>m</mi></mrow></math></span>, and a switching ratio of <span><math><mrow><mn>1</mn><mo>.</mo><mn>34</mn><mo>×</mo><mn>1</mn><msup><mrow><mn>0</mn></mrow><mrow><mn>7</mn></mrow></msup></mrow></math></span>. Comparative analysis shows that the TM-DG-NC-MOSFET offers enhanced DC, analog, and linearity performance with reduced distortion, indicating its suitability as a promising candidate for low-power circuit applications.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"159 ","pages":"Article 106656"},"PeriodicalIF":1.9,"publicationDate":"2025-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143739445","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

An investigation of how circuit parameters affect the short-circuit type 2 ruggedness in FS-IGBT

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-03-27 DOI: 10.1016/j.mejo.2025.106665

Jingping Zhang , Houcai Luo , Huan Wu , Bofeng Zheng , Xianping Chen

{"title":"An investigation of how circuit parameters affect the short-circuit type 2 ruggedness in FS-IGBT","authors":"Jingping Zhang , Houcai Luo , Huan Wu , Bofeng Zheng , Xianping Chen","doi":"10.1016/j.mejo.2025.106665","DOIUrl":"10.1016/j.mejo.2025.106665","url":null,"abstract":"<div><div>Field-stop insulated gate bipolar transistors (FS-IGBTs) are extensively utilized in various power applications because of their lower conduction and switching losses. However, as application conditions become more demanding, there is an increasing need for improved reliability and ruggedness of the FS-IGBT. Short circuits are one of the most common failures of FS-IGBTs. Under these circumstances, the device may conduct unexpectedly or operate with minimal bus parasitic inductance, leading to a significant increase in the device's junction temperature. Failure to turn off the FS-IGBT promptly may result in thermal runaway and device burnout. Short-circuit type 2 (SC2) is more frequently observed in practical FS-IGBT applications than short-circuit type 1 (SC1). Nevertheless, the majority of current research primarily concentrates on SC1, with relatively limited studies on SC2 of FS-IGBTs. This study aims to investigate the circuit parameters of SC2 and comprehensively analyze the impact of each parameter on SC2. The experimental results indicate that the bus voltage <em>V</em><sub><em>DC</em></sub>, gate voltage <em>V</em><sub><em>G</em></sub>, and temperature <em>T</em><sub><em>C</em></sub> significantly affect the SC2 performance of the FS-IGBT. Therefore, a moderate decrease in <em>V</em><sub><em>DC</em></sub>, <em>V</em><sub><em>G</em></sub>, and <em>T</em><sub><em>C</em></sub> can effectively enhance the ruggedness of SC2 and the short-circuit withstand time <em>t</em><sub><em>SC</em></sub> of the device.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"159 ","pages":"Article 106665"},"PeriodicalIF":1.9,"publicationDate":"2025-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143726099","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

An NMOS LDO with input pre-regulation technique for Sigma-Delta DAC with wide supply range

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-03-27 DOI: 10.1016/j.mejo.2025.106666

Xingyuan Tong, Yinbo Li, Xin Xin

{"title":"An NMOS LDO with input pre-regulation technique for Sigma-Delta DAC with wide supply range","authors":"Xingyuan Tong, Yinbo Li, Xin Xin","doi":"10.1016/j.mejo.2025.106666","DOIUrl":"10.1016/j.mejo.2025.106666","url":null,"abstract":"<div><div>An NMOS low-dropout regulator (LDO) is presented for a digital-to-analog converter with wide supply range. To widen the input voltage range of the NMOS LDO, a voltage pre-regulator and a charge pump are combined. Under high-voltage supply conditions, the input pre-regulator is employed to circumvent high-voltage transistors (HVT) and to avoid standard-voltage transistors (SVT) breakdowns. When the input voltage is low, the charge pump boosts the supply voltage of the driving circuit for ensuring enough overdrive voltage of the NMOS power transistors. Besides, a suppression circuit using negative feedback technique is also proposed to reduce the effect of the output voltage fluctuations of the charge pump and reference circuits on the accuracy of the LDO. The proposed LDO is designed with 0.18 μm BCD process and occupies an active area of 1.14 mm<sup>2</sup>. It can operate with an input voltage range of 3.3–24 V with highly SVTs and provide a load current of up to 1 A while the quiescent current is only 0.81 mA. The load and line regulation of the LDO are 0.57 μV/mA and 0.78 mV/V, respectively.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"159 ","pages":"Article 106666"},"PeriodicalIF":1.9,"publicationDate":"2025-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143739764","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A class-AB rail-to-rail operational amplifier with wide supply voltage and high gain

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-03-26 DOI: 10.1016/j.mejo.2025.106643

Sikai Chen, Peng Zhang, Lumiao Zhang, Zhang Zhang

{"title":"A class-AB rail-to-rail operational amplifier with wide supply voltage and high gain","authors":"Sikai Chen, Peng Zhang, Lumiao Zhang, Zhang Zhang","doi":"10.1016/j.mejo.2025.106643","DOIUrl":"10.1016/j.mejo.2025.106643","url":null,"abstract":"<div><div>This paper presents a high-gain rail-to-rail operational amplifier architecture, characterized by its low voltage and high gain. The design incorporates a complementary PMOS and NMOS folded cascode, using a transconductance linear loop to bias the Class-AB stage for push–pull output. Furthermore, the circuit supports a wide input power supply voltage range, operating efficiently over an input voltage span of 1.8 V to 5 V. The op-amp was fabricated using a 90 nm BCD technology, with a core chip size of approximately <span><math><mrow><mn>0</mn><mo>.</mo><mn>455</mn><mspace></mspace><mo>×</mo><mspace></mspace><mn>0</mn><mo>.</mo><mn>374</mn><mspace></mspace><msup><mrow><mtext>mm</mtext></mrow><mrow><mn>2</mn></mrow></msup></mrow></math></span>. Post-simulation results reveal a DC gain of 123 dB, a gain bandwidth of 0.86 MHz, and a noise level of <span><math><mrow><mn>24</mn><mspace></mspace><mtext>nV</mtext><mo>/</mo><msqrt><mrow><mtext>Hz</mtext></mrow></msqrt><mspace></mspace><mi>@</mi><mspace></mspace><mn>10</mn><mspace></mspace><mtext>kHz</mtext></mrow></math></span> with a 1.8 V supply voltage. Measurement outcomes demonstrate a slew rate of <span><math><mrow><mn>0</mn><mo>.</mo><mn>157</mn><mspace></mspace><mtext>V</mtext><mo>/</mo><mi>μ</mi><mtext>s</mtext></mrow></math></span> under loading conditions of 20pF and <span><math><mrow><mn>10</mn><mspace></mspace><mtext>k</mtext><mi>Ω</mi></mrow></math></span>, with an output current of 1 mA and power consumption of <span><math><mrow><mn>21</mn><mo>.</mo><mn>77</mn><mspace></mspace><mi>μ</mi><mtext>A</mtext></mrow></math></span> and <span><math><mrow><mn>25</mn><mo>.</mo><mn>26</mn><mspace></mspace><mi>μ</mi><mtext>A</mtext></mrow></math></span> at 1.8 V and 5 V conditions, respectively.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"159 ","pages":"Article 106643"},"PeriodicalIF":1.9,"publicationDate":"2025-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143714739","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Single-step electron beam evaporation for integrated dual-metal gate and gate field-plate in GaN-on-Si MIS-HEMTs

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-03-26 DOI: 10.1016/j.mejo.2025.106663

Sheng Gao , Yanjun Wu , Xingyu Luo , Shengqi Yu , Qi Wang

{"title":"Single-step electron beam evaporation for integrated dual-metal gate and gate field-plate in GaN-on-Si MIS-HEMTs","authors":"Sheng Gao , Yanjun Wu , Xingyu Luo , Shengqi Yu , Qi Wang","doi":"10.1016/j.mejo.2025.106663","DOIUrl":"10.1016/j.mejo.2025.106663","url":null,"abstract":"<div><div>This work reports the demonstration high performance GaN-on-Si metal-insulator-semiconductor (MIS) high-electron-mobility transistors (HEMTs) featuring dual-metal gate (DMG) and gate field-plate (GFP) structures. The DMG-GFP structures can be realized in a single step by adjusting the angle of electron beam evaporation, eliminating the requirement for multiple process steps. Higher carrier transfer efficiency and more uniform electric field distribution of the DMG-GFP-HEMTs (gate to drain distance <em>L</em><sub>GD</sub> of 18 μm) result in a pronounced enhancement of drain current (<em>I</em><sub>D</sub>) and transconductance (<em>G</em><sub>m</sub>) by 15 %, a remarkable breakdown voltage (<em>V</em><sub>br</sub>) increases of 44.9 %, and a significantly reduced current collapse over the single metal gate (SMG) control devices. Besides, the <em>V</em><sub>br</sub> of DMG-GFP-HEMTs exhibits a noteworthy 16.8 % improvement compared to SMG-GFP-HEMTs, further validating the advantageous impact of the DMG structure on <em>V</em><sub>br</sub> performance. Weibull analysis at 25 °C extrapolated a 10-year maximum operating gate voltage of 6.4 V for DMG-GFP HEMTs, a 16.3 % improvement over SMG-GFP HEMTs. The mechanism of DMG-GFP structures for suppressing current collapse has also been investigated, where the DMG structure helps to weaken the electron capture effect on the AlGaN/SiNx interface and the GFP structure enables the timely release of trapped electrons.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"159 ","pages":"Article 106663"},"PeriodicalIF":1.9,"publicationDate":"2025-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143726100","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Impact of the collector structure on the performance of the insulated gate bipolar transistor

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-03-25 DOI: 10.1016/j.mejo.2025.106651

Jeroen van Zoeren , Gaurav Gupta , Boni Boksteen , Lis K. Nanver , Raymond J.E. Hueting

引用次数: 0

An 8-bit 1.16 mw 500 ms/s SAR ADC with bidirectional-bit-distribution-based offset calibration and partially activated accelerating current source

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-03-24 DOI: 10.1016/j.mejo.2025.106649

Min Lin, Pengjun He, Jinpeng Tian

引用次数: 0

A digital background calibration method for SAR ADC based on dual-layer feedforward neural network

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-03-22 DOI: 10.1016/j.mejo.2025.106645

Tiehu Li , Jintao Huang , Jun Zeng , Chaodong Guo , Wei Zhang , Xiaojun Fu , Daiguo Xu , Gang Yan , Junyi Jiang , Rui Lai , Jun-an Zhang

{"title":"A digital background calibration method for SAR ADC based on dual-layer feedforward neural network","authors":"Tiehu Li , Jintao Huang , Jun Zeng , Chaodong Guo , Wei Zhang , Xiaojun Fu , Daiguo Xu , Gang Yan , Junyi Jiang , Rui Lai , Jun-an Zhang","doi":"10.1016/j.mejo.2025.106645","DOIUrl":"10.1016/j.mejo.2025.106645","url":null,"abstract":"<div><div>This paper addresses the impact of capacitor mismatch, comparator offset, and incomplete settling of the digital-to-analog converter (DAC) on the dynamic performance of Successive Approximation Register (SAR) Analog-to-Digital Converters (ADCs). A digital background calibration method using a double-layer feedforward neural network is proposed. The network is trained in MATLAB and implemented on an FPGA to validate the calibration algorithm. The study explores the influence of parameters like the number of neurons, training samples, and iterations on performance. FPGA results show that, after calibration, the Spurious-Free Dynamic Range (SFDR) and Signal-to-Noise-and-Distortion Ratio (SNDR) of a 12-bit 100 MSPS SAR ADC model improved from 46.58 dB and 46.53 dB to 98.10 dB and 70.87 dB. Similarly, for a 10-bit 31.25 MSPS SAR ADC chip, SFDR and SNDR increased from 61.46 dB and 46.86 dB to 79.87 dB and 57.09 dB. These results confirm the proposed method’s effectiveness for addressing non-idealities in both simulated models and hardware.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"159 ","pages":"Article 106645"},"PeriodicalIF":1.9,"publicationDate":"2025-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143705554","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0