Microelectronics Journal最新文献

An ultra-low-power CMOS image sensor with a new pixel structure in PWM mode featuring a programmable ramp generator for calibration 一种超低功耗CMOS图像传感器，具有PWM模式下的新像素结构，具有可编程斜坡发生器用于校准

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-05-23 DOI: 10.1016/j.mejo.2025.106726

Ziyuan Wang, Ye Zhao, Aoming Zhan, Jinyu Gao, Long Chen, Cunbiao Hao, Hongying Zhang, Shushan Qiao

{"title":"An ultra-low-power CMOS image sensor with a new pixel structure in PWM mode featuring a programmable ramp generator for calibration","authors":"Ziyuan Wang, Ye Zhao, Aoming Zhan, Jinyu Gao, Long Chen, Cunbiao Hao, Hongying Zhang, Shushan Qiao","doi":"10.1016/j.mejo.2025.106726","DOIUrl":"10.1016/j.mejo.2025.106726","url":null,"abstract":"<div><div>This paper presents an ultra-low-power 128 × 128 pixel pulse-width modulation (PWM) CMOS image sensor for low power applications. For always-on ultra-low-power imaging, a novel PWM pixel circuit with a tapered reset technology is implemented. Additionally, by turning off all the pixels except those in reset phase and readout phase, power consumption is reduced from 52 nW to 0.1 nW for each pixel. In addition, to overcome the settling latency of subthreshold comparator, we use a programmable ramp generator for voltage-to-time conversion for linear response, achieving a non-linearity of 0.04%. This ultra-low-power CMOS image sensor is designed and fabricated in CMOS 180 nm process technology. Measurement results demonstrate that the proposed CMOS image sensor consumes only <span><math><mrow><mn>61</mn><mo>.</mo><mn>6</mn><mspace></mspace><mi>μ</mi><mi>W</mi></mrow></math></span> at 62.5 frames per second (fps) with a fill factor of 58% at 0.8V operation. These performances make the image sensor perfectly suitable for IoT applications and some other edge devices.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"162 ","pages":"Article 106726"},"PeriodicalIF":1.9,"publicationDate":"2025-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144147930","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A 8–10 GHz compact low noise amplifier MMIC with high linearity based on GaAs technology 一种基于GaAs技术的8-10 GHz高线性度紧凑型低噪声MMIC放大器

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-05-23 DOI: 10.1016/j.mejo.2025.106742

Xuejie Bai, Yongle Wu, Shuchen Zhen, Zhenxing Gao, Weimin Wang

引用次数: 0

Optimizing label correlation in deep learning-based side-channel analysis 基于深度学习的边信道分析中标签相关性的优化

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-05-23 DOI: 10.1016/j.mejo.2025.106721

Shengcheng Xia, Lang Li, Yu Ou, Jiahao Xiang

{"title":"Optimizing label correlation in deep learning-based side-channel analysis","authors":"Shengcheng Xia, Lang Li, Yu Ou, Jiahao Xiang","doi":"10.1016/j.mejo.2025.106721","DOIUrl":"10.1016/j.mejo.2025.106721","url":null,"abstract":"<div><div>Label distribution learning techniques can significantly enhance the effectiveness of side-channel analysis. However, this method relies on using probability density functions to estimate the relationships between labels. The settings of parameters play a crucial role in the impact of the attacks. This study introduces a non-parametric statistical method to calculate the distribution between labels, specifically employing smoothing with the Gaussian kernel function and adjusting bandwidth. Then, the aggregation of the results from each label processed by the Gaussian kernel facilitates a hypothesis-free estimation of the label distribution. This method accurately represents the actual leakage distribution, speeding up guess entropy convergence. Secondly, we exploit similarities between profiling traces, proposing an analysis scheme for sample correlation locally of label distribution learning. Furthermore, Signal to-Noise Ratio (SNR) is employed to re-extract and reduce dataset dimensions to 500 power consumption points, resulting in noise reduction. Our results showcase the successful training of 800 profiling traces using our method for sample correlation locally of label distribution learning, with the findings indicating its exceptional performance.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"162 ","pages":"Article 106721"},"PeriodicalIF":1.9,"publicationDate":"2025-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144135185","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A 36× 7 scanning LiDAR sensor with full coincidence detection for background light suppression 一种36x7扫描激光雷达传感器，具有完全符合检测的背景光抑制

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-05-22 DOI: 10.1016/j.mejo.2025.106722

Qinglong Lin, Yingying Jiao, Kaiming Nie, Jiangtao Xu

{"title":"A 36× 7 scanning LiDAR sensor with full coincidence detection for background light suppression","authors":"Qinglong Lin, Yingying Jiao, Kaiming Nie, Jiangtao Xu","doi":"10.1016/j.mejo.2025.106722","DOIUrl":"10.1016/j.mejo.2025.106722","url":null,"abstract":"<div><div>This paper presents a scanning light detection and ranging (LiDAR) with a 36 × 7 array, integrated with coarse and fine quantization time to digital converters (TDCs). A novel coincidence detection circuit is proposed to mitigate the issues of miscounts and missed counts commonly encountered in conventional methods. Furthermore, the system employs a hybrid architecture that combines successive approximation with pipelining, enabling parallel binary quantization of each stage. The chip is designed using a 110 nm CMOS process with a total area of <span><math><mrow><mn>1</mn><mo>.</mo><mn>15</mn><mspace></mspace><msup><mrow><mi>mm</mi></mrow><mrow><mn>2</mn></mrow></msup></mrow></math></span>. The coarse quantization TDC adopts an analog counter design, achieving a compact macro-pixel size of <span><math><mrow><mn>55</mn><mo>×</mo><mn>55</mn><mspace></mspace><msup><mrow><mi>μ</mi><mi>m</mi></mrow><mrow><mn>2</mn></mrow></msup></mrow></math></span>. The simulation results demonstrate that the proposed coincidence detection circuit exhibits a higher success rate under varying background light intensities and distances, and the system achieves a depth precision of 0.18% over a measurement range of 48 meters with a frame rate of 50 fps.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"162 ","pages":"Article 106722"},"PeriodicalIF":1.9,"publicationDate":"2025-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144138324","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A low-power, area-efficient digital decimation filter with column-shared counter topology for CMOS image sensor 一种用于CMOS图像传感器的低功耗、面积高效的列共享计数器拓扑数字抽取滤波器

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-05-22 DOI: 10.1016/j.mejo.2025.106719

Qiang Zhao , Jianmin Zhang , Shiqi Dang , Bin Qiang , Xiuying Wang , Xin Li , Zhigang Li , Chunyu Peng , Zhiting Lin , Xiulong Wu

{"title":"A low-power, area-efficient digital decimation filter with column-shared counter topology for CMOS image sensor","authors":"Qiang Zhao , Jianmin Zhang , Shiqi Dang , Bin Qiang , Xiuying Wang , Xin Li , Zhigang Li , Chunyu Peng , Zhiting Lin , Xiulong Wu","doi":"10.1016/j.mejo.2025.106719","DOIUrl":"10.1016/j.mejo.2025.106719","url":null,"abstract":"<div><div>In this paper, a low-power, area-efficient digital decimation filter with column-shared counter for second-order incremental <span><math><mrow><mi>Σ</mi><mi>Δ</mi></mrow></math></span> analog-to-digital converter is proposed. A mathematical function transformation is used to reduce the number of transistors by turning the counter into a multicolumn-shared counter, and a 13-bit area-efficient adder design is proposed to further reduce the chip area and power consumption of the digital filter, and the filter operating speed is improved by the modification. The design is implemented with a 130 nm CMOS process. The total area of each digital filter row is <span><math><mrow><mn>4</mn><mo>.</mo><mn>5</mn><mo>×</mo><mn>160</mn><mspace></mspace><mi>μ</mi><msup><mrow><mtext>m</mtext></mrow><mrow><mn>2</mn></mrow></msup></mrow></math></span>, and the number of transistors is 314, which is a 30% reduction compared with the traditional architecture. According to the post-layout simulation, the maximum working frequency is 153 MHz. The total power consumption of the single-column filter without column-shared counter is <span><math><mrow><mn>2</mn><mo>.</mo><mn>25</mn><mspace></mspace><mi>μ</mi><mtext>W</mtext><mo>∼</mo><mn>4</mn><mo>.</mo><mn>5</mn><mspace></mspace><mi>μ</mi><mtext>W</mtext></mrow></math></span> under the clock frequency 50 MHz.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"162 ","pages":"Article 106719"},"PeriodicalIF":1.9,"publicationDate":"2025-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144116337","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A 10.5–13 GHz 6-bit 360°Active vector modulator phase shifter with 0.42 dB/2.2°RMS magnitude/phase errors for phased array systems 一种用于相控阵系统的10.5-13 GHz 6位360°有源矢量调制器移相器，其有效值/相位误差为0.42 dB/2.2°

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-05-19 DOI: 10.1016/j.mejo.2025.106733

Gaoyuan Zhao, Xiangyu Meng, Yanting Chen, Chuanjie Chen, Pengfei Bai

引用次数: 0

A resistor-based temperature sensor for MEMS frequency references 基于电阻的MEMS频率参考温度传感器

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-05-15 DOI: 10.1016/j.mejo.2025.106728

Yi Lai, Shiyue Ma, Xi Chen, Keping Wang

引用次数: 0

W-band wideband high-gain circularly polarized π-shaped antenna array with stacked parasitic patches w波段宽带高增益圆极化叠加寄生贴片π形天线阵列

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-05-13 DOI: 10.1016/j.mejo.2025.106729

Kuan Zhang , Yao Li , Quan Yuan , Guanghua Sun , Yanjie Wang

{"title":"W-band wideband high-gain circularly polarized π-shaped antenna array with stacked parasitic patches","authors":"Kuan Zhang , Yao Li , Quan Yuan , Guanghua Sun , Yanjie Wang","doi":"10.1016/j.mejo.2025.106729","DOIUrl":"10.1016/j.mejo.2025.106729","url":null,"abstract":"<div><div>This paper presents a W-band circularly polarized (CP) antenna featuring aperture-coupled rotating π-shaped patches and stacked parasitic patches. The design employs a pair of symmetrical π-shaped patches, whose optimized rotation angle enables the realization of high-quality circular polarization. Compared to conventional dipole or rectangular patch structures, the π-shaped configuration provides an enhanced axial ratio (AR) bandwidth. The radiating patches are embedded within a cavity formed by substrate-integrated waveguides (SIW), with energy coupling achieved through a precisely designed slot on the SIW ground plane. To further enhance the radiation performance, a pair of stacked rectangular parasitic patches are introduced above the radiating structure. Simulation results demonstrate that the proposed antenna element achieves an 11.7 % (86–97 GHz) AR bandwidth and a peak gain of 9.7 dBic. As proof of concept, a 2 × 2 elements prototype was designed and fabricated using single-layer PCB technology. Measurements demonstrate that this array exhibits an impedance bandwidth of 11.4 % (88–98.5 GHz), an AR bandwidth of 11.3 % from 87.2 to 97.6 GHz, a gain variation between 13.8 and 15.2 dBic, and the maximum aperture efficiency reaches 74.5 %.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"161 ","pages":"Article 106729"},"PeriodicalIF":1.9,"publicationDate":"2025-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143948165","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Simulation and fabrication of 4H-SiC SBD with main P-epilayer island termination 带有主p层岛端的4H-SiC SBD的仿真与制作

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-05-13 DOI: 10.1016/j.mejo.2025.106732

Xinyu Wang , Dengwen Yuan , Shicheng Zhu , Xiyao Huang , Yaxin Li , Lei Ge , Yingxin Cui , Mingsheng Xu , Yu Zhong , Xiaobo Hu , Kuan Yew Cheong , Xiangang Xu , Jisheng Han

{"title":"Simulation and fabrication of 4H-SiC SBD with main P-epilayer island termination","authors":"Xinyu Wang , Dengwen Yuan , Shicheng Zhu , Xiyao Huang , Yaxin Li , Lei Ge , Yingxin Cui , Mingsheng Xu , Yu Zhong , Xiaobo Hu , Kuan Yew Cheong , Xiangang Xu , Jisheng Han","doi":"10.1016/j.mejo.2025.106732","DOIUrl":"10.1016/j.mejo.2025.106732","url":null,"abstract":"<div><div>This article presents the design and fabrication results of 4H-SiC Schottky barrier diode (SBD) with a main P-epilayer island termination. The device simulations analyzed structural parameters, including the island thickness (T<sub>MP</sub>), inclination angle (θ), length (L<sub>MP</sub>), and end relaxation length (L<sub>ER</sub>), on electric field distribution within SBD. Additionally, the influence of the P-type doping concentration (D<sub>MP</sub>) on the breakdown voltage indicates that the main P-epilayer island structure exhibits a relatively wide tolerance range. Using optimal parameters and ion-implantation-free fabrication process, the fabricated SBD with the main P-epilayer island achieved a breakdown voltage of 1543 V with a leakage current of only 1.5 μA under a reverse voltage of 1200 V, and a forward voltage drop (V<sub>F</sub>) of 1.35 V at a forward current of 10 A using the structural parameters of θ = 20°, L<sub>MP</sub> = 104 μm, T<sub>MP</sub> = 1.2 μm, and D<sub>MP</sub> = 6 × 10<sup>17</sup> cm<sup>−3</sup>.This optimized design brings enormous potential for the low-cost development of SBD.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"161 ","pages":"Article 106732"},"PeriodicalIF":1.9,"publicationDate":"2025-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143948163","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Electrical properties of fully depleted silicon-on-insulator wafers 完全耗尽绝缘体上硅晶圆的电学特性

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-05-12 DOI: 10.1016/j.mejo.2025.106731

A.K. Aladim

引用次数: 0