Microelectronics Journal最新文献

{"title":"An enhanced efficiency 170–260 GHz frequency doubler based on three points resonance matching technique","authors":"","doi":"10.1016/j.mejo.2024.106424","DOIUrl":"10.1016/j.mejo.2024.106424","url":null,"abstract":"<div><div>This paper presents a full-band frequency doubler (170–260 GHz) with enhanced efficiency based on Schottky diodes. To achieve broadband matching between the matching circuit and the Schottky diode, a three points resonance matching technique (TPRMT) is employed. This technique is developed by considering the embedded impedance matching at three distinct frequency points: upper, middle, and lower, thereby guiding the design of the peripheral matching circuits. In comparison to single frequency point matching, this approach effectively suppresses sideband performance degradation, resulting in improved efficiency. Additionally, the peripheral matching circuits are meticulously designed to fulfill a resonance clockwise impedance trajectory, facilitating matching at the aforementioned three frequency points. Due to the limitation of the input power source, measurements were conducted only within the 170–237 GHz frequency band. The measured results show that the doubler achieves an efficiency ranging from 8.4 % to 14.1 % under an input power of 130–175 mW. The good consistency between simulation and measurement validates the significant advantages of TPRMT.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-09-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142316218","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Design of a low-power Digital-to-Pulse Converter (DPC) for in-memory-computing applications","authors":"","doi":"10.1016/j.mejo.2024.106420","DOIUrl":"10.1016/j.mejo.2024.106420","url":null,"abstract":"<div><div>Data converters such as analog-to-digital converters (ADCs), digital-to-analog converters (DACs), digital-to-time converters (DTCs), time-to-digital converters (TDCs), among others, are considered some of the most essential blocks in the field of integrated circuit design. In this work, we introduce a novel type of data converter known as the Digital-to-Pulse converter (DPC) and present its novel analog flow circuit implementation. The DPC system is a critical component in emerging artificial neural network accelerators and in-memory computing systems. The DPC system presented in this study offers two distinct operating modes. The first mode is the generation of a single pulse with a width that is modulated by the digital input. The second mode is an n-bit digital to discrete pulse converter, where the number of generated pulses is directly related to the value of the digital input. The proposed DPC system offers designers a high level of flexibility in shaping the characteristics of the output pulses, including the number of pulses, pulse width, and pulse amplitude. This empowers designers to accommodate different application requirements and scenarios effectively. The proposed circuit has been verified and tested using Virtuoso Cadence circuit tools in 180 nm CMOS technology with post-layout simulation and analysis. The results indicate a significant enhancement in average power consumption (<span><math><mrow><mo>∼</mo><mn>12</mn><mo>×</mo></mrow></math></span>), layout area (<span><math><mrow><mo>∼</mo><mn>5</mn><mo>×</mo></mrow></math></span>), and latency (<span><math><mrow><mo>∼</mo><mn>1</mn><mo>.</mo><mn>4</mn><mo>×</mo></mrow></math></span>) with the proposed system compared to the digital Register Transfer Level (RTL) implementation under a power supply of 1.8V and a clock frequency of 1 GHz in the Application Specific Integrated Circuits (ASIC) flow. This demonstrates the suitability of the proposed system for low-power and high-speed applications.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-09-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://www.sciencedirect.com/science/article/pii/S1879239124001243/pdfft?md5=7404a0b8217e2561fc2f63b7af8c8fb4&pid=1-s2.0-S1879239124001243-main.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142316217","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"String-level compact modeling of erase operations in the body-floated vertical channel of 3D charge trapping flash memory","authors":"","doi":"10.1016/j.mejo.2024.106423","DOIUrl":"10.1016/j.mejo.2024.106423","url":null,"abstract":"<div><div>In this study, we examined the use of string-level compact modeling as an effective framework for circuit simulation focusing on erase operation in 3D charge trapping flash (CTF) memory devices. We analyzed the behaviors of the accumulated hole from p-type bulk (p-well) and the corresponding difference of channel electrostatic potential in the CTF cell string, which is attributed to the variation in hole barrier height in the channel of the ground select line (GSL) transistor during erase operation. We derived a formula for the hole current delivering positive potential from the p-well to the channel region and established a modeling procedure. Technology computer-aided design (TCAD) simulation results were used to extract model parameters and analyze channel electrostatic potential during the erase operation. Additionally, experimental data for erase speed were verified using simulation program with integrated circuit emphasis (SPICE) results. Because the erase efficiency is strongly related to hole behaviors based on the conditions of the GSL transistor, the proposed compact modeling is an effective tool for circuit designers and system architects to achieve better performance in erase execution and optimizing the design of 3D CTF memory devices.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-09-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142316214","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A cost-effective and highly robust triple-node-upset self-recoverable latch design based on dual-output C-elements","authors":"","doi":"10.1016/j.mejo.2024.106422","DOIUrl":"10.1016/j.mejo.2024.106422","url":null,"abstract":"<div><div>With the continuous reduction of feature size of transistors, single-event triple-node-upsets (TNUs) induced by the striking of radiation particles in nano-scale CMOS circuits have emerged as a significant reliability concern. To address the shortcomings of existing radiation-hardened designs, including low reliability and high overhead, this paper proposes a cost-effective and highly robust TNU self-recovery latch design called DOCTRL. The proposed DOCTRL latch primarily consists of six dual-output C-elements (DOCs) and two clocked DOCs. By utilizing DOCs with two independent outputs, the proposed DOCTRL latch achieves a smaller area overhead. In addition, a four-level circular interlock matrix connection is designed to recover all possible TNUs within the proposed DOCTRL latch. Meanwhile, the latch also incorporates clock gating technology and a high-speed path to minimize power consumption and delay penalties. Simulation results indicate that the proposed DOCTRL reduces area by an average of 32.43 %, power consumption by 46.84 %, delay by 14.43 %, and area-power-delay product (APDP) by 69.55 %, compared to the five typical TNU self-recovery latches (SCLCRL, TNUSH, LCTNUCR, ADTRL, TSRL). Furthermore, detailed process, voltage, temperature (PVT), and Monte Carlo simulations verify the robustness of the proposed DOCTRL latch.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-09-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142311885","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Junctionless accumulation-mode SOI ferroelectric FinFET for synaptic weights","authors":"","doi":"10.1016/j.mejo.2024.106413","DOIUrl":"10.1016/j.mejo.2024.106413","url":null,"abstract":"<div><div>In this work, a novel silicon-on-insulator (SOI) based junctionless-accumulation-mode (JAM) ferroelectric (FE) fin field effect transistor (FinFET) is proposed along with its fabrication process flow at a 3-nm node for synaptic weights. The proposed JAM FE FinFET device can be easily integrated with the fabrication flow of p-FinFET in SOI process flow. The proposed device can be easily incorporated into standard FinFET SOI technology and thus is very attractive with respect to previously proposed devices. Further, using a well-calibrated 3D TCAD simulation setup, we show that the device effectively replicates the behavior required for neuromorphic computing applications. The outcomes of the proposed study emphasize the significance of using the JAM FE FinFET as a synaptic weight device that exhibits a 76 % higher nonvolatile conductance range in the ON-state over existing junctionless and conventional FE FinFET devices. Our simulations show that the proposed device offers continuous linear conductance variation and symmetric switching characteristics, which are essential for neuromorphic applications.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142316216","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A common-mode insensitive thyristor-based latch regenerative comparator for low supply voltage applications","authors":"","doi":"10.1016/j.mejo.2024.106419","DOIUrl":"10.1016/j.mejo.2024.106419","url":null,"abstract":"<div><p>Presented in this article is a new two-stage rail-to-rail regenerative comparator circuit designed for low supply voltage applications. This work introduces a thyristor-based latch for the first time, allowing the comparator to operate from rail-to-rail inputs. The proposed comparator has been post-layout simulated using a standard 65 nm CMOS technology. The worst-case simulation results demonstrate that the comparator exhibits a delay of less than 22ns and consumes only 132 nW of power at a supply voltage of 0.6V and a sample rate of 1 MHz across its full common-mode range. Furthermore, the total input-referred offset voltage (3std + mean) remains below 21 mV throughout the entire rail-to-rail common-mode voltage range. Compared to the conventional single-stage comparator, the proposed circuit showcases an improvement of over 87 % in terms of delay and energy efficiency. Given its dignified performance metrics, this comparator is well-suited for use in low supply voltage applications such as biomedical implants, successive approximation registers analog-to-digital converters (SAR ADCs), Internet of Things (IoT).</p></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142243648","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Radiation effects modeling of InP-based HEMT based on neural networks","authors":"","doi":"10.1016/j.mejo.2024.106414","DOIUrl":"10.1016/j.mejo.2024.106414","url":null,"abstract":"<div><div>This paper has proposed a novel radiation effects modeling methodology based on neural networks for InP-based high-electron-mobility transistors (HEMTs). 2 MeV proton radiation has been performed with dose of 1 × 10¹² H⁺/cm², 5 × 10¹² H⁺/cm², 1 × 10¹³ H⁺/cm², 5 × 10¹³ H⁺/cm², 1 × 10¹⁴ H⁺/cm². The radiation neural network models were comparatively constructed based on Feedforward Neural Network (FNN), Recurrent Neural Network (RNN), and Long Short-Term Memory (LSTM). Results indicate that the LSTM network outperforms the FNN and RNN networks in the modeling for both drain-source current (<em>I</em>_DS) and S-parameters, which demonstrates superior prediction accuracy with smaller fitting error. The proposed modeling approach offers an accurate characterization for the radiation effects of InP-based HEMT devices, without the need to consider the complex degradation process associated with radiation, thus providing practical guidelines for the space applications of such devices.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-09-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142311581","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Z-shaped gate tunnel FET with graphene channel: An extensive investigation of its analog and linearity performance","authors":"","doi":"10.1016/j.mejo.2024.106412","DOIUrl":"10.1016/j.mejo.2024.106412","url":null,"abstract":"<div><p>This work analyzes a graphene channel Z-shaped gate tunnel FET's (ZTFET) analog, and linearity performance. This research aims to introduce graphene with a two-dimensional honeycomb structure that is anticipated to be a strong challenger for the upcoming generation of semiconductor devices. The ZTFET with graphene channel provides a 3-decade increase in ON current, indicating a notable improvement in gate capacitance and transconductance compared to the conventional silicon channel. This improvement further leads to better linearity and analog/RF performance. We delved into various linearity and Radio Frequency (RF) figure-of-merits, including g_mn, VIP₂, VIP₃, IIP₃, 1‐dB compression point, GBWP, TFP, unity gain cut‐off frequency, and maximum oscillation frequency. The results of the new GC-ZTFET are compared with those of the traditional ZTFET to establish its superiority. The GC-ZTFET outshines other device structures when speaking of linearity, RF performance, and current-carrying capability.</p></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-09-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142229037","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 0.075 mm2 BJT-based temperature sensor with a one-point trimmed 3σ inaccuracy of ±0.97 °C from −40 °C to 120 °C","authors":"","doi":"10.1016/j.mejo.2024.106418","DOIUrl":"10.1016/j.mejo.2024.106418","url":null,"abstract":"<div><p>This paper presents a bipolar junction transistor (BJT)-based CMOS temperature sensor for high accuracy, small-scale area, and low power consumption. A structure with a feedback amplifier biasing NPN transistors, combined with dynamic element matching (DEM), is proposed to avoid the effects of errors arising from the limited current gain of substrate PNP transistors in deep-submicron processes. Moreover, the switched capacitor (SC) integrators employ two single-stage cascode amplifiers for alternating cyclic sampling and integration, effectively simplifying the circuit design and reducing the operating voltage. The proposed sensor is fabricated with a standard 180 nm CMOS process, occupying an active chip area of 0.075 mm². It consumes 39.1 <span><math><mi>μ</mi></math></span>W of power at room temperature, operating with a supply voltage of 1.8 V. The measurements indicate that the sensor exhibits an inaccuracy of ±0.97 °C (3<span><math><mi>σ</mi></math></span>) across the temperature range from −40 °C to 120 °C following a single-point temperature calibration.</p></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142243646","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Design and investigation of electrostatic doped heterostructure vertical Si(1-x)Gex/Si nanotube TFET","authors":"","doi":"10.1016/j.mejo.2024.106417","DOIUrl":"10.1016/j.mejo.2024.106417","url":null,"abstract":"<div><p>Researchers are inclining toward heterostructures suitable lattice matching, in Tunnel FETs to eliminate the difficulties of decreased On-Current, subthreshold swings, and ambipolar behavior. Nowadays, Electrostatic doping (ED) is a scrutinized substitute device for creating areas with a high electron or hole density to the conventional doped devices. This manuscript proposes an Electrostatic Doped Heterostructure Vertical Si_(1-x)Ge_x/Si Nanotube Tunnel Field Effect with performance scanned by analyzing the different device parameters, considering the energy band diagram, concentrations of electrons, holes, potential, and electric field. In comparison to the Nanowire TFETs, the area, and rate of tunneling of the proposed device stand superior with a better I_ON/I_OFF ratio of 1.56∗10¹³ and a lower OFF-current of about ∼10⁻¹⁸A/μm. The device exhibits a Drain current (I_DS) of 2.39∗10⁵A/μm. The architecture of the suggested device possessing Si(1-x)Gex/Si structure exhibits enhanced characteristics like improved steepness of the sub-threshold slope, I_ON/I_OFF ratio, drain current, and lowered OFF-current.</p></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142233589","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}