Microelectronics Journal最新文献

{"title":"An 85.6-dB SNDR 1.5 MHz-BW NS-pipelined SAR ADC employing the gain-error-shaping technique to enhance the ADC linearity","authors":"Wenjie Liang ,&nbsp;Dazheng Chen","doi":"10.1016/j.mejo.2025.106593","DOIUrl":"10.1016/j.mejo.2025.106593","url":null,"abstract":"<div><div>This paper presents a noise-shaping (NS) pipelined SAR ADC. For a pipelined-SAR ADC, Gain-error-shaping (GES) techniques executing its function in the digital domain can calibrate and correct amplifier gains, reducing nonlinearity errors introduced by amplifiers and thereby improving the ADC performance. Thanks to the highly digitized structure of SAR ADC, NS-pipelined SAR ADC based on the GES is a promising research direction.</div><div>In a 0.18 μm CMOS process, the proposed ADC achieves a SNDR of 82.57 dB, with the signal bandwidth and the sampling rate being 1.5 MHz and 25 MHz respectively. It consumes 3.37 mW in total at a 1.8-V supply, resulting in a SNDR-based Schreier figure-of-merit (FoMs) of 179.1 dB. The chip area occupied by the ADC core is 1200μm × 800 μm.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"157 ","pages":"Article 106593"},"PeriodicalIF":1.9,"publicationDate":"2025-02-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143378430","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A chaotic strong transition effect ring oscillator PUF with effective immunity to modeling attacks","authors":"Jingchang Bian,&nbsp;Xingchen Du,&nbsp;Yingchun Lu,&nbsp;Aibin Yan,&nbsp;Huaguo Liang,&nbsp;Zhengfeng Huang","doi":"10.1016/j.mejo.2025.106592","DOIUrl":"10.1016/j.mejo.2025.106592","url":null,"abstract":"<div><div>Although the rapid development of information technology has brought unprecedented convenience and revolutionary changes to human lifestyles, it has also led to serious privacy and security issues. Massive amounts of sensitive information are exchanged within cyber-physical systems (CPS), and the storage and authentication processes of this information are highly susceptible to the attention of malicious attackers. Strong physical unclonable function (PUF) is a crucial hardware security primitive for identity authentication in lightweight internet of things (IoT) devices. However, most of the existing strong PUFs have failed to resist advanced modeling attacks based on machine learning. The paper proposes a chaotic strong transition effect ring oscillator (CS-TERO) PUF, which combines the nonlinearity of strong TERO and the unpredictability of chaotic design to resist modeling attacks. The strong PUF feature is achieved through configurable dual XOR gates and extended TERO chains. Chaotic operations are performed by obfuscating challenges using logical mapping functions. Experimental results demonstrate that the CS-TERO PUF successfully resists state-of-the-art modeling attacks, and the accuracy of all attacks is below 70 %. Compared to other modeling attack-resilient PUFs, our CS-TERO PUF requires fewer hardware resources, saving almost 25 % of area overhead compared to the most lightweight solutions. Additionally, the CS-TERO PUF demonstrates a reliability of 98.27 %, uniqueness of 53.65 %, and uniformity of 49.26 %, reaching an advanced strong PUF application standard. Furthermore, the randomness has also passed the internationally accredited NIST 800-22 S P test.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"157 ","pages":"Article 106592"},"PeriodicalIF":1.9,"publicationDate":"2025-02-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143378429","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"An 88 dB SNDR second-order CIFF delta-sigma modulator with 3-bit quantizer and capacitor sharing circuit","authors":"Wonkyu Do ,&nbsp;Juncheol Kim ,&nbsp;Hoyong Jung ,&nbsp;Neungin Jeon ,&nbsp;Young-Chan Jang","doi":"10.1016/j.mejo.2025.106589","DOIUrl":"10.1016/j.mejo.2025.106589","url":null,"abstract":"<div><div>A second-order cascaded-integrator feedforward integrator (CIFF) delta-sigma modulator (DSM) is proposed for sensor interfaces that require small area, low power, and high-resolution characteristics. It consists of two integrators containing capacitor arrays, a 3-bit quantizer based on a successive approximation register (SAR) analog-to-digital converter (ADC), and a data-weighted averaging (DWA) block. The proposed second-order CIFF DSM uses a three-bit quantizer instead of a single-bit quantizer to improve the dynamic characteristics of the DSM while reducing the area of the integration capacitors in the first integrator. In the second capacitor array used for the second integrator, a capacitor sharing circuit is implemented to perform the sampling for the second integrator, the summing for the CIFF, and the operation of the capacitor digital-to-analog converter (CDAC) for the SAR ADC-based 3-bit quantizer. The proposed capacitor sharing circuit reduces the area of the DSM for the sensor interface by eliminating the capacitors used for the summation of the CIFF and CDAC of the 3-bit quantizer. The proposed second-order CIFF DSM is designed using a 180-nm CMOS process, with an active area of 0.144 mm². It has a sampling rate of 125 kHz, using an external clock with a frequency of 750 kHz, and consumes 145.8 μW of power at a supply voltage of 1.8 V. When it has an oversampling ratio of 512, the measured SNDR for an input signal with a frequency of 100.0 Hz is approximately 88.4 dB.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"157 ","pages":"Article 106589"},"PeriodicalIF":1.9,"publicationDate":"2025-02-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143275471","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Shrink eFPGA tile area by using custom cells and optimizing routing congestion","authors":"Yanze Li,&nbsp;Jian Wang,&nbsp;Jinmei Lai","doi":"10.1016/j.mejo.2024.106544","DOIUrl":"10.1016/j.mejo.2024.106544","url":null,"abstract":"<div><div>—Embedded FPGA (eFPGA) is widely used in SoC design because of its process portability and flexible programmability. However, the area of eFPGA always occupies a larger area ratio, and due to the limitation of the number of available metal layers, it is easy to cause routing congestion and lead to a larger area. FPGA-specific custom cells can significantly reduce the total cell area of eFPGAs. When designing these custom cells, it's crucial to consider not only their compact implementation but also their interconnections with other cells to minimize routing congestion. Beyond customizing cells, optimizing the connections of configuration memory cells can further optimize routing congestion. This paper is dedicated to optimizing the physical implementation of eFPGA tiles. An eFPGA-specific custom cell design method with compact circuit structure is proposed to reduce the cell area while considering the routing connections. A more complete routing optimization method is proposed to completely optimize the connections of configuration memory cells to reduce routing congestion. We validated our approach in a 28 nm technology and found that our optimization can save 22.63 % in area while improving 33.89 % of worst case path delay compared with the standard cell implementation.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"156 ","pages":"Article 106544"},"PeriodicalIF":1.9,"publicationDate":"2025-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143162405","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Knowledge transferring framework for cell library characterization","authors":"Zhengguang Tang ,&nbsp;Cong Li ,&nbsp;Guangxin Guo ,&nbsp;Mingyu Ma ,&nbsp;Hailong You ,&nbsp;Xiaoling Lin","doi":"10.1016/j.mejo.2024.106542","DOIUrl":"10.1016/j.mejo.2024.106542","url":null,"abstract":"<div><div>To evaluate digital circuit performance across PVT (process, voltage, and temperature) corners, standard cell library characterization requires costly simulations. Leveraging machine learning (ML) can improve the efficiency of this process. However, existing ML-based methods for cell library characterization often neglect the knowledge embedded across different timing arcs, leading to the need for extensive training data. In this paper, we propose a transfer learning (TL) framework to enhance timing characterization across multiple timing arcs. By quantifying the similarity among training tasks in the cell library using a fine-grained metric, our method enables rapid and accurate cell delay predictions through pre-training knowledge. Compared to conventional ML approaches, our TL framework improves both prediction accuracy and efficiency. Experimental results on 45 nm MOSFET and 14 nm FINFET technologies show significant error reductions of up to 80% and 67%, respectively.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"156 ","pages":"Article 106542"},"PeriodicalIF":1.9,"publicationDate":"2025-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143162392","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"TCAD analysis of gate leakage and threshold drift in GaN devices with dual-gate structure","authors":"Hao-jie Xie,&nbsp;Ying Wang,&nbsp;Shi-Jin Liu,&nbsp;Cheng-Hao Yu,&nbsp;Hao-Min Guo","doi":"10.1016/j.mejo.2024.106521","DOIUrl":"10.1016/j.mejo.2024.106521","url":null,"abstract":"<div><div>This article explores the characteristics and performance of a novel high-electron-mobility-transistor (HEMTs) featuring a dual-gate and dual-field plate design. Two-dimensional numerical simulations of the devices were conducted using the semiconductor process simulation software Sentaurus TCAD. The gate reliability issue of p-GaN packaged AlGaN/GaN high electron mobility transistors (HEMTs) was assessed by monitoring the positive gate bias stress time variation from 1μs to 10s. Compared to conventional p-GaN HEMT devices, research simulations show a reduction in gate leakage and an increase in forward gate breakdown voltage from 8.6 V to 11.4 V. Under the parametric conditions described in the text, the reduction in sub-gate resistance results in higher total saturation currents and higher power. This improvement is achieved at the expense of on-resistance and gate capacitance. The simulation results demonstrate that the improvement of the gate by leakage measurement electric field reduces the threshold drift of the device drain bias at 20 V, with the effect of the best forward drift being reduced from 0.2 V to approximately 0.1 V (stress = 10s).</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"156 ","pages":"Article 106521"},"PeriodicalIF":1.9,"publicationDate":"2025-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143163111","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A low-power high-linearity voltage controlled oscillator employing unipolar metal oxide thin-film transistors","authors":"Zhaoyu Deng,&nbsp;Rongsheng Chen,&nbsp;Zhijian Chen,&nbsp;Delang Lin,&nbsp;Zhaohui Wu,&nbsp;Bin Li,&nbsp;Mingjian Zhao","doi":"10.1016/j.mejo.2024.106543","DOIUrl":"10.1016/j.mejo.2024.106543","url":null,"abstract":"<div><div>A novel low-power VCO based on Indium-Zinc-Oxide (IZO) thin-film transistors (TFTs) technology is introduced for TFT VCO-based ADCs. A typical ring oscillator (RO) may have poor linearity because the supply voltage controls its frequency. Therefore, a non-inverting frequency control cell (FCC) is integrated into a traditional 7-stage RO (VCO-odd) to improve linearity. Then the FCC is changed to be inverting, and the number of stages is reduced to 6 (VCO-even) to lower power consumption. Experimental results show power consumption of 247.2 <span><math><mi>μ</mi></math></span>W and 127.2 <span><math><mi>μ</mi></math></span>W, with linearity errors of 2.46% and 2.39%, respectively. Sine waves are applied to verify the VCOs’ conversion functions. Results show that they achieve SNDRs of 40.75 and 40.82 dB. These VCOs show potential for use in low-speed sensor readout interfaces.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"156 ","pages":"Article 106543"},"PeriodicalIF":1.9,"publicationDate":"2025-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143162387","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Evaluation of space radiation effects on FinFET oxide layer with Geant4 simulation","authors":"Jianyu Zhang ,&nbsp;Yang Hua ,&nbsp;Sichong Huang ,&nbsp;Tongde Li ,&nbsp;Liang Wang ,&nbsp;Xing Zhang ,&nbsp;Yuanfu Zhao","doi":"10.1016/j.mejo.2024.106520","DOIUrl":"10.1016/j.mejo.2024.106520","url":null,"abstract":"<div><div>This study examines the radiation effects on FinFET devices in various space orbits utilizing Geant4 simulations. The impact of incident particles is assessed through the calculation of deposited energy in the oxide layer. By aggregating the radiation-induced energy deposition across all compositional elements, this research evaluates the effects of nine distinct orbital environments with varying incident energies and angles. The Geant4-derived energy deposition spectrum, combined with the orbital radiation model, facilitates a quantitative comparison of radiation effects on FinFET devices. The study ranks the orbits and their elements, identifying the most sensitive incident direction based on deposited energy. This quantitative evaluation method presents a novel approach for assessing space radiation effects on microelectronic devices with element-specific resolution.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"156 ","pages":"Article 106520"},"PeriodicalIF":1.9,"publicationDate":"2025-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143163289","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"SCARefusion: Side channel analysis data restoration with diffusion model","authors":"Zeng Lu ,&nbsp;Yan Longde ,&nbsp;Wan Fei ,&nbsp;Chen Aidong ,&nbsp;Yang Ning ,&nbsp;Li Xiang ,&nbsp;Zhang Jiancheng ,&nbsp;Zhang Yanlong ,&nbsp;Wang Shuo ,&nbsp;Zhou Jing","doi":"10.1016/j.mejo.2024.106546","DOIUrl":"10.1016/j.mejo.2024.106546","url":null,"abstract":"<div><div>Side channel Analysis (SCA) based on deep learning is highly sensitive to data quality. When using the ID leakage model as the labeling criterion in supervised classification problems, slight data imbalance issues arise, which can reduce analysis efficiency. Diffusion Models are an emerging class of generative models that offer more intuitive, stable, robust, and interpretable advantages compared to Generative Adversarial Network (GAN). To address data imbalance, we introduce a latent diffusion model based on U-Net that retains high-resolution information for the decoding process, thereby recovering detailed power consumption trace (hereinafter referred to as traces) information. Our model, named SCA Restoration with Diffusion Model (SCARefusion), comprises Conditional Nonlinear Activation Free Blocks (CNAFBlocks), downsampling, and upsampling modules. The network integrates the SimpleGate nonlinear activation function, enhancing model performance and computational efficiency, and improving adaptability to input data. This approach effectively generates balanced class data for labels, mitigating dataset imbalance and avoiding the instability of GAN training. In this paper, Correlation Power Analysis (CPA) is used to calculate and compare the correlation coefficients between hypothetical and measured traces to detect whether the generated data exhibit the same leakage points as the original data. Additionally, the effectiveness of the generated traces is validated using Convolutional Neural Network (CNN) attacks. Experimental results demonstrate that SCARefusion exhibits outstanding performance on the fixed-key ASCAD synchronous and asynchronous 50 dataset, capable of generating traces consistent with the leakage points of the original traces and successfully extracting the correct key. Furthermore, we discuss reducing the learning rate, optimizing network architecture, and other parameters to address loss oscillation issues during model training. These studies contribute to improving the performance and robustness of deep learning in SCA, effectively addressing data challenges.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"156 ","pages":"Article 106546"},"PeriodicalIF":1.9,"publicationDate":"2025-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143163320","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A dynamic comparator exploiting floating inverter preamplifier with stacked cross coupled feedback inverter for 16-bit 1 MS/s SAR ADC","authors":"Zhenyu Zhu,&nbsp;Yuzhou Xiong,&nbsp;Yanbo Zhang,&nbsp;Zhangming Zhu","doi":"10.1016/j.mejo.2024.106551","DOIUrl":"10.1016/j.mejo.2024.106551","url":null,"abstract":"<div><div>This paper presents a dynamic comparator based on floating inverter preamplifier (FIA) designed for high-resolution SAR ADCs. The comparator incorporates a floating inverter preamplifier with stacked cross-coupled feedback inverters and a latch. Load transistors are also added to the input transistors, enhancing small-signal gain and accelerating the initial integration speed of the FIA. The preamplifier achieves a higher gain, effectively suppressing input referred noise and accelerating the latch's regeneration process. Simulations performed using 180 nm CMOS technology with a 1.2 V supply demonstrate a significant gain increase, with only a minimal decrease in common-mode voltage, compared to state-of-the-art architectures. The simulation results indicate a pre-amplification stage gain of 52.9 dB, noise limited to 24 μV in tt corner, and energy consumption of 0.36 pJ per comparison, meeting the stringent requirements of a 16-bit SAR ADC. To validate its performance, the proposed comparator was implemented in a 16-bit 1 MS/s SAR ADC. Under transient noise conditions in post simulation, FFT results reveal a Signal-to-Noise and Distortion Ratio (SNDR) of 91.003 dB, confirming the comparator's enhanced capability to suppress input referred noise.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"156 ","pages":"Article 106551"},"PeriodicalIF":1.9,"publicationDate":"2025-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143162402","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}