Microelectronics Journal最新文献

Temperature dependence of linearity parameters of GaN-based junctionless drain extended FinFET 氮化镓基无结漏极扩展FinFET线性参数的温度依赖性

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-07-29 DOI: 10.1016/j.mejo.2025.106813

N. Ashwini, K.S. Nikhil

{"title":"Temperature dependence of linearity parameters of GaN-based junctionless drain extended FinFET","authors":"N. Ashwini, K.S. Nikhil","doi":"10.1016/j.mejo.2025.106813","DOIUrl":"10.1016/j.mejo.2025.106813","url":null,"abstract":"<div><div>In this work, temperature dependent linearity parameters of Galliun Nitride (GaN, a wide gap material) based Junctionless Drain Extended FinFETs (JLDEFinFETs) for a temperature ranging from 100K to 450K are investigated using 3D thermodynamic TCAD simulation. An analysis of the transfer characteristics, off-current, transconductance, and its derivatives are carried out at various temperatures. Additionally, the impact of various linearity parameters, such as <span><math><mrow><mi>V</mi><mi>I</mi><msub><mrow><mi>P</mi></mrow><mrow><mn>2</mn></mrow></msub></mrow></math></span>, <span><math><mrow><mi>V</mi><mi>I</mi><msub><mrow><mi>P</mi></mrow><mrow><mn>3</mn></mrow></msub></mrow></math></span>, <span><math><mrow><mi>I</mi><mi>I</mi><msub><mrow><mi>P</mi></mrow><mrow><mn>3</mn></mrow></msub></mrow></math></span>, <span><math><mrow><mi>I</mi><mi>M</mi><msub><mrow><mi>D</mi></mrow><mrow><mn>3</mn></mrow></msub></mrow></math></span>, and the 1-dB compression point on temperature is studied in detail. The device under consideration has a metal gate contact which offers opportunities to tune its performance parameters like on-current, off-current and threshold voltage. A comparative analysis of the designed device with various devices is also carried out to validate the device design.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"165 ","pages":"Article 106813"},"PeriodicalIF":1.9,"publicationDate":"2025-07-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144749933","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

An intelligent thermo-mechanical coupling collaborative design technique for 2.5D chiplet heterogeneous integration (CHI) system 2.5D晶片异质集成（CHI）系统的智能热-机械耦合协同设计技术

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-07-24 DOI: 10.1016/j.mejo.2025.106801

Yu Fu , Guoliang Li , Guangbao Shan , Zeyu Chen , Hongrui Zhao , Yintang Yang

引用次数: 0

A 600-V half-bridge gate drive circuit with high-speed and high-noise-immunity level shifter 一种带高速高抗噪电平移档器的600 v半桥栅驱动电路

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-07-23 DOI: 10.1016/j.mejo.2025.106816

Xupeng Wang , Xiaowu Cai , Yu Lu , Jianying Dang , Longli Pan , Jian Lu , Liang Shan , Lei Wang , Bo Li

{"title":"A 600-V half-bridge gate drive circuit with high-speed and high-noise-immunity level shifter","authors":"Xupeng Wang , Xiaowu Cai , Yu Lu , Jianying Dang , Longli Pan , Jian Lu , Liang Shan , Lei Wang , Bo Li","doi":"10.1016/j.mejo.2025.106816","DOIUrl":"10.1016/j.mejo.2025.106816","url":null,"abstract":"<div><div>Half-bridge drive circuits have been extensively adopted in power electronics due to their efficiency in energy conversion. However, transient noise poses significant challenges to the reliability of high-voltage power driver chips. It is difficult to simultaneously meet high operating frequencies and reliability using conventional structures. To address this limitation, this paper proposes a new high-voltage level shifter (LS). The circuit integrates the common-mode noise cancellation and the RS flip-flop uncertain state cancellation circuit to effectively mitigate common and differential-mode transient noise without requiring RC filters. It achieves a better trade-off between d<em>V</em>/dt noise immunity and propagation delay. The LS structure is implemented using a 1 μm 600 V Bipolar-CMOS-DMOS process. Simulations and experiments validate the LS's capability to achieve d<em>V</em>/dt noise immunity of up to 160 V/ns, with a propagation delay of only 4.27 ns. Additionally, it enables a negative VS swing of −11.2 V under a 15 V supply voltage. This significantly enhances reliability and reduces delay compared to conventional LS.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"165 ","pages":"Article 106816"},"PeriodicalIF":1.9,"publicationDate":"2025-07-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144749934","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A 1.8-μA quiescent current fast-transient capacitorless LDO with 99.99% current efficiency based on local positive-feedback and high-pass feed-forward compensation technique 基于局部正反馈和高通前馈补偿技术的1.8 μA静态电流快暂态无电容LDO，电流效率99.99%

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-07-23 DOI: 10.1016/j.mejo.2025.106805

Min Li, Yongqing Wang, Weiwei Yu, Penghao Li, Xiaosong Wang, Yige Geng, Qisheng Zhang

{"title":"A 1.8-μA quiescent current fast-transient capacitorless LDO with 99.99% current efficiency based on local positive-feedback and high-pass feed-forward compensation technique","authors":"Min Li, Yongqing Wang, Weiwei Yu, Penghao Li, Xiaosong Wang, Yige Geng, Qisheng Zhang","doi":"10.1016/j.mejo.2025.106805","DOIUrl":"10.1016/j.mejo.2025.106805","url":null,"abstract":"<div><div>This paper presents a fast transient response capacitorless low-dropout regulator (CL-LDO) with 1.8 <span><math><mi>μ</mi></math></span>A quiescent current and current efficiency up to 99.99 <span><math><mtext>%</mtext></math></span>. A local positive-feedback technique (LPFB) is adopted to improve the loop bandwidth and increase the charging/discharging currents of power transistor gate, which is to enhance transient response. Moreover, the technique introduces negative resistance to achieve higher loop gain and better load regulation. A high-pass feed-forward compensation technique is proposed, which improves the stability of the loop under light load. Additionally, a class-AB nonlinear transient enhancement structure further increases transient response. Validated by the CMOS 0.18 <span><math><mi>μ</mi></math></span>m process, the chip area is 0.04216 <span><math><msup><mrow><mi>mm</mi></mrow><mrow><mn>2</mn></mrow></msup></math></span>. The experimental results demonstrate that it has a transient overshoot/undershoot voltage of 722 mV/781 mV with an edge time of 2.5 ns. It also accomplishes a better load regulation of 0.045 mV/mA. Finally, the proposed CL-LDO achieves a FoM of 0.55 ps. Competitive FOMs value indicate the effectiveness of the techniques proposed.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"164 ","pages":"Article 106805"},"PeriodicalIF":1.9,"publicationDate":"2025-07-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144702541","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Low-phase-noise wideband dual-core quad-mode VCO using a mode-switching transformer 采用模式开关变压器的低相位噪声宽带双核四模压控振荡器

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-07-22 DOI: 10.1016/j.mejo.2025.106815

Shaofeng Tan , Xing Zhao , Chao Li , Binhong Li , Jianzhong Li , Tianchun Ye , Bo Gao , Jun Luo

引用次数: 0

A comprehensive study on the electrical effects of avalanche region on GaN Schottky barrier IMPATT diodes through injection phases 雪崩区通过注入相对GaN肖特基势垒IMPATT二极管电效应的综合研究

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-07-22 DOI: 10.1016/j.mejo.2025.106818

Xuan Huang, Lin-An Yang, Jian-Hua Zhou, Xin-Yi Wang, Dong-Liang Chen, Xiao-Hua Ma, Yue Hao

{"title":"A comprehensive study on the electrical effects of avalanche region on GaN Schottky barrier IMPATT diodes through injection phases","authors":"Xuan Huang, Lin-An Yang, Jian-Hua Zhou, Xin-Yi Wang, Dong-Liang Chen, Xiao-Hua Ma, Yue Hao","doi":"10.1016/j.mejo.2025.106818","DOIUrl":"10.1016/j.mejo.2025.106818","url":null,"abstract":"<div><div>The article investigates the effect of the avalanche region on GaN Schottky barrier IMPATT diodes using Sentaurus TCAD. The results show that as the avalanche region shrinks, thermal field emission deteriorates, resulting in a rapid decline of the avalanche multiplication factor and injection phase. It degrades the initiating oscillation and output. Narrowing the avalanche region from 125 nm to 50 nm, the injection phase decreases from 154°–169° to 119°–136°. At the designed frequency of 120 GHz, the start-up efficiency and speed are reduced by 18 % and 26 %, respectively. Additionally, the oscillating output capability and stability decrease by 50 % and 53 %. Meanwhile, the radio frequency conversion power drops by 40 %, whereas its efficiency improves by 50 %, lowering the junction temperature difference from 703 °C to 290 °C. It presents a method to adjust trade-offs between pulse width and instantaneous output power by the width of the avalanche region for the pulsed wave mode that is preferred in the device.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"165 ","pages":"Article 106818"},"PeriodicalIF":1.9,"publicationDate":"2025-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144738288","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Effect of polarized AlGaN/GaN structure-based field plate on the electric properties of a 4H-SiC Schottky barrier diode 极化AlGaN/GaN结构场极板对4H-SiC肖特基势垒二极管电性能的影响

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-07-22 DOI: 10.1016/j.mejo.2025.106814

Feng He , Wenting Zhang , Xiamin Hao , Xinyu Li , Ruifen Nie , Rui Jin

{"title":"Effect of polarized AlGaN/GaN structure-based field plate on the electric properties of a 4H-SiC Schottky barrier diode","authors":"Feng He , Wenting Zhang , Xiamin Hao , Xinyu Li , Ruifen Nie , Rui Jin","doi":"10.1016/j.mejo.2025.106814","DOIUrl":"10.1016/j.mejo.2025.106814","url":null,"abstract":"<div><div>By employing advanced physical models with the help of TCAD, we studied the impact of polarized AlGaN/GaN field plates on 4H-SiC Schottky barrier diodes (SBDs). In a traditional 4H-SiC SBD with a p-SiC field ring, the strongest electric field occurs at both the junction interface and the edge of the field ring, leading to premature breakdown and increased leakage current under reverse bias conditions. The proposed polarized AlGaN/GaN structure-based field plate evens out the electric field distribution between the AlGaN/GaN layer and the field plate dielectric layer, thereby enhancing the breakdown voltage (BV) of the device. Additionally, an optimum design strategy is detailed in the paper, using the length of the field plate (<em>L</em><sub>FP</sub>) and thickness of the field plate dielectric layer (<em>T</em><sub>FP</sub>) as control variables. Furthermore, this study also examines how surface defects and bulk traps would affect the device characteristics and discusses the physical mechanisms. It is found that donor-type traps would strongly add to device performance degradation.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"164 ","pages":"Article 106814"},"PeriodicalIF":1.9,"publicationDate":"2025-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144711116","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Design of irises-stabilized substrate integrated waveguide bandpass filters on silicon-based wafer-level packaging process 基于硅基晶圆级封装工艺的虹膜稳定基板集成波导带通滤波器设计

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-07-22 DOI: 10.1016/j.mejo.2025.106808

Jie Liu , Yi Le , Jun Liu , Guodong Su , Zengda Wang , Yuehang Xu

{"title":"Design of irises-stabilized substrate integrated waveguide bandpass filters on silicon-based wafer-level packaging process","authors":"Jie Liu , Yi Le , Jun Liu , Guodong Su , Zengda Wang , Yuehang Xu","doi":"10.1016/j.mejo.2025.106808","DOIUrl":"10.1016/j.mejo.2025.106808","url":null,"abstract":"<div><div>This article presents an irises-stabilized substrate integrated waveguide (IS-SIW) structure for bandpass filter (BPF) designs in the wafer-level packaging (WLP) process. The IS-SIW employs irises to reinforce the SIW cavity. They can effectively protect physical structure of SIW from wafer warpage, which is caused by thermal expansion. By introducing advanced coplanar waveguide (CPW) wave mode converters and H-slotted resonators, the IS-SIW can generate a passband with two transmission poles (TPs) and two transmission zeros (TZs). Additionally, the feedlines are designed with stepped-impedance resonators (SIRs) and defected ground structures (DGSs) ensure interconnection and impedance matching between the IS-SIW and the ground-signal-ground (GSG) ports. Finally, three IS-SIW BPF prototypes were designed and fabricated. Measurement results align well with the theoretical analysis and simulation results. These BPFs achieve miniaturization and at least 30 dB out-of-band suppression. Therefore, the proposed IS-SIW BPFs show great potential for applications in millimeter-wave short-range radar and communication systems.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"165 ","pages":"Article 106808"},"PeriodicalIF":1.9,"publicationDate":"2025-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144749932","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A linearized PVT-robust FVF input buffer with triode transconductance feedback achieving SFDR > 90 dB at 500-MHz input 具有三极管跨导反馈的线性化pvt鲁棒FVF输入缓冲器，在500-MHz输入时实现SFDR > 90 dB

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-07-22 DOI: 10.1016/j.mejo.2025.106802

Junye Su, Shubin Liu, Haolin Han

{"title":"A linearized PVT-robust FVF input buffer with triode transconductance feedback achieving SFDR > 90 dB at 500-MHz input","authors":"Junye Su, Shubin Liu, Haolin Han","doi":"10.1016/j.mejo.2025.106802","DOIUrl":"10.1016/j.mejo.2025.106802","url":null,"abstract":"<div><div>This paper presents a high-linearity input buffer leveraging triode-transconductance feedback (TTF) flipped voltage followers for RF sampling data converters. The proposed source follower incorporates a triode-biased transistor to enhance linearity by cancelling the third harmonic distortion (HD3). Under a 1-GS/s sampling rate, the buffer achieves SFDR of 90.4 dB and SNDR of 74.6 dB at Nyquist frequency. A dedicated constant-<span><math><msub><mrow><mi>g</mi></mrow><mrow><mi>m</mi></mrow></msub></math></span> current source and channel split bias circuits are also introduced in this work to accommodate process, voltage, and temperature (PVT) conditions. Simulated under 5corners, −40 to125  <span><math><mo>±</mo></math></span> 2.5<span><math><mtext>%</mtext></math></span>, the prototype buffer designed in 28-nm CMOS maintains SFDR <span><math><mo>≥</mo></math></span> 80 dB, improved by approximately 30 dB. With a power consumption of 23.54mW, the proposed buffer attains a figure of merit (FoM) of 173.0 dB, demonstrating an excellent trade-off among linearity, bandwidth and power consumption.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"164 ","pages":"Article 106802"},"PeriodicalIF":1.9,"publicationDate":"2025-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144686336","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Investigation of trench SiC MOSFETs with double deep trench under avalanche stress 雪崩应力下双深沟槽SiC mosfet的研究

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-07-22 DOI: 10.1016/j.mejo.2025.106809

Wenhan Yang, Xiaoyan Tang, Yibo Zhang, Jingyu Li, Haobo Kang, Weishuo Guo, Hao Yuan, Qingwen Song, Yuming Zhang

{"title":"Investigation of trench SiC MOSFETs with double deep trench under avalanche stress","authors":"Wenhan Yang, Xiaoyan Tang, Yibo Zhang, Jingyu Li, Haobo Kang, Weishuo Guo, Hao Yuan, Qingwen Song, Yuming Zhang","doi":"10.1016/j.mejo.2025.106809","DOIUrl":"10.1016/j.mejo.2025.106809","url":null,"abstract":"<div><div>In this article, the dynamic avalanche reliability of 1200-V silicon carbide (SiC) power metal-oxide semiconductor field-effect transistors (MOSFETs) with double deep trench(DDT-MOS) is studied. During unclamped inductive switching (UIS) measurement, a significant difference in avalanche capability was observed between the DDT-MOS. The damage analysis suggests that DDT-MOS show two failure mechanisms: burnout and gate failure during the UIS test. Through TCAD simulations and damage analysis, it can be determined that a serious temperature concentration occurred during the avalanche. Due to the characteristic that the avalanche current increases exponentially with the avalanche voltage once the drain–source voltage exceeds the avalanche threshold, the morphological differences in the P-well region caused by etching discrepancies will lead to a serious temperature concentration, which will deteriorate the avalanche capability and lead to the abnormal failure of the DDT-MOS. In addition, the uncontrollable value and distribution of etching discrepancies in deep trench is also a plausible explanation to explain the significant difference in avalanche capability between the DDT-MOS.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"164 ","pages":"Article 106809"},"PeriodicalIF":1.9,"publicationDate":"2025-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144702544","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0