Microelectronics Journal最新文献_第10页

Novel accurate steady-state thermal resistance model for power chips embedded in TTSVs heat dissipation array 嵌入 TTSV 散热阵列的功率芯片的新型精确稳态热阻模型

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2024-07-25 DOI: 10.1016/j.mejo.2024.106336

Linhong Lu , Xinghua Fu , Rui Hu , Fashun Yang , Jiexin Lin , Zhongchen Bai , Kui Ma

引用次数: 0

N-DIBL optimization of NC-GAAFET NW for low power fast switching applications 针对低功耗快速开关应用的 NC-GAAFET NW 的 N-DIBL 优化

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2024-07-24 DOI: 10.1016/j.mejo.2024.106321

Vivek Kumar, Ravindra Kumar Maurya, Kavicharan Mummaneni

引用次数: 0

A 0.91-μA-quiescent-current capacitor-less LDO with sub-threshold transient enhancement and bulk-driven feed-forward supply ripple cancellation 静态电流为 0.91μA 的无电容 LDO，具有亚阈值瞬态增强和批量驱动前馈电源纹波消除功能

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2024-07-23 DOI: 10.1016/j.mejo.2024.106311

Yuxin Zhang, Jueping Cai, Jizhang Chen, Lifeng Jiang

{"title":"A 0.91-μA-quiescent-current capacitor-less LDO with sub-threshold transient enhancement and bulk-driven feed-forward supply ripple cancellation","authors":"Yuxin Zhang, Jueping Cai, Jizhang Chen, Lifeng Jiang","doi":"10.1016/j.mejo.2024.106311","DOIUrl":"10.1016/j.mejo.2024.106311","url":null,"abstract":"<div><p>This paper presents a capacitor-less low-dropout (OCL-LDO) regulator that features a low quiescent current for low power applications. To enhance the transient response of proposed OCL-LDO, a sub-threshold transient enhancement circuit including a transient signal input stage, a current subtractor, and a current amplifier is suggested. Meanwhile, a circuit made up of a bulk-driven ripple feed-forward circuit and a ripple introduction circuit is developed in order to improve PSR of the OCL-LDO. The proposed OCL-LDO is fabricated in 0.18 <span><math><mi>μ</mi></math></span>m standard CMOS process and has an active area of 0.053 mm<sup>2</sup>. Based on measurement results, the proposed OCL-LDO has a maximum load current of 100 mA at 1.2 V input and 1 V output, and a minimum quiescent current of 0.91 <span><math><mi>μ</mi></math></span>A. The overshoot voltage and undershoot voltage are 199 mV and 204 mV, respectively. PSR of the OCL-LDO is <span><math><mo>−</mo></math></span>71.8 dB at 1 KHz when the load current is 100 mA. Furthermore, the OCL-LDO exhibits a load regulation of 11.1 <span><math><mi>μ</mi></math></span>V/mA and a line regulation of 1.05 mV/V.</p></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-07-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141849731","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A reconfigurable multi-precision quantization-aware nonlinear activation function hardware module for DNNs 用于 DNN 的可重构多精度量化感知非线性激活函数硬件模块

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2024-07-22 DOI: 10.1016/j.mejo.2024.106346

Qi Hong , Zhiming Liu , Qiang Long , Hao Tong , Tianxu Zhang , Xiaowen Zhu , Yunong Zhao , Hua Ru , Yuxing Zha , Ziyuan Zhou , Jiashun Wu , Hongtao Tan , Weiqiang Hong , Yaohua Xu , Xiaohui Guo

{"title":"A reconfigurable multi-precision quantization-aware nonlinear activation function hardware module for DNNs","authors":"Qi Hong , Zhiming Liu , Qiang Long , Hao Tong , Tianxu Zhang , Xiaowen Zhu , Yunong Zhao , Hua Ru , Yuxing Zha , Ziyuan Zhou , Jiashun Wu , Hongtao Tan , Weiqiang Hong , Yaohua Xu , Xiaohui Guo","doi":"10.1016/j.mejo.2024.106346","DOIUrl":"10.1016/j.mejo.2024.106346","url":null,"abstract":"<div><p>In recent years, the increasing variety of nonlinear activation functions (NAFs) in deep neural networks (DNNs) has led to higher computational demands. However, hardware implementation faces challenges such as lack of flexibility, high hardware cost, and limited accuracy. This paper proposes a highly flexible and low-cost hardware solution for implementing activation functions to overcome these issues. Based on the piecewise linear (PWL) approximation method, our method supports NAFs with different accuracy configurations through a customized implementation strategy to meet the requirements in different scenario applications. In this paper, the symmetry of the activation function is investigated, and incorporate curve translation preprocessing and data quantization to significantly reduce hardware storage costs. The modular hardware architecture proposed in this study supports NAFs of multiple accuracies, which is suitable for designing deep learning neural network accelerators in various scenarios, avoiding the need to design dedicated hardware circuits for the activation function layer and enhances circuit design efficiency. The proposed hardware architecture is validated on the Xilinx XC7Z010 development board. The experimental results show that the average absolute error (AAE) is reduced by about 35.6 % at a clock frequency of 312.5 MHz. Additionally, the accuracy loss of the model is maximized to −0.684 % after replacing the activation layer function of DNNs under the PyTorch framework.</p></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141841666","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Ambipolar current suppression in drain elevated TFET using a novel extended drain structure with a moderate doping profile 利用具有适度掺杂特征的新型扩展漏极结构抑制漏极升高型 TFET 中的两极电流

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2024-07-22 DOI: 10.1016/j.mejo.2024.106302

Manivannan T.S. , K.R. Pasupathy , G. Lakshminarayanan

{"title":"Ambipolar current suppression in drain elevated TFET using a novel extended drain structure with a moderate doping profile","authors":"Manivannan T.S. , K.R. Pasupathy , G. Lakshminarayanan","doi":"10.1016/j.mejo.2024.106302","DOIUrl":"10.1016/j.mejo.2024.106302","url":null,"abstract":"<div><p>In this paper, a simple and compact silicon-based Elevated and Extended Drain with Hetero-Dielectric Gate Oxide TFET (EED HDGO TFET) is proposed to suppress the ambipolar current in Elevated Drain TFET (ED TFET). The proposed device structure uses a moderately doped drain with a doping concentration of <span><math><mo>∼</mo></math></span>10<sup>18</sup> cm<sup>−3</sup> and a high drain length of <span><math><mo>∼</mo></math></span>50–100 nm. The combination of the moderate drain doping profile and the extended drain length reduced the impact of the electrostatic potential from the positive voltage of the drain electrode on the channel–drain junction. This structural technique widens the tunneling width at the channel–drain region causing the tunneling current to decrease significantly. The tunneling width is further increased by structurally isolating the channel–drain junction region from the gate electrode. Thus, distancing the channel–drain junction from both the gate electric field and the static drain potential of the drain electrode causes full suppression of the ambipolar (I<sub>amb</sub>) current. The proposed structure yields I<sub>amb</sub> and I<sub>off</sub> as low as <span><math><mo>∼</mo></math></span>10<sup>−18</sup> A/<span><math><mrow><mi>μ</mi><mi>m</mi></mrow></math></span> and <span><math><mo>∼</mo></math></span>10<sup>−17</sup> A/<span><math><mrow><mi>μ</mi><mi>m</mi></mrow></math></span> respectively, while maintaining the I<sub>on</sub> as <span><math><mo>∼</mo></math></span>0.3 mA. The device is optimized for low power and high-speed digital circuits through intensive parametric analysis on gate–drain C<sub>gd</sub> and the gate–source C<sub>gs</sub> capacitances for various device parameters.</p></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141852291","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

An 8b-Precison 16-Kb FDSOI 8T SRAM CIM macro based on time-domain for energy-efficient edge AI devices 基于时域的 8b-precison 16-Kb FDSOI 8T SRAM CIM 宏，用于高能效边缘人工智能设备

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2024-07-21 DOI: 10.1016/j.mejo.2024.106308

Yongliang Zhou , Yiming Wei , Tianzhu Xiong , Zixuan Zhou , Zhen Yang , Xiao Lin , Wei Hu , Xiulong Wu , Chunyu Peng

{"title":"An 8b-Precison 16-Kb FDSOI 8T SRAM CIM macro based on time-domain for energy-efficient edge AI devices","authors":"Yongliang Zhou , Yiming Wei , Tianzhu Xiong , Zixuan Zhou , Zhen Yang , Xiao Lin , Wei Hu , Xiulong Wu , Chunyu Peng","doi":"10.1016/j.mejo.2024.106308","DOIUrl":"10.1016/j.mejo.2024.106308","url":null,"abstract":"<div><p>Compute-in-memory has been increasingly appreciated by researchers as a well-suited hardware accelerator in convolutional neural networks (CNNs), because it can achieve low power consumption and high inference accuracy. This work presents a novel TD-CIM structure using:1) A Capacitor Charging scheme that uses Compact 8T Model for multiply-and-accumulate (MAC) Operations with serials inputs in Time Domain Level; 2) a new replicated bit-line time-domain converter (RBL-TDC) to achieve the quantization of the multiply-accumulate operations with high accuracy; 3) A 22 nm FD-SOI 16 Kb TD-CIM macro fabricated using foundry provided compact 8T-SRAM cells, which achieves normalized energy efficiency(EF) of 5816.5 TOPS/W, normalized area efficiency(64TOPS/mm<sup>2</sup>), and 8-bit weight for 8-bit serials inputs with 64 accumulations per cycle, as well as output precision(14b) in the MAC operation. This work also obtains an inference accuracy of 92.57 % on the VGG-16 network using the Cifar10 dataset over PVT variations.</p></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-07-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141954598","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

An auto-zeroing chopper-stabilized capacitively coupled instrumentation amplifier with 25-Vpp common-mode interference tolerance 具有 25 Vpp 的自动归零斩波稳定电容耦合仪表放大器</mml:msub

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2024-07-20 DOI: 10.1016/j.mejo.2024.106303

Jiacheng Liu , Yuke Shen , Shubin Liu , Ruixue Ding , Zhangming Zhu

引用次数: 0

Genetic neural network based background calibration method for pipeline ADC 基于遗传神经网络的管道 ADC 背景校准方法

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2024-07-20 DOI: 10.1016/j.mejo.2024.106317

Long Li , Yongsheng Yin , Jiashen Li , Yukun Song , Honghui Deng , Hongmei Chen , Luotian Wu , Muqi Li

引用次数: 0

Source/drain extension asymmetric counter-doping for suppressing channel leakage in stacked nanosheet transistors 源极/漏极扩展非对称反掺杂抑制叠层纳米片晶体管中的沟道泄漏

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2024-07-20 DOI: 10.1016/j.mejo.2024.106347

Qingkun Li , Lei Cao , Qingzhu Zhang , Lianlian Li , Xuexiang Zhang , Chuqiao Niu , Guanqiao Sang , Yunjiao Bao , Huaxiang Yin , Zhenhua Wu

{"title":"Source/drain extension asymmetric counter-doping for suppressing channel leakage in stacked nanosheet transistors","authors":"Qingkun Li , Lei Cao , Qingzhu Zhang , Lianlian Li , Xuexiang Zhang , Chuqiao Niu , Guanqiao Sang , Yunjiao Bao , Huaxiang Yin , Zhenhua Wu","doi":"10.1016/j.mejo.2024.106347","DOIUrl":"10.1016/j.mejo.2024.106347","url":null,"abstract":"<div><p>In the relentless pursuit of semiconductor device scaling, stacked silicon nanosheet gate-all-around field-effect transistors (NSFETs) are emerging as key candidates for sub-3nm technology nodes. However, the challenge of channel leakage in these devices is critical and necessitates innovative solutions. A novel SDE asymmetric counter-doping technique is proposed in this study. It investigates the impact of source/drain extension on device performance using different process schemes through three-dimensional technical computer-aided design (3D TCAD) simulations. The simulations demonstrate a comprehensive technically advantages for 25.2 %/16.65 % reduction in the off-state leakage, 27.36 %/15.03 % improvement in the on-off current ratio of N/P NSFETs, respectively. Furthermore, it shows more performance gain as the gate length scaling beyond 3 nm technology nodes. The compatibility of the asymmetric counter-doping method with mainstream NSFET integration flows and its scalability to 10 nm gate lengths indicate that it is a promising approach to optimize NSFETs performance with little extra process cost.</p></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-07-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141845939","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Quantized CNN-based efficient hardware architecture for real-time hand gesture recognition 基于量化 CNN 的实时手势识别高效硬件架构

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2024-07-19 DOI: 10.1016/j.mejo.2024.106345

Mohita Jaiswal, Vaidehi Sharma, Abhishek Sharma, Sandeep Saini, Raghuvir Tomar

{"title":"Quantized CNN-based efficient hardware architecture for real-time hand gesture recognition","authors":"Mohita Jaiswal, Vaidehi Sharma, Abhishek Sharma, Sandeep Saini, Raghuvir Tomar","doi":"10.1016/j.mejo.2024.106345","DOIUrl":"10.1016/j.mejo.2024.106345","url":null,"abstract":"<div><p>Nowadays, Convolutional Neural Networks (CNN) have been widely adopted for vision-based hand gesture recognition. Several existing CNN architectures designed for gesture classification perform well with high accuracy but require a high memory footprint and processing when deployed on low-power embedded devices. To address this issue, we present a quantized CNN-based efficient framework for meeting real-life hand gesture recognition challenges. The proposed quantized CNN is designed and implemented using the FINN-based pipelined streaming architecture on an FPGA. Moreover, hardware-based optimizations are used to minimize the resources needed and to achieve fast memory access. Experimental results demonstrate that the developed recognition system achieves an average accuracy of 92% on the numeral database of Indian Sign Language (ISL). Additionally, our optimized design attains an inference latency of 0.85ms for real-time single gesture prediction on the PYNQ Zynq Ultrascale (ZU) FPGA, consuming only 3.63 W of power. The proposed design achieves a better trade-off between hardware resource utilization and speed performance, over previous designs.</p></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-07-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141951257","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0