Microelectronics Journal最新文献_第10页

Key space estimation and security analysis of superlattice physical unclonable function 超晶格物理不可克隆函数的密钥空间估计与安全性分析

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2024-07-16 DOI: 10.1016/j.mejo.2024.106320

引用次数: 0

Design of RISC-V out-of-order processor based on segmented exclusive or Gshare branch prediction 基于分段排他或 Gshare 分支预测的 RISC-V 失序处理器设计

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2024-07-14 DOI: 10.1016/j.mejo.2024.106334

{"title":"Design of RISC-V out-of-order processor based on segmented exclusive or Gshare branch prediction","authors":"","doi":"10.1016/j.mejo.2024.106334","DOIUrl":"10.1016/j.mejo.2024.106334","url":null,"abstract":"<div>To address the balanced requirements of performance, power consumption, and area in embedded systems, this paper introduces a 32-bit out-of-order processor based on the RISC-V instruction set, and the processor supports interrupt handling. This processor is designed to support the RV32IMC instruction subset and utilizes a four-stage pipeline structure featuring sequential instruction fetching, out-of-order execution, and out-of-order write-back. The main contributions are as follows:1) The segmented exclusive or G-share branch prediction scheme for embedded processors is proposed, which provides high branch prediction accuracy when the capacity of pattern history table (PHT) is small. 2) The work undertaken by hardware and software during interrupt response is reasonably divided, which allows for fast interrupt response with minimal resource consumption. Furthermore, the interrupt response time in vectored mode is reduced by simultaneously stacking the control and status registers (CSRs) and obtaining the interrupt service routine (ISR) entry address. Executing branch prediction-related programs within an identical environment, the processor detailed in this paper demonstrates an average prediction accuracy improvement of 1.2 % over G-share and 0.6 % over bi-mode branch prediction when employing the segmented exclusive or G-share branch prediction scheme. Building on this foundation, the on-chip debugging system and memory management unit have been implemented. The processor reaches 1.389 Dhrystone/MHz and 2.802 Coremark/MHz.</div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-07-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141692931","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Broad spectral response of large array CIS with BSI-PD from visible light to near ultraviolet 采用 BSI-PD 的大型阵列 CIS 具有从可见光到近紫外光的宽光谱响应

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2024-07-14 DOI: 10.1016/j.mejo.2024.106344

引用次数: 0

Novel design and modelling of SiC junction barrier Schottky diode with improved Baliga FOM under high-temperature applications 在高温应用条件下改进 Baliga FOM 的碳化硅结势垒肖特基二极管的新型设计和建模

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2024-07-14 DOI: 10.1016/j.mejo.2024.106343

{"title":"Novel design and modelling of SiC junction barrier Schottky diode with improved Baliga FOM under high-temperature applications","authors":"","doi":"10.1016/j.mejo.2024.106343","DOIUrl":"10.1016/j.mejo.2024.106343","url":null,"abstract":"<div>A novel 650 V/50 A 4H–SiC junction barrier Schottky diode (JBSD) featuring a stripe-square composite cell design (SSC-JBSD) is proposed in this paper to improve the high-temperature performance. A model of the resistance of the JBS (RJBS) is established to explain the mechanism. The particular cell design of the SSC-JBSD forms a circular current distribution, which can improve the forward current and suppress the degeneration of RJBS caused by the lower electron mobility at high temperatures. The combination of the stripe and square P+ regions achieves a high current and a lower power loss under high temperature while maintaining a high breakdown voltage. Specifically, the power loss of the SSC-JBSD with a forward current of 50 A only increases by 6.9 % under 450 K compared to that under 300 K, while that of the conventional JBS diode (Conv-JBSD) increases by 14.1 %. And the Baliga figure of merit (FOM) of the SSC-JBSD is 15.6 % higher than that of the Conv-JBSD under a temperature of 450 K. The on-state self-heating measurement shows that the temperature of the SSC-JBSD is approximately 30 K lower than that of the Conv-JBSD after 5 s of constant on-state operation with a forward current of 50 A. The proposed SSC-JBSD demonstrates superior performance at high temperatures, making it an available replacement for Conv-JBSD in harsh environments characterized by high temperatures and large currents.</div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-07-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141637419","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Characterizing parameter variations for enhanced performance and adaptability in 3 nm MBCFET technology 表征参数变化，提高 3 纳米 MBCFET 技术的性能和适应性

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2024-07-14 DOI: 10.1016/j.mejo.2024.106338

{"title":"Characterizing parameter variations for enhanced performance and adaptability in 3 nm MBCFET technology","authors":"","doi":"10.1016/j.mejo.2024.106338","DOIUrl":"10.1016/j.mejo.2024.106338","url":null,"abstract":"<div>With the continuous scaling down of semiconductor devices, traditional transistor architectures face significant challenges in maintaining performance and power efficiency. Multi-bridge channel field-effect transistors (MBCFETs) are promising candidates for next-generation of transistors, enabling significant size reduction while preserving high performance. This paper investigates both n-type and p-type 3-nm MBCFETs with a focus on their behavior under diverse operating conditions. The study examines the influence of doping concentration, sheet thickness, temperature, device width, and the number of sheets, on the device's functionality aiming for high-performance applications. Doping concentrations of acceptors and donors ranging from 1 × 10 15 cm−3 - 9 × 10 17 cm−3 and 1 × 10 17 cm−3 - 9 × 10 19 cm−3, respectively, to observe their impact on device performance. Similarly, sheet thicknesses from 1 nm to 2 nm and device widths from 3 nm to 30 nm are analyzed to understand the scaling effects. The temperature varies from 273.15 K to 573.15 K to simulate different operational environments, while the number of sheets, ranging from 1 to 7, is adjusted to evaluate structural effects on device behavior. By extracting the subthreshold swing (SS), threshold voltage (Vth), ON-current (ION), OFF-current (IOFF), and the ION/IOFF ratio, the study offers valuable insights into the suitability and potential applications of N-MBCFET and P-MBCFET devices at the ultra-scaled 3 nm dimension. At room temperatures, the SS achieves 60 mV dec⁻1 for n-type and 64 mV dec⁻1 for p-type which indicates proper switching speed, with corresponding ON/OFF ratios of 2 × 106 and 1 × 105 for n-type and p-type, respectively. This study makes notable contributions to the field of nanoscale transistor technology, aiding in the design and optimization of future electronic devices.</div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-07-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141622833","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A high constancy and noise suppression voltage shift generator in SEIR-based BIST circuit for ADC linearity test 用于 ADC 线性测试的基于 SEIR 的 BIST 电路中的高恒定性和噪声抑制电压偏移发生器

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2024-07-14 DOI: 10.1016/j.mejo.2024.106341

引用次数: 0

Power-efficient 12-bit 800 MS/s voltage-time hybrid domain ADC with split TDC in 28 nm CMOS 采用 28 纳米 CMOS 的高能效 12 位 800 MS/s 电压-时间混合域 ADC，带分路 TDC

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2024-07-14 DOI: 10.1016/j.mejo.2024.106340

引用次数: 0

A novel design of hysteretic comparator circuit towards GaN-based power IC 面向氮化镓基功率集成电路的新型滞后比较器电路设计

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2024-07-14 DOI: 10.1016/j.mejo.2024.106339

{"title":"A novel design of hysteretic comparator circuit towards GaN-based power IC","authors":"","doi":"10.1016/j.mejo.2024.106339","DOIUrl":"10.1016/j.mejo.2024.106339","url":null,"abstract":"<div>This paper proposes a hysteretic comparator circuit employing a positive feedback loop composed of all N-type devices towards GaN-based power integration circuits. By combining a source follower with comparator, the proposed hysteretic comparator circuit avoids the dependence on resistors, thus improving the integration density. To demonstrate the novelty, feasibility, and advantages of the proposed circuit, not only GaN-based but also Si-based circuits are investigated by simulations in ADS and Cadence, respectively. Simulated by the cadence virtuoso tool using TSMC 180 nm technology, it exhibits a layout area of 171.08 μm2, signal gain of 55.74 dB at low frequency, and maximum static power dissipation of 364.6 μW when the power supply is 3.3 V. In addition, it's verified that a signal gain of 55.11 dB at low frequency, transition time of 0.2 ns, and maximum static power dissipation of 2.064 W when the power supply is 12 V are achieved in GaN-based circuit according to simulation results in ADS. Consequently, compared with other mainstream or previously reported circuit in the same conditions, more ideal working performance and compact size are achieved by the proposed circuit, providing an advantageous strategy for monolithically integrating hysteretic comparator circuit in GaN-based power IC.</div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-07-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141637418","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Distance optimization KNN and EMD based lightweight hardware IP core design for EEG epilepsy detection 基于距离优化 KNN 和 EMD 的脑电图癫痫检测轻量级硬件 IP 核设计

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2024-07-11 DOI: 10.1016/j.mejo.2024.106335

引用次数: 0

A fully digital timing background calibration algorithm based on first-order auto-correlation for time-interleaved ADCs 基于时间交错 ADC 一阶自相关性的全数字时序背景校准算法

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2024-07-09 DOI: 10.1016/j.mejo.2024.106330

引用次数: 0