Microelectronics Journal最新文献_第10页

Enhancing the reliability of CSP solder joints under thermal cycling conditions through particle swarm optimization of an improved BP neural network 通过改进型 BP 神经网络的粒子群优化提高热循环条件下 CSP 焊点的可靠性

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2024-11-14 DOI: 10.1016/j.mejo.2024.106484

Miao Zhu, Xuexia Yang, Yanxi Sun, Ze Wang, Erqiang Liu

{"title":"Enhancing the reliability of CSP solder joints under thermal cycling conditions through particle swarm optimization of an improved BP neural network","authors":"Miao Zhu, Xuexia Yang, Yanxi Sun, Ze Wang, Erqiang Liu","doi":"10.1016/j.mejo.2024.106484","DOIUrl":"10.1016/j.mejo.2024.106484","url":null,"abstract":"<div><div>The packaging of chip-scale (CSP) devices plays a pivotal role in enhancing the reliability of CSP under thermal cycling conditions, largely due to the intricate structure and the recurrent alterations in the actual operating environment. The objective of this study is to enhance the reliability of solder joints by optimising the structural parameters of CSP packaging in order to reduce the strain values at the solder joints. In order to enhance the design efficiency and accuracy of the computational model, the Anand model is adopted in order to define the solder joint parameters, and finite element simulations are conducted using Ansys software. This paper puts forward a novel intelligent algorithm that fuses response surface methodology with a neural network-particle swarm optimization algorithm, thereby enhancing the precision of the system. The method is capable of identifying the combination with the minimum strain value using limited data, thereby addressing the issue of insufficient generalisation ability in conventional methods. The implementation of this method into the model resulted in a minimum strain value of 4.071 × 10<sup>−3</sup>, representing a 37.6 % reduction compared to the original CSP structure. Furthermore, the optimized lifespan is approximately 3.24 times longer than that observed prior to optimization. The approach presented in this paper has the potential to significantly enhance design efficiency and increase the lifespan of components. It offers a novel perspective for optimising the structural parameters of CSP packaging.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"154 ","pages":"Article 106484"},"PeriodicalIF":1.9,"publicationDate":"2024-11-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142661892","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A spike-based background light suppression lock-in pixel for 2D&3D synchronous imaging 用于二维和三维同步成像的基于尖峰的背景光抑制锁定像素

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2024-11-13 DOI: 10.1016/j.mejo.2024.106482

Xiaolin Shi, Xinyao Li, Yujia Mao, Ying Ren

引用次数: 0

A fully-integrated 60-GHz 8-element phased-array transceiver with embedded antenna T/R switch in 65-nm CMOS 65 纳米 CMOS 全集成 60 GHz 8 元相控阵收发器，带嵌入式天线 T/R 开关

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2024-11-12 DOI: 10.1016/j.mejo.2024.106475

Jing Feng , Haipeng Duan , Tao Zhang , Lin Lu , Lei Luo , Yue Liang , Xin Chen , Depeng Cheng , Long He , Xu Wu , Xiangning Fan , Lianming Li

{"title":"A fully-integrated 60-GHz 8-element phased-array transceiver with embedded antenna T/R switch in 65-nm CMOS","authors":"Jing Feng , Haipeng Duan , Tao Zhang , Lin Lu , Lei Luo , Yue Liang , Xin Chen , Depeng Cheng , Long He , Xu Wu , Xiangning Fan , Lianming Li","doi":"10.1016/j.mejo.2024.106475","DOIUrl":"10.1016/j.mejo.2024.106475","url":null,"abstract":"<div><div>This paper presents an 8-element phased-array heterodyne transceiver (TRX) chip for 60-GHz wireless applications. The chip integrates transmit/receive (T/R) elements, bi-directional variable-gain driving amplifiers (BI-VGDAs), up/down mixing chains, and the local oscillator (LO) chain. To support the time division duplexing (TDD) operation and increase output power, a low-loss compact on-chip antenna T/R switch is introduced by embedding it in the power amplifier (PA) power combiner, thereby achieving a high transmitter (TX) output power and low receiver (RX) noise figure (NF), respectively. Fabricated in a 65-nm CMOS process, the proposed phased array TRX chip occupies an area of 5.1 mm × 2.5 mm. With measurements, the TX path provides a 32-dB maximum conversion gain, an 11.3-dBm <em>OP</em><sub>1dB</sub>, and a 16-dBm <em>P</em><sub>sat</sub>, respectively. The RX path achieves a peak gain of 24 dB and an NF of 6.5–9 dB across 57–66 GHz. With the 16-QAM modulation, a 7.04 Gb/s data rate is demonstrated.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"154 ","pages":"Article 106475"},"PeriodicalIF":1.9,"publicationDate":"2024-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142661889","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Hetero dielectric based dual material gate AlGaN channel MISHEMT for enhanced electrical characteristics 基于异质介质的双材料栅氮化铝沟道 MISHEMT，可增强电气特性

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2024-11-12 DOI: 10.1016/j.mejo.2024.106465

Sreelekshmi P.S., Jobymol Jacob

引用次数: 0

Design and implementation of a charge-sharing in-memory-computing macro with sparse feature for quantized neural network 为量化神经网络设计和实现具有稀疏特征的电荷共享内存计算宏

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2024-11-12 DOI: 10.1016/j.mejo.2024.106470

Yihe Liu , Junjie Wang , Shuang Liu , Mingyuan Sun , Xiaoyang Zhang , Jingtao Zhou , Shiqin Yan , RuiCheng Pan , Hao Hu , Yang Liu

{"title":"Design and implementation of a charge-sharing in-memory-computing macro with sparse feature for quantized neural network","authors":"Yihe Liu , Junjie Wang , Shuang Liu , Mingyuan Sun , Xiaoyang Zhang , Jingtao Zhou , Shiqin Yan , RuiCheng Pan , Hao Hu , Yang Liu","doi":"10.1016/j.mejo.2024.106470","DOIUrl":"10.1016/j.mejo.2024.106470","url":null,"abstract":"<div><div>With the rapid development of artificial intelligence technology, in-memory computing has become a research hotspot. In this article, we propose an in-memory computing (IMC) architecture that achieves high energy efficiency and performance. Our work is based on the working mechanism of charge sharing, enabling configurable multi-bit Multiply-Accumulate operations. This work employs a unique bit-cell structure to implement sparse strategies at the bit-level in IMC arrays and compensates for errors caused by non-ideal effects, thus achieving better energy efficiency and performance. A hardware-aware quantification method and a hardware simulation model based on Pytorch have been proposed to evaluate the hardware mapping and compare with other charge domain IMC works. The MNIST and CIFAR-10 datasets have been used to validate algorithm models and chip performance, achieving accuracy rates of 97.6% and 90.5%respectively. The IMC chip was fabricated with a 180 nm CMOS process. The measurement shows that the chip achieves an energy efficiency of 41.8 TOPS/W.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"154 ","pages":"Article 106470"},"PeriodicalIF":1.9,"publicationDate":"2024-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142661890","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Finite element simulation and experimental study of the coupling acoustic field characteristics of ultrasonic waves with internal defects inside microelectronic packaging 微电子封装内部缺陷与超声波耦合声场特性的有限元模拟和实验研究

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2024-11-12 DOI: 10.1016/j.mejo.2024.106479

Yuan Chen , Sitian Li , Dengxue Liu , Xiang Wan , Ming Dong

{"title":"Finite element simulation and experimental study of the coupling acoustic field characteristics of ultrasonic waves with internal defects inside microelectronic packaging","authors":"Yuan Chen , Sitian Li , Dengxue Liu , Xiang Wan , Ming Dong","doi":"10.1016/j.mejo.2024.106479","DOIUrl":"10.1016/j.mejo.2024.106479","url":null,"abstract":"<div><div>The miniaturization, ultra-thin and multi-layer complex structure of microelectronic packaging complicates the coupling acoustic field of ultrasonic waves and internal defects in the packaging, making accurate defect detection very difficult. In this paper, the finite element models of flip chip (FC) packaging and ball grid array (BGA) packaging are established to investigate the coupling acoustic field characteristics of ultrasonic waves and defects. In addition, based on the ultrasonic pitch and catch technique, the coupling laws of ultrasonic waves of different frequencies and the defects of different types, positions and sizes are analyzed by simulation, and the relationship between the relative amplitudes of the bottom waves and the sizes of different defects is revealed. Two specimens of microelectronic packaging are designed and fabricated to carry out the experimental studies using an ultrasonic signal acquisition system. The simulation and experimental results show that the relationship between the defects with small changes in the same location and the relative amplitudes of the bottom waves is basically linear, while the relationship between the solder ball extension defects with large changes and the relative amplitudes of the bottom waves is basically logarithmic, which provides a theoretical guidance for accurate evaluation of the type, size and location of defects in the practical detection.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"154 ","pages":"Article 106479"},"PeriodicalIF":1.9,"publicationDate":"2024-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142661891","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Fully dynamic zoom ADC with energy-efficient residue feedforward and two-step summation 具有高能效残差前馈和两步求和功能的全动态变焦 ADC

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2024-11-10 DOI: 10.1016/j.mejo.2024.106474

Rongshan Wei, Zhijian Zheng, Yuxuan Lin, Nannan Xu, Gumeng Zhao, Qunchao Chen

引用次数: 0

A novel structure of less switching loss IGBT with super junction 一种具有超级结的低开关损耗IGBT新结构

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2024-11-10 DOI: 10.1016/j.mejo.2024.106477

Bokang Huang, Quanyuan Feng, Qiqi Liu, Zhiyong Qiu

{"title":"A novel structure of less switching loss IGBT with super junction","authors":"Bokang Huang, Quanyuan Feng, Qiqi Liu, Zhiyong Qiu","doi":"10.1016/j.mejo.2024.106477","DOIUrl":"10.1016/j.mejo.2024.106477","url":null,"abstract":"<div><div>In order to further reduce the switching loss (E<sub>SW</sub>), a novel floating CS layer and super-junction insulated gate bipolar transistor (FCS-SJBJ-IGBT) with internal barrier junction is proposed and simulated. On the premise of not affecting breakdown voltage (BV), the CS layer of FCS-SJBJ-IGBT is floating, so that the P-body is connected with the P-drift region, and a small part of P-pillar is formed between the CS layer and the left gate, which enables electrons to flow rapidly through this region in the on state, and provides an extraction hole path in the off state to reduce the loss. The simulation results show that，under the same forward conduction voltage (V<sub>ON</sub>) condition, the turn-on energy loss (E<sub>ON</sub>) of FCS-SJBJ-IGBT is significantly lower than that of the traditional super-junction IGBT (con-SJ-IGBT) and 34.5 % lower than that of the recently reported super-junction IGBT (SJBJ-IGBT) with blocking junction, P-pillar and N-pillar, while their turn-off energy loss (E<sub>OFF</sub>) is almost the same. The research results can provide important reference for reducing the E<sub>SW</sub> of IGBT.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"155 ","pages":"Article 106477"},"PeriodicalIF":1.9,"publicationDate":"2024-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142747892","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Deformation behavior study of SAC305 solder joints under shear and tensile loading by crystal plasticity finite element method 利用晶体塑性有限元法研究 SAC305 焊点在剪切和拉伸载荷下的变形行为

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2024-11-09 DOI: 10.1016/j.mejo.2024.106471

Qingyun Zhu, Zhiyong Huang, Hongjiang Qian, Jian Wang, Zeshuai Shen, Qikai Zhou

{"title":"Deformation behavior study of SAC305 solder joints under shear and tensile loading by crystal plasticity finite element method","authors":"Qingyun Zhu, Zhiyong Huang, Hongjiang Qian, Jian Wang, Zeshuai Shen, Qikai Zhou","doi":"10.1016/j.mejo.2024.106471","DOIUrl":"10.1016/j.mejo.2024.106471","url":null,"abstract":"<div><div>Micro solder joints experience various loads during operation, and the failure of a single micro solder joint can impact the overall reliability of the entire microsystem. This study utilized the Crystal Plasticity Finite Element Method (CPFEM) to create a polycrystalline model that accurately represents the shape of solder joints. By calibrating the crystal plasticity characteristics of SAC305 material solder joints using macroscopic stress-strain curves, the model successfully simulates the deformation mechanisms of micro-solder joints under both tensile and shear loads. This paper highlights that equivalent plastic strain serves as a key indicator of solder joint fracture behavior, revealing that strain components have varying effects on cracking: shear strain was found to cause crack initiation, while normal strain was found to promote crack extension. Moreover, Grain boundary features and orientation lead to uneven plastic strain by affecting the slip system and the Schmidt factor, especially small Schmidt factor grains at triple grain boundary intersections are more susceptible to crack initiation. Additionally, the study found that solder joints exhibit more pronounced mechanical responses under tensile loading compared to shear loading. These insights offer valuable guidance for the design and manufacturing of micro-solder joints.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"154 ","pages":"Article 106471"},"PeriodicalIF":1.9,"publicationDate":"2024-11-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142661888","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Analyzing negative differential resistance and capacitive effects in SiOx-based resistive switching devices for security applications 分析安全应用中基于氧化硅的电阻开关器件的负差分电阻和电容效应

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2024-11-08 DOI: 10.1016/j.mejo.2024.106472

Raju Vemuri, Saurabh Nagar

引用次数: 0