Microelectronics Journal最新文献_第10页

Garbage collection optimization with data separation for large data storage in deep learning applications 深度学习应用中基于数据分离的大数据存储垃圾收集优化

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-03-01 DOI: 10.1016/j.mejo.2025.106620

Qiang Zhou , Sirui Peng , Taoran Shen , Jie Yin , Tieli Sun , Xiaoyong Xue

{"title":"Garbage collection optimization with data separation for large data storage in deep learning applications","authors":"Qiang Zhou , Sirui Peng , Taoran Shen , Jie Yin , Tieli Sun , Xiaoyong Xue","doi":"10.1016/j.mejo.2025.106620","DOIUrl":"10.1016/j.mejo.2025.106620","url":null,"abstract":"<div><div>Deep learning has revolutionized numerous domains, creating an urgent need for storage systems capable of handling massive datasets and the intensive computational demands inherent to these workloads. Solid-State Drives (SSDs), known for their fast random access, low power consumption, and shock resistance, have emerged as a preferred storage medium in this context. However, traditional SSDs face critical challenges, including garbage collection (GC) overhead, write amplification, and inefficiencies in the software storage stack, stemming from the intrinsic characteristics of NAND flash and limitations in the existing storage ecosystem. These challenges underscore the necessity for specialized SSD controller chip designs tailored for deep learning workloads, addressing performance bottlenecks and optimizing data management to meet the unique demands of AI-driven applications. In this work, we implemented an open-channel SSD (OCSSD) based on a Xilinx FPGA, which can effectively alleviate the above-mentioned issues by exposing the structural characteristics of NAND flash to the host. To mitigate the performance cliff of I/O requests during GC operations, the link distance for data transmission is shortened by decoupling the host end and the device end. Moreover, the valid data migration and the GC operation frequency are both dramatically reduced by detecting and separating hot data and cold data to improve the overall performance of the SSD system. To verify the superiority of our design, we build a test platform through hardware and software co-design. The experimental results show that random read and random write bandwidth are increased by 159.7 % and 25.3 % compared to the mainstream SSDs, respectively. The latency of a single GC operation is reduced by an average of 12.64 % and the GC frequency is lowered by up to 64.8 %.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"158 ","pages":"Article 106620"},"PeriodicalIF":1.9,"publicationDate":"2025-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143549259","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A high speed adaptive reflection cancellation equalization circuit with Floating Tap FFE and Loop-Refactored DFE for ADC-DSP-based wireline receiver 一种用于adc - dsp有线接收机的高速自适应反射抵消均衡电路，具有浮动分接FFE和环重构DFE

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-02-27 DOI: 10.1016/j.mejo.2025.106612

Cewen Liu , Xingyun Qi , Fangxu Lv, Qiang Wang, Liquan Xiao, Xiaoyue Hu, Chaolong Xu, Zhouhao Yang, Meng Li, Mingche Lai

{"title":"A high speed adaptive reflection cancellation equalization circuit with Floating Tap FFE and Loop-Refactored DFE for ADC-DSP-based wireline receiver","authors":"Cewen Liu , Xingyun Qi , Fangxu Lv, Qiang Wang, Liquan Xiao, Xiaoyue Hu, Chaolong Xu, Zhouhao Yang, Meng Li, Mingche Lai","doi":"10.1016/j.mejo.2025.106612","DOIUrl":"10.1016/j.mejo.2025.106612","url":null,"abstract":"<div><div>High speed communication networks depend on higher data rates for bandwidth expansion, but face challenges in maintaining signal integrity when data rates exceed 100 Gb/s due to ISI and reflection, which hinder transmission speed advancements. This paper proposes the design of an adaptive reflection cancellation circuit for high-speed 4-level pulse amplitude (PAM4) serializer-deserializer (Serdes) receiver based on analog-to-digital converter (ADC) + digital signal processing (DSP) architecture. The proposed parallel Floating Tap Feedforward equalization(FT-FFE) effectively mitigates the impact of reflection without the need for a large number of equalizers, thereby reducing power consumption overhead. A Loop-Refactored decision feedback equalizer (LR-DFE) is implemented to mitigate timing constraints in ADC-DSP based high-speed wireline receivers, improving system performance and timing reliability. The tap coefficients are adaptively updated in combination with the Least Mean Square (LMS) algorithm. Simulation and FPGA platform validation results demonstrate that at a data rate of 56 Gb/s, the bit error rate(BER) is below 1e-12 through a channel with 39 dB insertion loss(IL).</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"159 ","pages":"Article 106612"},"PeriodicalIF":1.9,"publicationDate":"2025-02-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143562046","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Parasitic-induced multi-zero generation and port-fusion compact filter based on 3-D through-silicon via technology 基于三维硅通孔技术的寄生诱导多零产生和端口融合紧凑滤波器

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-02-27 DOI: 10.1016/j.mejo.2025.106618

Xiangkun Yin, Xiangyu Ma, Nairong Liu, Libo Qian, Tao Zhang, Qijun Lu, Zhangming Zhu

引用次数: 0

An accurate non-uniformity characterization of the temperature field in microsystems based on singular value decomposition 基于奇异值分解的微系统温度场非均匀性精确表征

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-02-27 DOI: 10.1016/j.mejo.2025.106619

Yanrong Pei , Wenchang Li , Jian Liu

{"title":"An accurate non-uniformity characterization of the temperature field in microsystems based on singular value decomposition","authors":"Yanrong Pei , Wenchang Li , Jian Liu","doi":"10.1016/j.mejo.2025.106619","DOIUrl":"10.1016/j.mejo.2025.106619","url":null,"abstract":"<div><div>The significant thermal challenges faced by the new generation of high-density integrated microsystems have become hot research topics in current thermal design, management, and reliability of microsystems. The non-uniformity of temperature field (NUTF) is at the core of these challenges. Accurately characterizing the NUTF of microsystems has been a difficult task. This paper proposes an accurate characterization method for microsystem NUTF based on singular value decomposition (SVD) to enhance the effectiveness and accuracy of traditional NUTF characterization methods. The paper also investigates the impact of the non-uniform distribution of the microsystem's heat flux densities (HFDs) on the temperature field and its complexity using the singular value properties. The results demonstrate that the proposed method can quantitatively characterize the steady-state NUTF and the spatial-temporal transient NUTF of the microsystems. The decay rate of the singular values can effectively identify the non-uniformity of the microsystem's HFDs. The number of singular values above a threshold can quantitatively assess the complexity of the microsystem temperature field.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"158 ","pages":"Article 106619"},"PeriodicalIF":1.9,"publicationDate":"2025-02-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143527114","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Switchable-core Wideband Class-F23 VCO with 200.8 dBc/Hz Peak FoMT in 130-nm SiGe 具有200.8 dBc/Hz峰值fmt的可交换核心宽带f23类压控振荡器

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-02-27 DOI: 10.1016/j.mejo.2025.106613

Lianzhen Zhang, Haipeng Fu, Lang Nie, Zhipeng Wang, Hao Shi, Kaixue Ma

引用次数: 0

Investigation of LTPS and a-Si TFT pixel circuit for micro-light-emitting-triode with current gain 具有电流增益的微型发光三极管LTPS和a-Si TFT像素电路的研究

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-02-26 DOI: 10.1016/j.mejo.2025.106615

Keren Wang , Jinyu Ye , Wenjuan Su , Yibin Lin , Xiongtu Zhou , Jianpu Lin , Tailiang Guo , Chaoxing Wu , Yongai Zhang

{"title":"Investigation of LTPS and a-Si TFT pixel circuit for micro-light-emitting-triode with current gain","authors":"Keren Wang , Jinyu Ye , Wenjuan Su , Yibin Lin , Xiongtu Zhou , Jianpu Lin , Tailiang Guo , Chaoxing Wu , Yongai Zhang","doi":"10.1016/j.mejo.2025.106615","DOIUrl":"10.1016/j.mejo.2025.106615","url":null,"abstract":"<div><div>The driving capability of Micro-LED displays based on thin film transistor (TFT) often falls short due to limited TFT current output performance. In this study, we propose a 6T2C pixel circuit for micro light-emitting-triode (Micro-LET), which integrates GaN-based LED and bipolar junction transistor (BJT) in a single chip vertically. The proposed pixel circuit, utilizing low-temperature polysilicon (LTPS) TFT, effectively compensates for threshold voltage shifts and mobility variations, thereby addressing the issue of pixel non-uniformity. Circuit simulation results demonstrate that the current error rates (CER) of the emission current are less than 4.71 % and 1.83 %, respectively, when subjected to ±0.5 V threshold voltage change and ±30 % mobility variation. Furthermore, the LTPS TFT can be extended to amorphous silicon (a-Si) TFT in the pixel circuit, showcasing its potential in enabling high-brightness Micro-LED displays driven by a-Si TFT technology with current amplification capabilities. These findings validate the feasibility of cost-effective and highly luminous Micro-LED displays while also alleviating concerns regarding overcapacity issues associated with a-Si TFT.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"158 ","pages":"Article 106615"},"PeriodicalIF":1.9,"publicationDate":"2025-02-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143529447","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A power-efficient spiking convolutional neural network accelerator based on temporal parallelism and streaming dataflow 一种基于时间并行和流数据流的高能效尖峰卷积神经网络加速器

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-02-25 DOI: 10.1016/j.mejo.2025.106616

Jian Zhang , Yong Wang , Yanlong Zhang , Bo Bi , Qiliang Chen , Yimao Cai

引用次数: 0

A 100-MHz bandwidth continuous-time sigma-delta ADC with 1 V supply in 28 nm CMOS 一个100mhz带宽连续时间σ - δ ADC与1 V电源在28纳米CMOS

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-02-22 DOI: 10.1016/j.mejo.2025.106597

Ben He , Xuan Guo , Hanbo Jia , Xinyu Liu

{"title":"A 100-MHz bandwidth continuous-time sigma-delta ADC with 1 V supply in 28 nm CMOS","authors":"Ben He , Xuan Guo , Hanbo Jia , Xinyu Liu","doi":"10.1016/j.mejo.2025.106597","DOIUrl":"10.1016/j.mejo.2025.106597","url":null,"abstract":"<div><div>A fourth-order continuous-time (CT) sigma-delta modulator (SDM) is presented for RF front-end system-on-chip (SoC) applications. Due to system constraints, only a 1 V power supply is available. To address this, we propose a three-stage operational amplifier with feedforward compensation that operates efficiently at low voltage. This amplifier achieves a DC gain of 78.5 dB and maintains a gain of 53.4 dB at an input signal frequency of 100 MHz, with a unity gain bandwidth of only 4.2 GHz. In contrast, traditional Miller-compensated operational amplifiers would require a unity gain bandwidth as high as 40.7 GHz to achieve similar performance. To mitigate DAC unit cell mismatch, we propose a dynamic element matching (DEM) circuit implementation utilizing a data-weighted averaging (DWA) algorithm. By removing the DEM block from the loop, the delay of this block does not affect the delay of the loop filter. This DEM technique enhances the signal-to-noise and distortion ratio (SNDR) by 13.9 dB and the spurious-free dynamic range (SFDR) by 20 dB. The prototype, implemented using a 28 nm CMOS process, achieves a dynamic range (DR) of 73.7 dB and a peak SNDR of 66.8 dB.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"158 ","pages":"Article 106597"},"PeriodicalIF":1.9,"publicationDate":"2025-02-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143474105","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Design of wideband high-efficiency power amplifier based on microstrip filter matching network with hybrid rings 基于混合环微带滤波器匹配网络的宽带高效功率放大器设计

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-02-22 DOI: 10.1016/j.mejo.2025.106614

Sen Xu , JianFeng Wu , Xiang Chen

引用次数: 0

WiseEDA: LLMs in RF Circuit Design WiseEDA：射频电路设计法学硕士

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-02-22 DOI: 10.1016/j.mejo.2025.106607

Hangjiang Jin, Junchao Wang, Junjie Sheng, Yifan Wu, Jiayu Chen, Yaqi Wang, Jun Liu

引用次数: 0