Microelectronics Journal最新文献_第10页

A comprehensive study on the electrical effects of avalanche region on GaN Schottky barrier IMPATT diodes through injection phases 雪崩区通过注入相对GaN肖特基势垒IMPATT二极管电效应的综合研究

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-07-22 DOI: 10.1016/j.mejo.2025.106818

Xuan Huang, Lin-An Yang, Jian-Hua Zhou, Xin-Yi Wang, Dong-Liang Chen, Xiao-Hua Ma, Yue Hao

{"title":"A comprehensive study on the electrical effects of avalanche region on GaN Schottky barrier IMPATT diodes through injection phases","authors":"Xuan Huang, Lin-An Yang, Jian-Hua Zhou, Xin-Yi Wang, Dong-Liang Chen, Xiao-Hua Ma, Yue Hao","doi":"10.1016/j.mejo.2025.106818","DOIUrl":"10.1016/j.mejo.2025.106818","url":null,"abstract":"<div><div>The article investigates the effect of the avalanche region on GaN Schottky barrier IMPATT diodes using Sentaurus TCAD. The results show that as the avalanche region shrinks, thermal field emission deteriorates, resulting in a rapid decline of the avalanche multiplication factor and injection phase. It degrades the initiating oscillation and output. Narrowing the avalanche region from 125 nm to 50 nm, the injection phase decreases from 154°–169° to 119°–136°. At the designed frequency of 120 GHz, the start-up efficiency and speed are reduced by 18 % and 26 %, respectively. Additionally, the oscillating output capability and stability decrease by 50 % and 53 %. Meanwhile, the radio frequency conversion power drops by 40 %, whereas its efficiency improves by 50 %, lowering the junction temperature difference from 703 °C to 290 °C. It presents a method to adjust trade-offs between pulse width and instantaneous output power by the width of the avalanche region for the pulsed wave mode that is preferred in the device.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"165 ","pages":"Article 106818"},"PeriodicalIF":1.9,"publicationDate":"2025-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144738288","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Effect of polarized AlGaN/GaN structure-based field plate on the electric properties of a 4H-SiC Schottky barrier diode 极化AlGaN/GaN结构场极板对4H-SiC肖特基势垒二极管电性能的影响

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-07-22 DOI: 10.1016/j.mejo.2025.106814

Feng He , Wenting Zhang , Xiamin Hao , Xinyu Li , Ruifen Nie , Rui Jin

{"title":"Effect of polarized AlGaN/GaN structure-based field plate on the electric properties of a 4H-SiC Schottky barrier diode","authors":"Feng He , Wenting Zhang , Xiamin Hao , Xinyu Li , Ruifen Nie , Rui Jin","doi":"10.1016/j.mejo.2025.106814","DOIUrl":"10.1016/j.mejo.2025.106814","url":null,"abstract":"<div><div>By employing advanced physical models with the help of TCAD, we studied the impact of polarized AlGaN/GaN field plates on 4H-SiC Schottky barrier diodes (SBDs). In a traditional 4H-SiC SBD with a p-SiC field ring, the strongest electric field occurs at both the junction interface and the edge of the field ring, leading to premature breakdown and increased leakage current under reverse bias conditions. The proposed polarized AlGaN/GaN structure-based field plate evens out the electric field distribution between the AlGaN/GaN layer and the field plate dielectric layer, thereby enhancing the breakdown voltage (BV) of the device. Additionally, an optimum design strategy is detailed in the paper, using the length of the field plate (<em>L</em><sub>FP</sub>) and thickness of the field plate dielectric layer (<em>T</em><sub>FP</sub>) as control variables. Furthermore, this study also examines how surface defects and bulk traps would affect the device characteristics and discusses the physical mechanisms. It is found that donor-type traps would strongly add to device performance degradation.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"164 ","pages":"Article 106814"},"PeriodicalIF":1.9,"publicationDate":"2025-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144711116","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Design of irises-stabilized substrate integrated waveguide bandpass filters on silicon-based wafer-level packaging process 基于硅基晶圆级封装工艺的虹膜稳定基板集成波导带通滤波器设计

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-07-22 DOI: 10.1016/j.mejo.2025.106808

Jie Liu , Yi Le , Jun Liu , Guodong Su , Zengda Wang , Yuehang Xu

{"title":"Design of irises-stabilized substrate integrated waveguide bandpass filters on silicon-based wafer-level packaging process","authors":"Jie Liu , Yi Le , Jun Liu , Guodong Su , Zengda Wang , Yuehang Xu","doi":"10.1016/j.mejo.2025.106808","DOIUrl":"10.1016/j.mejo.2025.106808","url":null,"abstract":"<div><div>This article presents an irises-stabilized substrate integrated waveguide (IS-SIW) structure for bandpass filter (BPF) designs in the wafer-level packaging (WLP) process. The IS-SIW employs irises to reinforce the SIW cavity. They can effectively protect physical structure of SIW from wafer warpage, which is caused by thermal expansion. By introducing advanced coplanar waveguide (CPW) wave mode converters and H-slotted resonators, the IS-SIW can generate a passband with two transmission poles (TPs) and two transmission zeros (TZs). Additionally, the feedlines are designed with stepped-impedance resonators (SIRs) and defected ground structures (DGSs) ensure interconnection and impedance matching between the IS-SIW and the ground-signal-ground (GSG) ports. Finally, three IS-SIW BPF prototypes were designed and fabricated. Measurement results align well with the theoretical analysis and simulation results. These BPFs achieve miniaturization and at least 30 dB out-of-band suppression. Therefore, the proposed IS-SIW BPFs show great potential for applications in millimeter-wave short-range radar and communication systems.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"165 ","pages":"Article 106808"},"PeriodicalIF":1.9,"publicationDate":"2025-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144749932","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A linearized PVT-robust FVF input buffer with triode transconductance feedback achieving SFDR > 90 dB at 500-MHz input 具有三极管跨导反馈的线性化pvt鲁棒FVF输入缓冲器，在500-MHz输入时实现SFDR > 90 dB

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-07-22 DOI: 10.1016/j.mejo.2025.106802

Junye Su, Shubin Liu, Haolin Han

{"title":"A linearized PVT-robust FVF input buffer with triode transconductance feedback achieving SFDR > 90 dB at 500-MHz input","authors":"Junye Su, Shubin Liu, Haolin Han","doi":"10.1016/j.mejo.2025.106802","DOIUrl":"10.1016/j.mejo.2025.106802","url":null,"abstract":"<div><div>This paper presents a high-linearity input buffer leveraging triode-transconductance feedback (TTF) flipped voltage followers for RF sampling data converters. The proposed source follower incorporates a triode-biased transistor to enhance linearity by cancelling the third harmonic distortion (HD3). Under a 1-GS/s sampling rate, the buffer achieves SFDR of 90.4 dB and SNDR of 74.6 dB at Nyquist frequency. A dedicated constant-<span><math><msub><mrow><mi>g</mi></mrow><mrow><mi>m</mi></mrow></msub></math></span> current source and channel split bias circuits are also introduced in this work to accommodate process, voltage, and temperature (PVT) conditions. Simulated under 5corners, −40 to125  <span><math><mo>±</mo></math></span> 2.5<span><math><mtext>%</mtext></math></span>, the prototype buffer designed in 28-nm CMOS maintains SFDR <span><math><mo>≥</mo></math></span> 80 dB, improved by approximately 30 dB. With a power consumption of 23.54mW, the proposed buffer attains a figure of merit (FoM) of 173.0 dB, demonstrating an excellent trade-off among linearity, bandwidth and power consumption.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"164 ","pages":"Article 106802"},"PeriodicalIF":1.9,"publicationDate":"2025-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144686336","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Investigation of trench SiC MOSFETs with double deep trench under avalanche stress 雪崩应力下双深沟槽SiC mosfet的研究

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-07-22 DOI: 10.1016/j.mejo.2025.106809

Wenhan Yang, Xiaoyan Tang, Yibo Zhang, Jingyu Li, Haobo Kang, Weishuo Guo, Hao Yuan, Qingwen Song, Yuming Zhang

{"title":"Investigation of trench SiC MOSFETs with double deep trench under avalanche stress","authors":"Wenhan Yang, Xiaoyan Tang, Yibo Zhang, Jingyu Li, Haobo Kang, Weishuo Guo, Hao Yuan, Qingwen Song, Yuming Zhang","doi":"10.1016/j.mejo.2025.106809","DOIUrl":"10.1016/j.mejo.2025.106809","url":null,"abstract":"<div><div>In this article, the dynamic avalanche reliability of 1200-V silicon carbide (SiC) power metal-oxide semiconductor field-effect transistors (MOSFETs) with double deep trench(DDT-MOS) is studied. During unclamped inductive switching (UIS) measurement, a significant difference in avalanche capability was observed between the DDT-MOS. The damage analysis suggests that DDT-MOS show two failure mechanisms: burnout and gate failure during the UIS test. Through TCAD simulations and damage analysis, it can be determined that a serious temperature concentration occurred during the avalanche. Due to the characteristic that the avalanche current increases exponentially with the avalanche voltage once the drain–source voltage exceeds the avalanche threshold, the morphological differences in the P-well region caused by etching discrepancies will lead to a serious temperature concentration, which will deteriorate the avalanche capability and lead to the abnormal failure of the DDT-MOS. In addition, the uncontrollable value and distribution of etching discrepancies in deep trench is also a plausible explanation to explain the significant difference in avalanche capability between the DDT-MOS.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"164 ","pages":"Article 106809"},"PeriodicalIF":1.9,"publicationDate":"2025-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144702544","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A bit-level loosely coupled computing-in-memory macro with early termination 具有提前终止的位级松散耦合内存计算宏

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-07-21 DOI: 10.1016/j.mejo.2025.106796

Junchuan Gu , Yang Chen , Wenwei Wang , Akash Kumar , Salim Ullah , Kejie Huang , Haibin Shen

{"title":"A bit-level loosely coupled computing-in-memory macro with early termination","authors":"Junchuan Gu , Yang Chen , Wenwei Wang , Akash Kumar , Salim Ullah , Kejie Huang , Haibin Shen","doi":"10.1016/j.mejo.2025.106796","DOIUrl":"10.1016/j.mejo.2025.106796","url":null,"abstract":"<div><div>Computing-in-memory (CIM) has emerged as a promising solution for artificial intelligence (AI) edge devices. However, conventional bit-slicing CIM designs necessitate the availability of all input bits prior to the computation process. This tight coupling between input and output bits results in a substantial need for temporary storage and leads to significant output delays. In this article, we propose a bit-level loosely coupled (BLC) computation scheme for CIM macros, which reduces the bit widths of temporary data to 1 bit, thereby saving register demand. Accuracy and computational efficiency is further enhanced by zero detection scheme and early termination scheme. A CIM macro is designed to implement BLC multiply and accumulate (MAC) computation. Compared with the 8-bit quantized model, our proposed scheme incurs only 0.29% and 0.52% accuracy loss on AlexNet and ResNet20 (CIFAR-10 dataset), respectively. In a 40-nm process, the power consumption of our CIM macro is 3.54 mW (256 x 256 at 8-bit) and the computing-power ratio is 37.01 TOPS/W.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"164 ","pages":"Article 106796"},"PeriodicalIF":1.9,"publicationDate":"2025-07-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144724499","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Interrupted field-stop layer reverse conducting MOS controlled thyristor and mitigation of the voltage snapback 中断场停止层反导MOS控制晶闸管及电压回跳的缓解

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-07-19 DOI: 10.1016/j.mejo.2025.106812

Gaoming Li, Tongfei Wu, Weidong Chen, Xiaolong Zhao, Yongning He

引用次数: 0

A 12.5–50 GHz frequency synthesizer for Software-Defined Radios in 40-nm CMOS 用于40纳米CMOS软件定义无线电的12.5-50 GHz频率合成器

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-07-18 DOI: 10.1016/j.mejo.2025.106806

Yanhui Wu , Shize Duan , Zhenrong Li , Jianbo Qiu , Jiayi Li , Xi Ji , Jinsong Tu , Jie Li , Cong Li , Gangzi Chen , Qiong Li

{"title":"A 12.5–50 GHz frequency synthesizer for Software-Defined Radios in 40-nm CMOS","authors":"Yanhui Wu , Shize Duan , Zhenrong Li , Jianbo Qiu , Jiayi Li , Xi Ji , Jinsong Tu , Jie Li , Cong Li , Gangzi Chen , Qiong Li","doi":"10.1016/j.mejo.2025.106806","DOIUrl":"10.1016/j.mejo.2025.106806","url":null,"abstract":"<div><div>In this paper, we propose a dual-channel SDR frequency synthesizer based on a fractional CP-PLL architecture, designed to achieve continuous frequency coverage from 12.5 to 50 GHz. An <em>LC</em>-VCO array is used to generate fundamental frequency signals ranging from 12.5 to 25 GHz, and a frequency doubler extends the frequency range to 25 to 50 GHz. An inductive biasing technique is introduced to eliminate phase noise deterioration due to resistive thermal noise while supporting implicit common-mode resonance to further optimize phase noise performance. The chip is fabricated using 40-nm CMOS technology. Measurement results indicate a phase noise of −109.7 dBc/Hz at a 1 MHz offset from the 12.5 GHz carrier, while the integrated jitter (from 12 kHz to 20 MHz) is less than 100 fs over the entire frequency range. The chip consumes 80.5 mW of power with a 1.1 V supply and occupies an area of 3.7 mm × 3 mm. In addition, the chip integrates an RF power amplifier to amplify fundamental and octave signals, improving driving capability.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"165 ","pages":"Article 106806"},"PeriodicalIF":1.9,"publicationDate":"2025-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144772613","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Design of quasi-reflectionless filter based on hybrid absorption architecture 基于混合吸收结构的准无反射滤波器设计

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-07-16 DOI: 10.1016/j.mejo.2025.106810

Zichen Guo , Zhiyu Wang , Junjie Xie , Xinyu Wang , Siyuan Ma , Annan Xu , Minyi Yang , Xi Guo , Jiongjiong Mo , Faxin Yu

{"title":"Design of quasi-reflectionless filter based on hybrid absorption architecture","authors":"Zichen Guo , Zhiyu Wang , Junjie Xie , Xinyu Wang , Siyuan Ma , Annan Xu , Minyi Yang , Xi Guo , Jiongjiong Mo , Faxin Yu","doi":"10.1016/j.mejo.2025.106810","DOIUrl":"10.1016/j.mejo.2025.106810","url":null,"abstract":"<div><div>In this paper, a quasi-reflectionless (QRL) filter based on hybrid absorption architecture is proposed and analyzed. The filter adopts a modular design philosophy, comprising a quasi-complementary diplexer (QCD) network formed by conventional filters with frequency complementarity and a reflection-absorption compensation (RAC) network integrating phase shifters and lossy power combiners<u>.</u> The incorporation of the RAC network enhances the reflectionless frequency range of QCD network. This enables conventional complementary bandpass and bandstop filters to be rapidly transformed into QRL filters with ultra-wideband absorption capabilities, without strict complementary responses or designated feeding structure designs<u>.</u> To demonstrate this approach, a 24–28 GHz quasi-reflectionless bandpass filter (QRL-BPF) consisting of multi-mode microstrip resonators is simulated and fabricated using GaAs integrated passive device (IPD) process. Measured results show that the proposed QRL-BPF achieves a reflectionless relative bandwidth (RFBW) of 150 % with reflection absorption level approaching −10dB.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"164 ","pages":"Article 106810"},"PeriodicalIF":1.9,"publicationDate":"2025-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144702543","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A pre-congestion-aware deterministic-adaptive hybrid routing (PcaDAHR) algorithm for network-on-chip 片上网络的预拥塞感知确定性自适应混合路由（PcaDAHR）算法

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-07-16 DOI: 10.1016/j.mejo.2025.106811

Ning Ji, Yintang Yang

引用次数: 0