Microelectronics Journal最新文献_第10页

Workload variation compensation optimization of ring oscillator temperature measurement method and its application in field-programmable gate array

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-02-01 DOI: 10.1016/j.mejo.2024.106545

Yaning Wang , Shiwei Feng , Xianliang Lv , Kun Bai , Shijie Pan , Zixuan Feng , Xiaozhuang Lu , Yinqi Zhou , Boyang Zhang

{"title":"Workload variation compensation optimization of ring oscillator temperature measurement method and its application in field-programmable gate array","authors":"Yaning Wang , Shiwei Feng , Xianliang Lv , Kun Bai , Shijie Pan , Zixuan Feng , Xiaozhuang Lu , Yinqi Zhou , Boyang Zhang","doi":"10.1016/j.mejo.2024.106545","DOIUrl":"10.1016/j.mejo.2024.106545","url":null,"abstract":"<div><div>—With the ongoing improvements in semiconductor manufacturing technology, the supply voltage required for field-programmable gate array (FPGA) chips is gradually decreasing. As a result, the oscillation frequencies of ring oscillators are affected more obviously by voltage fluctuations, and the sharp changes in the oscillation frequency that can be caused by small changes in the FPGA core voltage have become a problem that cannot be ignored for digital temperature sensors. In this paper, we use a 28 nm FPGA chip to realize a digital temperature sensor network, and at the same time deploy 32 temperature sensors for comprehensive temperature monitoring of the FPGA chip; the monitoring process mainly characterizes the non-ideal influence of the workload changes on the ring oscillator's response. The temperature measurement method, which is based on the oscillation frequency, is modified to compensate for the influence of core voltage variations due to changes in the working load on the output frequency of the ring oscillator. The test results are compared with those from an infrared thermal imager. These results prove that the proposed compensation method can improve the temperature measurement accuracy and ensure that it reflects the actual chip temperature accurately under various working load conditions. This condition is essential for electronic device health monitoring, thermal management, and fault diagnosis scenarios to prevent problems being caused by overheating and to ensure reliable system operation.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"156 ","pages":"Article 106545"},"PeriodicalIF":1.9,"publicationDate":"2025-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143162393","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

High-selectivity fully tunable wideband bandpass filter with adaptive transmission zeros

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-02-01 DOI: 10.1016/j.mejo.2024.106504

Xuan Chen , Jing Guo , Hong-Lang Li , Yang Xiong , Hong-Yuan Zhang , Yu-Qi Li , Cui-Ping Li , Dan Li , Li-Rong Qian , Lin Miao , Li-Tian Wang

引用次数: 0

Design and analysis of digital-like RF transmitter based on novel harmonic-rejected frequency multiplication architecture

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-02-01 DOI: 10.1016/j.mejo.2025.106557

Jun Zhao , Yetong Wang , Guo Wei , Hao Zhang , Keping Wang

{"title":"Design and analysis of digital-like RF transmitter based on novel harmonic-rejected frequency multiplication architecture","authors":"Jun Zhao , Yetong Wang , Guo Wei , Hao Zhang , Keping Wang","doi":"10.1016/j.mejo.2025.106557","DOIUrl":"10.1016/j.mejo.2025.106557","url":null,"abstract":"<div><div>The increasing use of IoT technology highlights the importance of wireless sensing, where low power consumption and efficient transmission are critical. This paper presents a high-efficiency 400–460 MHz inductorless digital transmitter (TX) tailored for wireless sensing applications. The proposed design incorporates a novel harmonic-rejected frequency multiplication (HRFM) architecture to suppress 3rd- and 5th-order harmonics, ensuring efficient transmission with minimal power consumption. The architecture employs a delay-locked loop (DLL) and a resistance-divider-based edge combiner to both shape the output waveform for harmonic suppression and achieve 9x frequency multiplication. To further optimize DC power consumption, the HRFM generates multipath signals at lower frequencies through the DLL. A feedback-modified, highly matched charge pump (CP) with dynamic current compensation reduces CP charge/discharge current mismatch. Additionally, a dual voltage control approach enhances the operating range of the voltage-controlled delay line (VCDL). Implemented in a 65 nm CMOS process, the transmitter occupies a core area of 0.05 mm<sup>2</sup>. Simulations show the DLL achieves a spur of approximately 61 dB, while post-layout simulations indicate harmonic distortions greater than −40 dBc for the 3rd-order and −52 dBc for the 5th-order harmonics, all without using inductors. The transmitter delivers −16 dBm output power to a 50 Ω antenna load, with a global DC power consumption of 1.3 mW. Overall, the proposed transmitter demonstrates highly efficient, low-power transmission for wireless sensing applications.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"156 ","pages":"Article 106557"},"PeriodicalIF":1.9,"publicationDate":"2025-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143163326","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A novel Ω-SOI Gate-All-Around FET with doping free load-Si and two-step wet etching achieving superior leakage suppression and short-channel effects immunity

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-02-01 DOI: 10.1016/j.mejo.2024.106534

Longyu Sun , Haoyan Liu , Xin Wang , Xiaofeng Jia , Jiayi Zhang , Yongliang Li

{"title":"A novel Ω-SOI Gate-All-Around FET with doping free load-Si and two-step wet etching achieving superior leakage suppression and short-channel effects immunity","authors":"Longyu Sun , Haoyan Liu , Xin Wang , Xiaofeng Jia , Jiayi Zhang , Yongliang Li","doi":"10.1016/j.mejo.2024.106534","DOIUrl":"10.1016/j.mejo.2024.106534","url":null,"abstract":"<div><div>In this article, we proposed a novel 4-layer silicon-on-insulator (SOI) nanosheet (NS) Gate-All-Around (GAA) field-effect transistor (FET) with an Ω-structure (Ω-SOI). Through high-quality SiGe/Si multilayers epitaxy on the ground-plane (GP) doping free load-Si, and a two-step wet etching Ω-structure formation process, this novel Ω-SOI GAAFET was successfully fabricated, achieving threshold swing (SS), off-state current (I<sub>off</sub>), current ratio (I<sub>on</sub>/I<sub>off</sub>), and drain-induced barrier lowering (DIBL) values of 65 mV/dec, 2.8 × 10<sup>−4</sup> μA/μm, 3 × 10<sup>6</sup>, and 7 mV/V, respectively. Moreover, 3D technology computer-aided design (TCAD) simulation was applied in advanced node, confirming that this novel Ω-SOI GAAFET can provide enhanced gate control capability than conventional SOI (C-SOI) GAAFET, leading to superior leakage suppression, and short-channel effects (SCE) immunity. This novel Ω-SOI GAAFET is compatible with the process flow of mainstream GAAFET, providing a promising candidate for extending CMOS technology.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"156 ","pages":"Article 106534"},"PeriodicalIF":1.9,"publicationDate":"2025-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143163086","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Optimized design of UTB SOI MOSFET and connections for 2.45 G weak energy density harvesting

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-02-01 DOI: 10.1016/j.mejo.2024.106531

YuChen Zhang, JianJun Song, JiaZhi Ren, AiLan Tang

引用次数: 0

Lumped-parameter modeling of MEMS hydrophone for different diaphragm geometries

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-02-01 DOI: 10.1016/j.mejo.2024.106511

Xin Wang, Hua Yang, Fei Sun, Ying Zhang, Beibei Mao

{"title":"Lumped-parameter modeling of MEMS hydrophone for different diaphragm geometries","authors":"Xin Wang, Hua Yang, Fei Sun, Ying Zhang, Beibei Mao","doi":"10.1016/j.mejo.2024.106511","DOIUrl":"10.1016/j.mejo.2024.106511","url":null,"abstract":"<div><div>The geometry of hydrophone elements significantly influences array structure fill-factor and overall hydrophone performance. This study introduces an enhanced theoretical model for Microelectromechanical Systems (MEMS) piezoelectric hydrophone elements, comprehensively characterizing their performance across various geometries. Utilizing the Ritz method, our model provides a generalized solution for approximating mode shape functions of hydrophone elements with diverse shapes and boundary conditions. We derive electromechanical equivalent circuits through modal orthogonality, providing a new mathematical insight into the derivation process, while maintaining equivalence to traditional energy-based methods. The static receiving sensitivity expression is then obtained by analyzing the equivalent circuit’s system function. Our proposed model demonstrates satisfactory accuracy with significantly reduced computational demands compared to finite element method (FEM) based numerical models. This comprehensive theoretical framework offers valuable insights for optimizing element dimensions in MEMS hydrophones and piezoelectric micromachined ultrasonic transducers (PMUTs), potentially advancing the design and enhancing the performance of piezoelectric hydrophones.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"156 ","pages":"Article 106511"},"PeriodicalIF":1.9,"publicationDate":"2025-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143162244","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Design and optimization of discrete-time delta-sigma modulators

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-02-01 DOI: 10.1016/j.mejo.2024.106529

Ziqiang Peng, Cong Wei, Lijie Huang, Jinze Lai, Xiaoqiang Lu, Rongshan Wei

引用次数: 0

A 2-MHz BW 93.2-dB SFDR 2nd-Order Hybrid EF-CIFF Noise Shaping SAR ADC

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-02-01 DOI: 10.1016/j.mejo.2024.106549

MingJie Li , MingChao Jian , HuanLin Xie , JiaJun Yang , JiaWei Tian , Bo Sun , ChunBing Guo

引用次数: 0

An FPGA-based binary neural network accelerator with enhanced hardware efficiency and data reuse

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-02-01 DOI: 10.1016/j.mejo.2025.106556

Dezheng Zhang , Rui Cen , Han Pu , Rui Wan , Dong Wang

{"title":"An FPGA-based binary neural network accelerator with enhanced hardware efficiency and data reuse","authors":"Dezheng Zhang , Rui Cen , Han Pu , Rui Wan , Dong Wang","doi":"10.1016/j.mejo.2025.106556","DOIUrl":"10.1016/j.mejo.2025.106556","url":null,"abstract":"<div><div>Binary neural network (BNN) algorithms have gained significant attention due to their low computational complexity and improved accuracy. Field-programmable gate array (FPGA)-based accelerators for BNNs typically transform binary operations into XNOR and popcount operations, efficiently utilizing logic resources. However, fixed-point operations in the first and final layers result in high hardware costs. Moreover, frequent off-chip memory access, particularly for shortcut operations, can severely limit throughput.</div><div>This paper introduces a hardware-efficient FPGA-based BNN accelerator with minimized off-chip memory access. The first layer’s inputs are binarized using an enhanced thermometer encoding scheme, enabling all convolution layers to be executed on a unified binary computing unit. A multi-mode computing unit is designed to perform both ReAct parametric rectified linear unit (RPReLU) and linear operations using shared hardware multipliers, which maximizes hardware reuse. To address bandwidth limitations, we implement a dynamic data buffering architecture, featuring high-bandwidth and high-volume buffers for caching intra-layer and cross-layer data, respectively. The accelerator supports two data buffering schemes, and the one minimizing the off-chip memory access is selected for each convolution layer. The accelerator is evaluated on an Alinx AXU3EGB development board and a custom development board with a Xilinx XC7V690T device, respectively. Experiments on ImageNet demonstrate 69.34% accuracy, with frames per second (FPS) of 129.1 and 405.6 on the ZU3EG and XC7V690T devices, respectively. Compared to the state-of-the-art design, our accelerator achieves 2.7<span><math><mo>×</mo></math></span> FPS on the same FPGA device.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"156 ","pages":"Article 106556"},"PeriodicalIF":1.9,"publicationDate":"2025-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143163325","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A time-interleaved 2b/Cycle SAR ADC with sign-inversion method for timing-skew calibration

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-02-01 DOI: 10.1016/j.mejo.2024.106522

JiaWei Tian , MingChao Jian , HuanLin Xie , MingJie Li , JiaJun Yang , ChunBing Guo

引用次数: 0