A 12.5–50 GHz frequency synthesizer for Software-Defined Radios in 40-nm CMOS

In this paper, we propose a dual-channel SDR frequency synthesizer based on a fractional CP-PLL architecture, designed to achieve continuous frequency coverage from 12.5 to 50 GHz. An LC-VCO array is used to generate fundamental frequency signals ranging from 12.5 to 25 GHz, and a frequency doubler extends the frequency range to 25 to 50 GHz. An inductive biasing technique is introduced to eliminate phase noise deterioration due to resistive thermal noise while supporting implicit common-mode resonance to further optimize phase noise performance. The chip is fabricated using 40-nm CMOS technology. Measurement results indicate a phase noise of −109.7 dBc/Hz at a 1 MHz offset from the 12.5 GHz carrier, while the integrated jitter (from 12 kHz to 20 MHz) is less than 100 fs over the entire frequency range. The chip consumes 80.5 mW of power with a 1.1 V supply and occupies an area of 3.7 mm × 3 mm. In addition, the chip integrates an RF power amplifier to amplify fundamental and octave signals, improving driving capability.