雪崩应力下双深沟槽SiC mosfet的研究

IF 1.9 3区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronics Journal Pub Date : 2025-07-22 DOI:10.1016/j.mejo.2025.106809

Wenhan Yang, Xiaoyan Tang, Yibo Zhang, Jingyu Li, Haobo Kang, Weishuo Guo, Hao Yuan, Qingwen Song, Yuming Zhang

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引用次数: 0

摘要

本文研究了1200 v双深沟槽功率金属氧化物半导体场效应晶体管（mosfet）的动态雪崩可靠性。在非箝位电感开关（UIS）测量中，观察到DDT-MOS之间的雪崩能力有显着差异。损伤分析表明，在UIS试验中，DDT-MOS表现出两种破坏机制：燃尽和栅破坏。通过TCAD仿真和损伤分析，可以确定雪崩过程中发生了严重的温度集中。由于漏源电压一旦超过雪崩阈值，雪崩电流随雪崩电压呈指数增长的特点，由于蚀刻差异引起的p阱区形态差异将导致严重的温度集中，从而使雪崩能力恶化，导致DDT-MOS的异常失效。此外，刻蚀差异在深沟槽内的不可控值和分布也可能解释了两种DDT-MOS在雪崩能力上的显著差异。

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Investigation of trench SiC MOSFETs with double deep trench under avalanche stress

In this article, the dynamic avalanche reliability of 1200-V silicon carbide (SiC) power metal-oxide semiconductor field-effect transistors (MOSFETs) with double deep trench(DDT-MOS) is studied. During unclamped inductive switching (UIS) measurement, a significant difference in avalanche capability was observed between the DDT-MOS. The damage analysis suggests that DDT-MOS show two failure mechanisms: burnout and gate failure during the UIS test. Through TCAD simulations and damage analysis, it can be determined that a serious temperature concentration occurred during the avalanche. Due to the characteristic that the avalanche current increases exponentially with the avalanche voltage once the drain–source voltage exceeds the avalanche threshold, the morphological differences in the P-well region caused by etching discrepancies will lead to a serious temperature concentration, which will deteriorate the avalanche capability and lead to the abnormal failure of the DDT-MOS. In addition, the uncontrollable value and distribution of etching discrepancies in deep trench is also a plausible explanation to explain the significant difference in avalanche capability between the DDT-MOS.

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来源期刊

Microelectronics Journal 工程技术-工程：电子与电气

CiteScore

4.00

自引率

27.30%

发文量

222

审稿时长

43 days

期刊介绍： Published since 1969, the Microelectronics Journal is an international forum for the dissemination of research and applications of microelectronic systems, circuits, and emerging technologies. Papers published in the Microelectronics Journal have undergone peer review to ensure originality, relevance, and timeliness. The journal thus provides a worldwide, regular, and comprehensive update on microelectronic circuits and systems. The Microelectronics Journal invites papers describing significant research and applications in all of the areas listed below. Comprehensive review/survey papers covering recent developments will also be considered. The Microelectronics Journal covers circuits and systems. This topic includes but is not limited to: Analog, digital, mixed, and RF circuits and related design methodologies; Logic, architectural, and system level synthesis; Testing, design for testability, built-in self-test; Area, power, and thermal analysis and design; Mixed-domain simulation and design; Embedded systems; Non-von Neumann computing and related technologies and circuits; Design and test of high complexity systems integration; SoC, NoC, SIP, and NIP design and test; 3-D integration design and analysis; Emerging device technologies and circuits, such as FinFETs, SETs, spintronics, SFQ, MTJ, etc. Application aspects such as signal and image processing including circuits for cryptography, sensors, and actuators including sensor networks, reliability and quality issues, and economic models are also welcome.