A linearized PVT-robust FVF input buffer with triode transconductance feedback achieving SFDR > 90 dB at 500-MHz input

Abstract

This paper presents a high-linearity input buffer leveraging triode-transconductance feedback (TTF) flipped voltage followers for RF sampling data converters. The proposed source follower incorporates a triode-biased transistor to enhance linearity by cancelling the third harmonic distortion (HD3). Under a 1-GS/s sampling rate, the buffer achieves SFDR of 90.4 dB and SNDR of 74.6 dB at Nyquist frequency. A dedicated constant-$g_m$ current source and channel split bias circuits are also introduced in this work to accommodate process, voltage, and temperature (PVT) conditions. Simulated under 5 corners, −40 to 125 $°C$ and 1.8 V $\pm$  2.5$\text{\%}$, the prototype buffer designed in 28-nm CMOS maintains SFDR $\ge$ 80 dB, improved by approximately 30 dB. With a power consumption of 23.54 mW, the proposed buffer attains a figure of merit (FoM) of 173.0 dB, demonstrating an excellent trade-off among linearity, bandwidth and power consumption.