Microelectronics Journal最新文献_第9页

UIC: A unified and scalable chip integrating neuromorphic computation and general purpose processor UIC：集成神经形态计算和通用处理器的统一可扩展芯片

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2024-11-26 DOI: 10.1016/j.mejo.2024.106449

Qiang Zhang , Mingyue Cui , Weichong Chen , Yue Liu , Zhiyi Yu

{"title":"UIC: A unified and scalable chip integrating neuromorphic computation and general purpose processor","authors":"Qiang Zhang , Mingyue Cui , Weichong Chen , Yue Liu , Zhiyi Yu","doi":"10.1016/j.mejo.2024.106449","DOIUrl":"10.1016/j.mejo.2024.106449","url":null,"abstract":"<div><div>Most SNN hardware implementations adopt a heterogeneous architecture consisting of CPUs and accelerators to achieve efficiency in neuromorphic computing. However, this architectural method encounters challenges like load imbalance, communication delays, and substantial demand for hardware resources. To address this issue, we build a unified model description framework and processing architecture, the unified integration core (UIC), which integrates neuromorphic computing (NC) and general-purpose computing (GPC), and conduct software and hardware co-design. By implementing a set of integration and transformation operations, UIC can support critical general purpose processor (GPP) and SNN operations with the same processing elements achieving significant area reduction and latency reduction over those of a naive implementation. A compatible communication infrastructure is proposed to enable homogeneous and heterogeneous scalability on a decentralized intra- and inter-core network. Several optimization methods are incorporated, including resource and data sharing, near-memory processing, and intra-/inter-core pipeline. Compared to the previous state-of-the-art works, UIC achieves high energy efficiency at 2.55 mJ/inference with a low latency of 18.4 ms. In terms of hardware resource consumption, LUTs, and FF hardware resources are reduced by 56% and 60%.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"155 ","pages":"Article 106449"},"PeriodicalIF":1.9,"publicationDate":"2024-11-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142747891","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Analytical multistage thermal resistance model for NSFET self-heating effects 针对 NSFET 自热效应的多级热阻分析模型

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2024-11-23 DOI: 10.1016/j.mejo.2024.106499

Pan Zhao, Taoyu Zhou, Naiqi Liu, Yandong He, Gang Du

{"title":"Analytical multistage thermal resistance model for NSFET self-heating effects","authors":"Pan Zhao, Taoyu Zhou, Naiqi Liu, Yandong He, Gang Du","doi":"10.1016/j.mejo.2024.106499","DOIUrl":"10.1016/j.mejo.2024.106499","url":null,"abstract":"<div><div>As semiconductor technology nodes continue to scale down to 3 nm, the self-heating effect in Gate-All-Around Nanosheet Field-Effect Transistors (GAA-NSFETs) has become a significant concern. This issue arises due to the complex interaction between device dimensions, material properties, and thermal management, which can lead to performance degradation and reliability challenges in advanced transistor designs. This paper aims to investigate the self-heating phenomenon in three-stacked nanosheet FETs and to develop a novel thermal resistance model that accurately captures the thermal behavior of these devices. The goal is to create a reliable framework for analyzing and mitigating self-heating effects in nanosheet-based transistors. We employed TCAD and SPICE simulations to analyze the self-heating effect in nanosheet FETs. A new multi-stage thermal resistance model (TRM), incorporating both thermal resistance (Rₜₕ) and thermal capacitance (Cₜₕ), was developed within the Berkeley Short-channel IGFET Model-Common MultiGate (BSIM-CMG) framework. Model accuracy was ensured by fitting the simulated ID-VG curves to experimental data, followed by parameter extraction and calibration based on self-heating evaluations. The proposed multi-stage Rₜₕ model demonstrated strong agreement with the simulation results, providing an accurate representation of the thermal behavior in three-stacked nanosheet FETs. This model offers a robust tool for analyzing self-heating effects in advanced nanosheet devices and can be used to guide the design and optimization of future low-power, high-performance transistors.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"155 ","pages":"Article 106499"},"PeriodicalIF":1.9,"publicationDate":"2024-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142721250","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A 7.3–14.2 GHz 6.3 mW LNA with 9.4±0.6 dB gain using transformer feedback and peak-gain distribution 7.3-14.2 GHz 6.3 mW LNA，增益9.4±0.6 dB，采用变压器反馈和峰值增益分布

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2024-11-22 DOI: 10.1016/j.mejo.2024.106497

Yuanrong Xie, Jincai Wen

引用次数: 0

A novel double-trench SiC SBD-embedded MOSFET with improved figure-of-merit and short-circuit ruggedness 一种新型的双沟槽SiC sbd嵌入式MOSFET，具有改进的性能因数和短路坚固性

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2024-11-22 DOI: 10.1016/j.mejo.2024.106495

Ziwei Hu , Jiafei Yao , Fan Yang , Yuxuan Dai , Kemeng Yang , Man Li , Jing Chen , Maolin Zhang , Jun Zhang , Yufeng Guo

{"title":"A novel double-trench SiC SBD-embedded MOSFET with improved figure-of-merit and short-circuit ruggedness","authors":"Ziwei Hu , Jiafei Yao , Fan Yang , Yuxuan Dai , Kemeng Yang , Man Li , Jing Chen , Maolin Zhang , Jun Zhang , Yufeng Guo","doi":"10.1016/j.mejo.2024.106495","DOIUrl":"10.1016/j.mejo.2024.106495","url":null,"abstract":"<div><div>A novel 1.2-kV double-trench SiC MOSFET with stepped Schottky barrier diode (SBD) (DTSS-MOS) has been proposed and studied. The proposed device employs a deep gate trench filled with high-K dielectric and a shallow source trench with stepped SBD to modulate the electric field distribution, causing a higher figure-of-merit (<em>FOM</em>). After optimizing the structural parameters, the <em>FOM</em> of the DTSS-MOS improves by 266 % and 47 % compared to the planar-gate MOSFET (PG-MOS) and the trench-gate MOSFET (TG-MOS), respectively. Meanwhile, due to its lower specific on-resistance (<em>R</em><sub>on,sp</sub>), the DTSS-MOS exhibits an outstanding high-frequency figure of merit (<em>HFFOM</em>). Furthermore, the shallow source trench incorporates the stepped SBD, allowing the P-well region and P+ shielding layer to effectively reduce the electron flowing path in the SBD region, thereby lowering the temperature and enhancing the short-circuit withstand time (<em>SCWT</em>). The <em>SCWT</em> of the DTSS-MOS is increased by 75 % and 133 % compared with PG-MOS and TG-MOS, respectively. Additionally, a feasible process flow for the DTSS-MOS is provided.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"155 ","pages":"Article 106495"},"PeriodicalIF":1.9,"publicationDate":"2024-11-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142747890","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Corrigendum to “A 9T-SRAM based computing-in-memory with redundant unit and digital operation for boolean logic and MAC” [145, March 2024, 106124 基于 9T-SRAM 的内存计算与冗余单元以及布尔逻辑和 MAC 的数字运算》[145，2024 年 3 月，106124] 更正

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2024-11-19 DOI: 10.1016/j.mejo.2024.106473

Xin Li , Mengya Gao , Zihua Ren , Kefeng Yu , Wenjuan Lu , Chenghu Dai , Wei Hu , Chunyu Peng , Xiulong Wu

引用次数: 0

An efficient power management circuit with MPPT for self-powered wireless sensors 用于自供电无线传感器的带 MPPT 的高效电源管理电路

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2024-11-19 DOI: 10.1016/j.mejo.2024.106487

Haozhen Li, Guangwen Yan, Zhengmin Zhang, Yu Pang, Lei Liu, Tingcong Ye, Ningning Wang

引用次数: 0

General neural network-based static performance prediction model construction techniques for gate-all-around and planar field effect transistor 基于通用神经网络的全栅极和平面场效应晶体管静态性能预测模型构建技术

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2024-11-17 DOI: 10.1016/j.mejo.2024.106485

Jing Chen , Jiahao Wu , Wei Du , Qing Yao , Kemeng Yang , Jun Zhang , Jiafei Yao , Yufeng Guo

{"title":"General neural network-based static performance prediction model construction techniques for gate-all-around and planar field effect transistor","authors":"Jing Chen , Jiahao Wu , Wei Du , Qing Yao , Kemeng Yang , Jun Zhang , Jiafei Yao , Yufeng Guo","doi":"10.1016/j.mejo.2024.106485","DOIUrl":"10.1016/j.mejo.2024.106485","url":null,"abstract":"<div><div>—This paper proposes general neural network-based static performance prediction model construction techniques for gate-all-around (GAA) and planar field effect transistor (FET). Firstly, a unique data preprocessing method named quasi-linear transformation is proposed to improve the prediction accuracy. By introducing transformation functions to process the input, the relationship between the input and output is simplified, thereby facilitating the model training. Secondly, an improved weighted loss function scheme that considers a more comprehensive evaluation criterion to enhance the training process is proposed. Compared with traditional artificial neural networks, the average prediction error of the output and transfer curves is reduced by 33 % and 25 % for GAA and planar FET, respectively. Meanwhile, the proposed model demonstrates strong extrapolation ability. Moreover, compared to traditional methods of obtaining static characteristic curves, this method is more efficient. Furthermore. the proposed neural network-based static performance prediction model is converted to Verilog-A model, demonstrating potential in circuit simulation.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"154 ","pages":"Article 106485"},"PeriodicalIF":1.9,"publicationDate":"2024-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142661940","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A high-precision GSG probe planarization method based on direct current signal 基于直流信号的高精度 GSG 探头平面化方法

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2024-11-15 DOI: 10.1016/j.mejo.2024.106478

Tianxiang Wu , Chen Lin , Ning Zuo , Qiwei Hu , Lijuan Yuan , Peiyuan Lu , Junhui Li

{"title":"A high-precision GSG probe planarization method based on direct current signal","authors":"Tianxiang Wu , Chen Lin , Ning Zuo , Qiwei Hu , Lijuan Yuan , Peiyuan Lu , Junhui Li","doi":"10.1016/j.mejo.2024.106478","DOIUrl":"10.1016/j.mejo.2024.106478","url":null,"abstract":"<div><div>Since the GSG (ground-signal-ground) probe has three pins, it needs planarization before the wafer test. To ensure the reliability of the RF wafer test, a new high-precision GSG probe planarization method is first proposed based on DC (Direct Current) analysis. The angle-force model of the GSG probe contact and separation process is derived, which is based on the analysis of the collected real-time force and electrical data using a designed force sensing system, and voltage measuring circuit. The results show that when the GSG probe is in contact with the substrate and away from the substrate, the relationship between the angle and force model is a primary function and a quadratic function respectively. The angle of the GSG probe can be obtained by substituting the force of the change points of voltage and resistance into the angle and force model. In addition, the smaller the difference between the minimum force at two-pin contact and three-pin contact of the GSG probe, the smaller the angle of the GSG probe. This method can provide a method and idea for the automatic planarization of GSG probes.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"155 ","pages":"Article 106478"},"PeriodicalIF":1.9,"publicationDate":"2024-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142721249","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Design and analysis of ultra-low power third-harmonic receiver with enhanced conversion gain and out-of-band rejection for IEEE 802.11ba 为 IEEE 802.11ba 设计和分析具有增强转换增益和带外抑制功能的超低功耗三次谐波接收器

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2024-11-15 DOI: 10.1016/j.mejo.2024.106315

Zongle Ma , Ran Hong , Meiru Liu , Rui Chen , Keping Wang

{"title":"Design and analysis of ultra-low power third-harmonic receiver with enhanced conversion gain and out-of-band rejection for IEEE 802.11ba","authors":"Zongle Ma , Ran Hong , Meiru Liu , Rui Chen , Keping Wang","doi":"10.1016/j.mejo.2024.106315","DOIUrl":"10.1016/j.mejo.2024.106315","url":null,"abstract":"<div><div>This paper presents an ultra-low power (ULP) receiver with enhanced conversion gain and high out-of-band rejection for Wi-Fi 802.11ba. The proposed third-harmonic mixer based on 6-phase non-overlap local oscillator (LO) not only minimizes power of the radio frequency (RF) front-end, but also improves out-of-band rejection. In addition, the 8-bit analog finite impulse response (AFIR) low-pass filter is designed in the baseband circuit, which can greatly improve the adjacent channel rejection (ACR) of the receiver with ultra-low power consumption. Meanwhile, the zero-power tunable tapped-capacitor resonator is proposed, which alleviate the resonance frequency offset impact by using switched capacitors for process corners compensation. This 802.11ba receiver is designed in a 65-nm CMOS process occupying an active area of 0.25 mm<sup>2</sup>. Post-layout simulation results show that, when operating at 2.4 GHz, the receiver achieves an ACR of 93 dB and a voltage gain of 51 dB. It consumes 197 μW DC power from 0.7 V supply voltage.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"154 ","pages":"Article 106315"},"PeriodicalIF":1.9,"publicationDate":"2024-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142700929","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A 1-V 3.9–5.2-GHz reference-sampling PLL with 168-fsrms integrated jitter and −76-dBc reference spur 1 V 3.9-5.2 GHz 基准采样 PLL，具有 168-fsrms 集成抖动和 -76-dBc 基准杂散

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2024-11-14 DOI: 10.1016/j.mejo.2024.106483

Feng Bu , Ruixue Ding , Depeng Sun , Yuan Gao , Ruiqing Wang , Xiaoteng Zhao , Rong Zhou , Shubin Liu

引用次数: 0