Pengke Mo , Nan Wang , Yan Fang , Dunjun Chen , Qianyu Hou , Wenhong Sun , Jin Wang
{"title":"Simulation-based study of low dark current phototransistors with p-hBN/AlGaN/GaN HEMT structures","authors":"Pengke Mo , Nan Wang , Yan Fang , Dunjun Chen , Qianyu Hou , Wenhong Sun , Jin Wang","doi":"10.1016/j.mejo.2025.106840","DOIUrl":"10.1016/j.mejo.2025.106840","url":null,"abstract":"<div><div>In this work, we report a high-performance ultraviolet (UV) phototransistor (PT) based on p-GaN/AlGaN/GaN high electron mobility transistor (HEMT) structure. Under dark conditions, the conducting channel of the p-hBN HEMT-based UV PT is depleted by the p-n junction, resulting in a low dark current density of 2.29 × 10<sup>−12</sup> mA/mm under 10 V drain bias, which demonstrates three orders of magnitude suppression relative to the PTs employing p-GaN HEMT architectures. This can be attributed to the stronger depletion effect caused by the higher activation hole concentration in the p-hBN layer. Moreover, the photocurrent density reaches 228.91 mA/mm under 0.5 mW/cm<sup>2</sup> UV illumination. The photo-to-dark current ratio is 1 × 10<sup>14</sup>. Additionally, the impact of structural parameters on the performance of p-hBN HEMT-based PTs is investigated. These results demonstrate that the p-hBN HEMT-based PTs have applicable potential in UV detection applications, suggesting an alternative strategy for developing improved UV photodetectors.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"165 ","pages":"Article 106840"},"PeriodicalIF":1.9,"publicationDate":"2025-08-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144858322","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A level shifting correlated multiple sampling circuit for low-noise CMOS image sensor","authors":"Ziwen Wang , Jing Gao","doi":"10.1016/j.mejo.2025.106843","DOIUrl":"10.1016/j.mejo.2025.106843","url":null,"abstract":"<div><div>This paper presents a low noise level shifting correlated multiple sampling (LSCMS) circuit, which consists of PGA based on correlated level shifting (CLS) and improved CMS. The CLS technique is employed in PGA, which divides the holding state of PGA into evaluation and shifting state by a level-shifting capacitor. The output signal is first stored by the shifting capacitor during the evaluation phase, and is removed from the amplifier's output during the shifting phase, which makes the equivalent input voltage approach the ideal virtual ground. Thus, the error from finite opamp gain is reduced and signal accuracy is improved. In improved CMS, the reset signal and exposure signal of pixel are differentially processed through capacitor flipping, which reduces the readout time and the number of capacitors by 12.5 %. Furthermore, the high accuracy buffer is employed in the CMS, which decreases noise and improves signal accuracy. The simulation results show that the LSCMS circuit achieves an input-referred random noise of 64.8μV<sub>rms</sub>.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"165 ","pages":"Article 106843"},"PeriodicalIF":1.9,"publicationDate":"2025-08-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144827583","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Kefan Qin , Xinyue Zheng , Jianwei Zhao , Shangzheng Yang , Wei Ma , Weibo Hu
{"title":"A command-driven SAR ADC with incremental and random converting technique","authors":"Kefan Qin , Xinyue Zheng , Jianwei Zhao , Shangzheng Yang , Wei Ma , Weibo Hu","doi":"10.1016/j.mejo.2025.106833","DOIUrl":"10.1016/j.mejo.2025.106833","url":null,"abstract":"<div><div>A command-driven 16-bit 500 kS/s successive approximation analog to digital converter (SAR ADC) is proposed to support accurate real-time data acquisition in this paper. The proposed ADC starts conversion upon receiving commands from the master, thereby enabling precise data acquisition and fault diagnosis. The ADC consists of three parts, the 1<sup>st</sup> sub-ADC, the residue amplifier (RA), and the 2<sup>nd</sup> sub-ADC. The 1<sup>st</sup> sub-ADC decomposes its capacitive digital-to-analog converter (CDAC) into incremental CDAC and binary CDAC. An incremental random converting technique is implemented in the 1<sup>st</sup>-CDAC to optimize the linearity and dynamic performance by solving the redundant switching. This technique calculates the effective number of capacitors that need to be flipped, and then uses pseudo-random sequence to flip randomly according to the result. The design is implemented with a 180-nm CMOS technology. Measurement results show that the ADC achieves SNR of 89.5 dB, SNDR of 88.4 dB, and THD of −99.1 dB at a sampling rate of 500 kS/s. The measured integral nonlinearity (INL) and differential nonlinearity (DNL) are −0.28/+0.49 LSB and −1.95/+1.8 LSB, respectively. The prototype consumes 6.2 mW and occupies 0.9 mm<sup>2</sup>.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"165 ","pages":"Article 106833"},"PeriodicalIF":1.9,"publicationDate":"2025-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144810531","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Si/SiGe superlattice-based double gate feedback field-effect transistor and its application in 1T-DRAM","authors":"Subir Das, Ashraf Maniyar, Pushp Raj, Jawar Singh, Pramod Kumar Tiwari","doi":"10.1016/j.mejo.2025.106822","DOIUrl":"10.1016/j.mejo.2025.106822","url":null,"abstract":"<div><div>This work presents the design and performance analysis of a Si/SiGe superlattice-based double gate feedback field-effect transistor (SL DGFBFET). The proposed SL DGFBFET is designed successively by stacking 3 nm thin Si and Si<span><math><msub><mrow></mrow><mrow><mn>1</mn><mo>−</mo><mi>x</mi></mrow></msub></math></span> <span><math><mrow><mi>G</mi><msub><mrow><mi>e</mi></mrow><mrow><mi>x</mi></mrow></msub></mrow></math></span> layers to achieve a higher ON current, extremely steeper switching characteristics, and a larger memory window than Si-based DGFBFET. The device offers 19 times higher ON current (2.24 × 10<sup>−3</sup> A/<span><math><mi>μ</mi></math></span>m), 10.36 times higher <span><math><mrow><msub><mrow><mi>I</mi></mrow><mrow><mi>O</mi><mi>N</mi></mrow></msub><mo>/</mo><msub><mrow><mi>I</mi></mrow><mrow><mi>O</mi><mi>F</mi><mi>F</mi></mrow></msub></mrow></math></span> ratio (<span><math><mo>∼</mo></math></span> 7.44 × 10<sup>9</sup>), a large memory window of 1.7 V, and an extremely lower subthreshold swing (<span><math><mo>∼</mo></math></span> 0.3 <span><math><mi>μ</mi></math></span>V/decade) than a Si-based FBFET of similar dimensions with a molar fraction x = 0.4, which can be very useful for memory and neuromorphic applications. The device’s OFF-to-ON switching is achieved at a lower gate voltage (threshold voltage = 0.34 V), making it suitable for low-power electronic devices. We have also shown the proposed device application in 1T DRAM which shows a remarkable performance in retention time (<span><math><mo>∼</mo></math></span> 1000 s) and energy consumption (2.37 fJ/bit). The Synopsys TCAD tool has been utilized in the study to design the device structure and analyze its electrical performance.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"165 ","pages":"Article 106822"},"PeriodicalIF":1.9,"publicationDate":"2025-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144827084","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Hu Liu, Pengyu Wang, Mingze Du, Yubin Li, Lei Pan, Yifan Lei, Chunyan Li, Yongrui, Zhang
{"title":"A high-performance vertical double-gate tunnel field-effect transistor (VDG-TFET)-based dual-band photosensor","authors":"Hu Liu, Pengyu Wang, Mingze Du, Yubin Li, Lei Pan, Yifan Lei, Chunyan Li, Yongrui, Zhang","doi":"10.1016/j.mejo.2025.106832","DOIUrl":"10.1016/j.mejo.2025.106832","url":null,"abstract":"<div><div>This study presents a high-performance dual-band photosensor based on a vertical double-gate tunnel field-effect transistor (VDG-TFET), enabling detection across 400–1100 nm. The device features a large light-absorption area, enhancing the generation of photocarriers and increasing the photocurrent. The incorporation of a vertical double-gate structure facilitates the modulation of the electric field distribution in the channel, improving the tunneling probability at the source-channel interface and resulting in higher sensitivity during signal transmission. Investigations demonstrates that the photosensor achieves a photoresponsivity of 106 mA/W at 400 nm wavelength, with an exceptional signal-to-noise ratio (SNR) reaching 175 dB and quantum efficiency of 33 %. In the near-infrared regime, the device exhibits a spectral sensitivity exceeding 300, while maintaining remarkable specific detectivity (<em>D</em>∗) values of 1.2 × 10<sup>12</sup> Jones at 700 nm and 5.7 × 10<sup>10</sup> Jones at 1000 nm. Furthermore, temperature-dependent analysis reveals suppressed thermal noise at lower temperatures, sustaining high SNR and <em>D</em>∗, while elevated temperatures degrade performance due to noise interference.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"165 ","pages":"Article 106832"},"PeriodicalIF":1.9,"publicationDate":"2025-08-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144779304","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Weizhong Chen , Zesheng Chen , Zhijie Deng , Yufan Xiao , Haishi Wang
{"title":"A double auxiliary gate SiC trench MOSFET with dynamic P-well control and integrated MOS-channel diode","authors":"Weizhong Chen , Zesheng Chen , Zhijie Deng , Yufan Xiao , Haishi Wang","doi":"10.1016/j.mejo.2025.106821","DOIUrl":"10.1016/j.mejo.2025.106821","url":null,"abstract":"<div><div>An asymmetric trench SiC MOSFET featuring Double Auxiliary Gate (DAG-ATMOS) is proposed to enhance both forward conduction and reverse recovery performance. The Auxiliary Gate (AG) is inserted beside the Auxiliary Source (AS) in the P-well, and a P-type barrier region (P-re) controlled by AG is formed between AG and AS. During the on-state, AG and AS jointly completely deplete the P-re under a gate-to-source voltage (V<sub>GS</sub>) of 15 V, disconnecting the P-well from the source and leaving it floating. This reduces the JFET region resistance (R<sub>JFET</sub>). At the reverse conduction, AS introduces a low-barrier MOS-channel diode with a lower reverse conduction threshold voltage (V<sub>cut-in</sub>) compared with the body diode, effectively eliminating the bipolar degradation by suppressing the conduction of parasitic body diode. Simulation results show that the DAG-ATMOS demonstrates a specific on-resistance (R<sub>on,sp</sub>) of 2.64 mΩ cm<sup>2</sup> and R<sub>JFET</sub> of 0.94 mΩ cm<sup>2</sup>, representing reductions of 7.2 % and 16.8 %, respectively, compared to conventional ATMOS. The V<sub>cut-in</sub> of the DAG-ATMOS is 2.0 V, 0.8 V lower than the conventional structure, while the reverse recovery charge (Q<sub>RR</sub>) is reduced by 79.2 %.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"165 ","pages":"Article 106821"},"PeriodicalIF":1.9,"publicationDate":"2025-08-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144826392","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Fengjuan Wang , Kai Li , Xiangkun Yin , Jiangfan Liu , Yiqun Liu , Yuan Yang
{"title":"Towards miniaturization: Reflectionless filter with sharp roll-off characterization based on through-silicon via","authors":"Fengjuan Wang , Kai Li , Xiangkun Yin , Jiangfan Liu , Yiqun Liu , Yuan Yang","doi":"10.1016/j.mejo.2025.106823","DOIUrl":"10.1016/j.mejo.2025.106823","url":null,"abstract":"<div><div>-This paper presents a through-silicon via (TSV)-based reflectionless filter with an optimized pseudo-elliptic frequency response. Specifically, the introduction of a resonant branch in the even-mode circuit enhances the roll-off sharpness, resulting in a rectangular coefficient of 1.065 at 20 dB attenuation level. Utilizing odd-even mode synthesis and tuning of the even-mode reflection coefficient, the filter achieves reflection suppression exceeding 19.6 dB across the entire DC-30 GHz bandwidth, thereby ensuring reflectionless performance in both the passband and stopband. Simultaneously, the out-of-band rejection exceeds 14.3 dB while maintaining a passband insertion loss of less than 1 dB, indicating effective signal suppression. Furthermore, through TSV integration, the filter achieves a highly compact footprint of 0.476 × 0.422 mm<sup>2</sup>.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"165 ","pages":"Article 106823"},"PeriodicalIF":1.9,"publicationDate":"2025-08-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144826393","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Temperature dependence of linearity parameters of GaN-based junctionless drain extended FinFET","authors":"N. Ashwini, K.S. Nikhil","doi":"10.1016/j.mejo.2025.106813","DOIUrl":"10.1016/j.mejo.2025.106813","url":null,"abstract":"<div><div>In this work, temperature dependent linearity parameters of Galliun Nitride (GaN, a wide gap material) based Junctionless Drain Extended FinFETs (JLDEFinFETs) for a temperature ranging from 100K to 450K are investigated using 3D thermodynamic TCAD simulation. An analysis of the transfer characteristics, off-current, transconductance, and its derivatives are carried out at various temperatures. Additionally, the impact of various linearity parameters, such as <span><math><mrow><mi>V</mi><mi>I</mi><msub><mrow><mi>P</mi></mrow><mrow><mn>2</mn></mrow></msub></mrow></math></span>, <span><math><mrow><mi>V</mi><mi>I</mi><msub><mrow><mi>P</mi></mrow><mrow><mn>3</mn></mrow></msub></mrow></math></span>, <span><math><mrow><mi>I</mi><mi>I</mi><msub><mrow><mi>P</mi></mrow><mrow><mn>3</mn></mrow></msub></mrow></math></span>, <span><math><mrow><mi>I</mi><mi>M</mi><msub><mrow><mi>D</mi></mrow><mrow><mn>3</mn></mrow></msub></mrow></math></span>, and the 1-dB compression point on temperature is studied in detail. The device under consideration has a metal gate contact which offers opportunities to tune its performance parameters like on-current, off-current and threshold voltage. A comparative analysis of the designed device with various devices is also carried out to validate the device design.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"165 ","pages":"Article 106813"},"PeriodicalIF":1.9,"publicationDate":"2025-07-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144749933","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Yu Fu , Guoliang Li , Guangbao Shan , Zeyu Chen , Hongrui Zhao , Yintang Yang
{"title":"An intelligent thermo-mechanical coupling collaborative design technique for 2.5D chiplet heterogeneous integration (CHI) system","authors":"Yu Fu , Guoliang Li , Guangbao Shan , Zeyu Chen , Hongrui Zhao , Yintang Yang","doi":"10.1016/j.mejo.2025.106801","DOIUrl":"10.1016/j.mejo.2025.106801","url":null,"abstract":"<div><div>An intelligent thermo-mechanical coupling collaborative design technique for 2.5D chiplet heterogeneous integration (CHI) systems is proposed. Using a four-chiplet 2.5D CHI system as an example, a thermo-mechanical coupling simulation model is established to reduce computational load through Latin hypercube sampling and data-driven modeling, significantly improving design efficiency. A GA-BPNN is developed to map design parameters to performance parameters, enabling fast and reliable performance prediction. An improved PSO-LDIW algorithm is employed for multi-physics collaborative optimization, with results verified via finite element analysis. The proposed method effectively reduces maximum temperature and stress, with optimization deviations below 1.006%, providing an efficient solution for optimizing thermal and mechanical performance in high-density chip systems and offering insights for multi-domain collaborative design.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"165 ","pages":"Article 106801"},"PeriodicalIF":1.9,"publicationDate":"2025-07-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144749931","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"An ultra-low-power three-stage amplifier using impedance multiplication compensation for nF-range capacitive loads","authors":"Mingqi Sun, Fanghui Yin, Xian Tang","doi":"10.1016/j.mejo.2025.106819","DOIUrl":"10.1016/j.mejo.2025.106819","url":null,"abstract":"<div><div>An impedance multiplication compensation (IMC) technology is presented to stabilize the three-stage amplifier driving nF-range capacitive loads. In the proposed compensation method, a serial multiplied RC impedance is located at output of the first stage to generate a low-frequency (LF) left-half-plane (LHP) zero, which reduces the value of the compensation capacitor and consumes only a small amount of quiescent current. It eliminates the bridge-connecting Miller capacitor between the outputs of the first and third stage, thereby preventing the generation of complex poles and improving the gain-bandwidth (GBW) product. The proposed IMC amplifier is implemented in a standard 180 nm CMOS technology with a core area of 0.0027 mm<sup>2</sup>. Post-layout simulation results demonstrate that, in the worst case, the circuit achieves a gain exceeding 100 dB and a gain-bandwidth product of 0.901 MHz with a capacitive load of 15 nF, while consuming only 13.06 μA of quiescent current.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"165 ","pages":"Article 106819"},"PeriodicalIF":1.9,"publicationDate":"2025-07-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144810532","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}