Microelectronics Journal最新文献_第9页

Compact bandpass filter with low insertion loss and high selectivity based on 3D glass-based IPD technology

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-02-01 DOI: 10.1016/j.mejo.2024.106539

Xueyuan Zhang, Yazi Cao, Xiaoyan Yang, Jialong Xin, Gaofeng Wang

{"title":"Compact bandpass filter with low insertion loss and high selectivity based on 3D glass-based IPD technology","authors":"Xueyuan Zhang, Yazi Cao, Xiaoyan Yang, Jialong Xin, Gaofeng Wang","doi":"10.1016/j.mejo.2024.106539","DOIUrl":"10.1016/j.mejo.2024.106539","url":null,"abstract":"<div><div>A compact bandpass filter with low insertion loss and high selectivity is presented using 3D glass-based IPD technology. A modified asymmetric π structure is introduced to generate three poles to achieve wide bandwidth and low insertion loss. In order to achieve better selectivity and higher out-of-band rejection, the introduced modified asymmetric π structure is adopted to generate two controllable transmission zeros on both sides of the passband. Compared to the traditional π structure, the modified π structure does not require the design to be completely symmetrical, thereby providing the filter design greater flexibility. High-Q 3D inductors based on 3D glass-based technology are utilized to achieve lower insertion loss. The proposed bandpass filter, which covers the band of 2.4–2.9 GHz, is fabricated with a compact size of 1.6 mm × 0.8 mm × 0.35 mm. The measured results show that it can achieve an insertion loss less than 1.6 dB and a return loss better than 15 dB in the passband. Its out-of-band rejection is better than 24 dB from DC to 1.89 GHz and from 3.7 GHz to 10 GHz. The simulated and measured results of the proposed BPF are in reasonably good agreement.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"156 ","pages":"Article 106539"},"PeriodicalIF":1.9,"publicationDate":"2025-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143163162","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Exploring the impact of sheet thickness scaling on Nanosheet FET gate electrostatics using k.p based simulations

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-02-01 DOI: 10.1016/j.mejo.2024.106480

Ramandeep Kaur, Nihar R. Mohapatra

引用次数: 0

Analytical modeling of cylindrical Silicon-on-Insulator Schottky Barrier MOSFET and impact of insulator pillar radius on analog/RF and linearity parameters for low power circuit application

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-02-01 DOI: 10.1016/j.mejo.2024.106505

Jitender Kumar , Amit Saxena , S.S. Deswal , Aparna N. Mahajan , R.S. Gupta

{"title":"Analytical modeling of cylindrical Silicon-on-Insulator Schottky Barrier MOSFET and impact of insulator pillar radius on analog/RF and linearity parameters for low power circuit application","authors":"Jitender Kumar , Amit Saxena , S.S. Deswal , Aparna N. Mahajan , R.S. Gupta","doi":"10.1016/j.mejo.2024.106505","DOIUrl":"10.1016/j.mejo.2024.106505","url":null,"abstract":"<div><div>In the current scenario of semiconductor technologies, the researchers are investigating the cylindrical Silicon-on-Insulator Schottky Barrier (SOISB) Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) due to its enhanced analog/RF parameters, high I<sub>ON</sub>/I<sub>OFF</sub> ratio and reduced ambipolarity. This study presents an analytical model for the cylindrical SOISB MOSFET, specifically focusing on how to calculate surface potential, threshold voltage, and drain current. Further, the research explores how altering the radius of the concentric SiO<sub>2</sub> insulator pillar impacts the MOSFETs performance in analog/RF circuit applications. The Silvaco 3D device simulator has been used for conducting the numerical simulations for a channel length of 22 nm and a silicon radius of 5 nm. The SiO<sub>2</sub> insulator pillar radius has been varied from 1 nm to 4 nm and its effect on the device characteristics has been investigated. The results show improved changes in analog/RF parameters and linearity, providing valuable insights for advanced semiconductor technologies.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"156 ","pages":"Article 106505"},"PeriodicalIF":1.9,"publicationDate":"2025-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143163290","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A small area-occupation three-stage OTA with transistor resistance and parasitic capacitance Q-factor modulation for miniaturized communication systems

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-02-01 DOI: 10.1016/j.mejo.2024.106501

Yangtao Hu, Siwan Dong, Xiaoliang Ji, Zengwei Qi, Cheng Shan

引用次数: 0

Design and implementation of a floating Pwell MTSCR for low-voltage ESD protection

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-02-01 DOI: 10.1016/j.mejo.2024.106512

Fengfeng Zhou , Hongjiao Yang , Yang Wang , Jun Deng , Haotian Chen

引用次数: 0

The application of the optimized genetic algorithm in SerDes circuit design

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-02-01 DOI: 10.1016/j.mejo.2024.106509

Xuan Wei

{"title":"The application of the optimized genetic algorithm in SerDes circuit design","authors":"Xuan Wei","doi":"10.1016/j.mejo.2024.106509","DOIUrl":"10.1016/j.mejo.2024.106509","url":null,"abstract":"<div><div>In modern high-speed communication systems, the main function of Serializer/Deserializer (SerDes) is to convert parallel data into high-speed serial data streams at the sending end to reduce the number and complexity of transmission lines. This study aims to solve the complex design problem of replacing inefficient, traditional parallel structures with high-speed serial interface SerDes. The Genetic Algorithm (GA) is optimized by adding a selection and substitution procedure, and the optimized GA is applied to the common-source amplifier. The low-frequency gain, bandwidth, and slew rate target circuit optimization design are completed. Additionally, the Clock and Data Recovery (CDR) circuit in SerDes is analyzed and designed. The CDR structure based on phase selector/phase interpolator type is used as the CDR circuit of the high-speed serial interface, enabling the final circuit function and performance to meet the requirements. Simulation experiments denote that the optimized GA can ensure that the evolved parameters allow the transistor to work in the saturation region to complete the common-drain amplifier's circuit optimization design. After 250 generations of evolution, the maximum gain of 0.75 is roughly achieved at an input voltage of 1.2V and a Metal Oxide Semiconductor (MOS) transistor width of 20 μm. The energy consumption per bit of data in the circuit based on the optimized GA is 16.8 pJ, 19.6 % lower than the 20.1 pJ of the conventional circuit before optimization. Therefore, the multi-objective circuit optimization design with a moderate gain is realized.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"156 ","pages":"Article 106509"},"PeriodicalIF":1.9,"publicationDate":"2025-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143163315","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A simple interface circuit for edge inference kernels based on SC-LNO memristor crossbar

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-02-01 DOI: 10.1016/j.mejo.2024.106537

Siqi Wang , Yinyu Liu , Xin Liu , Yuting Liu , Zihan Liu , Zhanqiang Xing

{"title":"A simple interface circuit for edge inference kernels based on SC-LNO memristor crossbar","authors":"Siqi Wang , Yinyu Liu , Xin Liu , Yuting Liu , Zihan Liu , Zhanqiang Xing","doi":"10.1016/j.mejo.2024.106537","DOIUrl":"10.1016/j.mejo.2024.106537","url":null,"abstract":"<div><div>Edge inference chips based on non-volatile memory hold promise in mitigating the bottleneck attributed to substantial data movement in artificial intelligence (AI) applications. Particularly, the efficient acceleration of numerous vector matrix multiply-accumulate (VMM) operations can be achieved through the collaboration of memristor crossbars and associated peripheral circuits. These efficient operations utilize the synaptic plasticity, high integration density, and inherent parallel execution capabilities of memristor crossbars. However, analog memristive devices often exhibit non-idealities such as readout nonlinearity, necessitating compatible peripheral interface circuits to ensure precision and stability in readout. In this work, a simple interface application-specified integrated circuit (ASIC) tailored to support non-ideal single-crystal <span><math><mrow><mi>L</mi><mi>i</mi><mi>N</mi><mi>b</mi><msub><mrow><mi>O</mi></mrow><mrow><mn>3</mn></mrow></msub></mrow></math></span> (SC-LNO) memristor crossbars is proposed, facilitating the efficient realization of VMM operations. The transmit (TX) and receive (RX) components of the interface circuit are respectively responsible for stimulating and reading the outputs of the memristor crossbar. A common-mode voltage strategy is employed to avoid the I–V nonlinearity and negative voltage sensitivity inherent in memristors. The trans-impedance readout front end within the RX module ensures signal stability in the presence of large input parasitic capacitance. As a proof of concept, a 180-nm prototype ASIC is tested in conjunction with a resistor array featuring parallel parasitic capacitance, demonstrating its linearly stable readout capability. The entire interface circuit consumes a mere 2 mW, with the ASIC’s active area measuring 0.086 mm<span><math><msup><mrow></mrow><mrow><mn>2</mn></mrow></msup></math></span>.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"156 ","pages":"Article 106537"},"PeriodicalIF":1.9,"publicationDate":"2025-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143163318","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

The sampling network for a 16-channel time-interleaved ADC

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-02-01 DOI: 10.1016/j.mejo.2025.106563

Pengfei Ji , Chengyuan Liu , Li Dang , Shaoxuan Li , Ruixue Ding , Shubin Liu , Zhangming Zhu

引用次数: 0

A low-jitter charge-pumped PLL for LiDAR detectors

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-02-01 DOI: 10.1016/j.mejo.2024.106507

Yuanhao Bi , Ming Li , Zheng Li , Siyu Li , Shuaikang Wang , Yue Xu

{"title":"A low-jitter charge-pumped PLL for LiDAR detectors","authors":"Yuanhao Bi , Ming Li , Zheng Li , Siyu Li , Shuaikang Wang , Yue Xu","doi":"10.1016/j.mejo.2024.106507","DOIUrl":"10.1016/j.mejo.2024.106507","url":null,"abstract":"<div><div>A low-jitter charge-pumped phase-locked loop (CPPLL) with four-stage differential delay units is implemented in 180 nm standard CMOS technology. Not only a current-steering technique is adopted to eliminate charge injection and clock feed-through effects, but also a frequency divider with a retiming structure is used to ensure the high accuracy of the system feedback loop. The voltage-controlled oscillator adopts a gated-ring structure to achieve a stable and controllable clock. The prototype of the CPPLL occupies 0.184 <span><math><mrow><msup><mrow><mspace></mspace><mtext>mm</mtext></mrow><mn>2</mn></msup></mrow></math></span>, and results reveal that when the reference clock is 50 MHz, the output frequency is locked at 800 MHz accurately. The phase noise is as low as −140 dBc/Hz @1 MHz, with a peak-to-peak jitter of 4.36 ps. Meanwhile, an ultra-low root-mean-square (RMS) jitter of 0.161 ps is obtained. At the output spectrum of 800 MHz, the reference spur is merely −72 dBc. These results highlight the CPPLL's outstanding performance in phase noise, jitter, and stability, making it well-suited for high-precision integrated LiDAR.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"156 ","pages":"Article 106507"},"PeriodicalIF":1.9,"publicationDate":"2025-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143162243","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A 14-bit 750 MS/s energy-efficient pipelined ADC for MEMS LiDAR system

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-02-01 DOI: 10.1016/j.mejo.2024.106528

Yizhe Hu , Lili Lang , Yemin Dong

引用次数: 0