Microelectronics Journal最新文献_第9页

A novel design method for wideband bandpass filters with fewer inductors 使用较少电感器的宽带带通滤波器新设计方法

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2024-07-17 DOI: 10.1016/j.mejo.2024.106300

{"title":"A novel design method for wideband bandpass filters with fewer inductors","authors":"","doi":"10.1016/j.mejo.2024.106300","DOIUrl":"10.1016/j.mejo.2024.106300","url":null,"abstract":"<div><p>Inductors that are widely used in wideband filter designs could result in large filter size and high insertion loss. A novel design method using admittance matrix based on direct circuit implementation is introduced for wideband bandpass filters. Firstly, a frequency transformation is performed on cross-couplings to realize the conversion between inductor and capacitor, thereby reducing usage of inductors. Moreover, by virtue of an enhanced resonator (type I), an approach of adding extra transmission zero is proposed to improve the out-of-band rejection without any additional usage of inductors. Thirdly, based on the frequency transformation, another enhanced resonator (type II) is introduced to further improve the frequency characteristics without compromising usage of inductors. Finally, by cascading the enhanced resonators of type I and type II, a novel filter can be constructed. This novel filter is designed and fabricated using a glass-based integrated passive device (IPD) technology. The measurement results are highly consistent with the simulation results. It is shown that the proposed design method can reduce the filter size and thus improve the chip integration. It enriches the freedoms during the filter design.</p></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-07-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141729193","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Novel III-V inverted T-channel TFET with dual-gate impact on line tunneling, with and without negative capacitance 新型 III-V 倒 T 沟道 TFET，具有双栅极对线路隧道的影响，有负电容和无负电容

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2024-07-16 DOI: 10.1016/j.mejo.2024.106309

{"title":"Novel III-V inverted T-channel TFET with dual-gate impact on line tunneling, with and without negative capacitance","authors":"","doi":"10.1016/j.mejo.2024.106309","DOIUrl":"10.1016/j.mejo.2024.106309","url":null,"abstract":"<div><p>We introduce two novel III-V inverted T-channel vertical line tunnel field-effect transistor (TFET) configurations, leveraging staggered bandgap compound materials. Design D-1 operate s without negative capacitance, while Design D-2 incorporates negative capacitance. Both designs employ area-enhanced gate normal line tunneling with dual-gate impact, utilizing InGaAs and GaAsSb materials to effectively reduce the overall bandgap. The double-area line tunneling, facilitated by the double gate, significantly enhances performance. D-1 exhibits notable improvements, with an I<sub>ON</sub> value reaching 596.55 μA/μm, an I<sub>ON</sub>/I<sub>OFF</sub> ratio of 2.5 × 108, a minimum subthreshold swing (SS) of 9.75 mV/dec, and an average subthreshold swing (AVSS) of 31.93 mV/dec. Building upon these achievements, D-2 takes a step further by implementing NC through a ferroelectric layer gate stack, significantly increasing the line tunneling rate symmetrically on the left and right channels beneath both gates. This marks the first proposal of double gate area-enhanced line tunneling with negative capacitance in this paper. D-2 demonstrates remarkable performance for future low-power applications.</p></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141729195","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

3D network-on-chip data acquisition system mapping based on reinforcement learning and improved attention mechanism 基于强化学习和改进注意力机制的 3D 片上网络数据采集系统制图

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2024-07-16 DOI: 10.1016/j.mejo.2024.106323

{"title":"3D network-on-chip data acquisition system mapping based on reinforcement learning and improved attention mechanism","authors":"","doi":"10.1016/j.mejo.2024.106323","DOIUrl":"10.1016/j.mejo.2024.106323","url":null,"abstract":"<div><p>The three-dimensional Network-on-Chip (NoC) data acquisition system is designed to create a time-interleaved data acquisition system using NoC technology. In the design of NoC application systems, optimizing the mapping algorithm can effectively reduce network communication latency. Aiming at the mapping challenge of a large number of functional IP nodes in 3D NoC data acquisition system, the reinforcement learning and improved attention mechanism mapping algorithm (RA-Map) is proposed. The RA-Map mapping algorithm employs node function encoding and node position encoding to express the properties of an IP node in the task graph preprocessing. The local attention mechanism is used in the mapping network encoder, and the fusion of dynamic key node information is proposed in the decoder. The mapping result evaluation network achieves unsupervised training of the mapping network. These targeted improvements improve the quality of the mapping. Experimental results show that the RA-Map mapping algorithm can effectively model the IP core mapping. Compared with the DPSO algorithm and SA algorithm, the average communication cost of RA-Map mapping algorithm is reduced by 6.5 % and 8.5 %, respectively.</p></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141736419","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

17-Cell battery monitoring analog front end with high sampling accuracy for battery pack applications 17 芯电池监测模拟前端，采样精度高，适用于电池组应用

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2024-07-16 DOI: 10.1016/j.mejo.2024.106327

引用次数: 0

Design and modelling of SiC MPS diodes with superior surge current robustness 具有卓越浪涌电流稳健性的 SiC MPS 二极管的设计与建模

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2024-07-16 DOI: 10.1016/j.mejo.2024.106298

引用次数: 0

Compact wide dual-band square dielectric resonator antenna to serve X-band/emerging 5G communication 服务于 X 波段/新兴 5G 通信的紧凑型宽双频方形介质谐振器天线

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2024-07-16 DOI: 10.1016/j.mejo.2024.106328

引用次数: 0

A fully integrated charge pump with double-loop control and differentiator-based transient enhancer for neural stimulation applications 用于神经刺激应用的具有双环控制和基于微分器的瞬态增强器的全集成电荷泵

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2024-07-16 DOI: 10.1016/j.mejo.2024.106313

{"title":"A fully integrated charge pump with double-loop control and differentiator-based transient enhancer for neural stimulation applications","authors":"","doi":"10.1016/j.mejo.2024.106313","DOIUrl":"10.1016/j.mejo.2024.106313","url":null,"abstract":"<div><p>This paper proposes a fully integrated charge pump (CP) with a double-loop control and a differentiator-based transient enhancer (DTE) for high-voltage neural stimulation applications. The double-loop control includes a clock-supply-voltage (<em>V</em><sub>CLK</sub>) modulation loop and a pulse-frequency modulation (PFM) loop. The <em>V</em><sub>CLK</sub> modulation loop regulates the output voltage by adjusting <em>V</em><sub>CLK</sub> while the PFM loop adjusts the operating frequency of the CP in accordance with the load current in order to improve power efficiency. The proposed CP combines the function of output voltage regulation and <em>V</em><sub>CLK</sub> generation into a single unit, leading to significantly reduced circuit complexity. The proposed double-loop control is capable of dealing with different dc current requirements while the proposed DTE suppresses the undershoots and overshoots of the output voltage during load transients. The proposed CP has been simulated using a 0.18-μm triple-well CMOS process and occupies an area of 0.537 mm<sup>2</sup>. The post-layout simulation results show that it can provide a regulated 9-V output voltage from a 3.6-V input voltage with a peak power efficiency of 73.4 % at 2-mA load condition. The Monte-Carlo simulation demonstrates that the overshoot and undershoot of the output voltage are kept below 3 % when undergoing a 2-mA load transient.</p></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141852529","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Driving scheme for residual image reduction in active-matrix organic light-emitting diodes display 减少有源矩阵有机发光二极管显示屏残留图像的驱动方案

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2024-07-16 DOI: 10.1016/j.mejo.2024.106324

{"title":"Driving scheme for residual image reduction in active-matrix organic light-emitting diodes display","authors":"","doi":"10.1016/j.mejo.2024.106324","DOIUrl":"10.1016/j.mejo.2024.106324","url":null,"abstract":"<div><p>Residual image is a frequent issue in active-matrix organic light-emitting diode (AMOLED) display, due to hysteresis effects of the internal devices. Up to now, some optimized methods have been researched mainly from process perspective. However, the approaches from driving scheme perspective and their electrical mechanism have rarely been demonstrated systematically. In this work, a technical proposal has been proposed to separate the influences of different devices including both thin film transistors (TFTs) and OLEDs furtherly. It was found that the current curve gap was nearly equal to the luminance curve gap and the main factor of residual image was shown to be the hysteresis of TFTs. An equivalent circuit of two thin film transistors and one capacitor (2T1C) was also adopted to substantiate the influences of threshold voltage (V<sub>th</sub>) compensation for reducing residual image, and a series of experiments of tuning capacitance were carried out for corresponding compensation improvements. Moreover, other driving scheme optimizations were also studied to reduce residual image furtherly, including increasing the data input time and resetting the driving TFTs. The research opens the possibility of considering reduction of residual image from driving scheme perspective and more systemic analysis from the internal electrical mechanism in AMOLED display.</p></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141729020","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Compact on-chip dual-band bandpass filter with wide out-of-band suppression based on hybrid coupling technique 基于混合耦合技术的带宽带外抑制紧凑型片上双频带通滤波器

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2024-07-16 DOI: 10.1016/j.mejo.2024.106304

引用次数: 0

A high-light-load-efficiency hysteresis-controlled buck converter with adaptively clocked hysteresis dynamic comparator for IoT applications 面向物联网应用的高轻载效率磁滞控制降压转换器与自适应时钟磁滞动态比较器

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2024-07-16 DOI: 10.1016/j.mejo.2024.106319

引用次数: 0