A PVT-insensitive 7T SRAM CIM macro for multibit multiplication with dynamic matching quantization circuits

Compute-in-memory (CIM) promises to solve the huge energy consumption and bandwidth limitation of multiply-and-accumulate (MAC) operation in von-Neumann architecture. However, there are still challenges for SRAM-based CIM: (i) traditional 6T SRAM has the problem of destroying internal node data when multiple rows are opened at the same time; (ii) the analog CIM faces nonlinearity and inconsistency issues; (iii) the separated ADC circuit and extra circuit take area overhead and large power consumption. In this paper, we propose 7T SRAMs (7TR and 7TL) with decoupled read and write paths. A 128 × 128 7T SRAM macro offers massively parallel with embedded SRAM array to realized analog voltage to digital output. The grouped calculation row and reference row help to reduce PVT influence, and reduce weight update frequency. The measured energy efficiency of 4bit × 4bit MAC is 36.24–71.82 TOPS/W using 0.7–0.9 V core supply.