一种具有快速瞬态响应和频率补偿能力的pn互补电流增强结构LDO

IF 1.9 3区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronics Journal Pub Date : 2025-04-23 DOI:10.1016/j.mejo.2025.106701

Sujuan Liu, Aoran Ge, Xudong Sun, Junchao Zhao, Kun Liu, Peiyuan Wan

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引用次数: 0

摘要

提出了一种新型的pn互补电流增强结构（PN-CCES），用于无电容低压差稳压器ldo。本设计采用PN互补级联结构和两个交流耦合网络来降低功率晶体管的栅极阻抗，从而增大栅极充放电电流。此外，PN互补级联结构与多级Miller补偿相结合，有效地将两个非优势极点与优势极点分离，减轻了共轭效应，保证了回路的稳定性。该电路采用0.18 μm BCD CMOS工艺实现，占据0.087 mm2的有源芯片面积。仿真结果表明，LDO的静态电流消耗约为37.5 μA，最大电流效率为99.963%。负载电容为100 pF，负载电流变化为100 mA/100 ns时，恢复时间为175 ns。

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A PN-complementary current-enhancement structure LDO with fast transient response and frequency compensation capability

This paper presents a novel PN-complementary current-enhancement structure (PN-CCES) designed for capacitor-less low-dropout regulators LDOs. The proposed design adopts a PN complementary cascode structure and two AC coupling networks to reduce the gate impedance of the power transistor, thereby increasing the gate charging and discharging current. Additionally, the combination of the PN complementary cascode structure and multistage Miller compensation effectively separates the two non-dominant poles away from the dominant poles, mitigating the conjugation effect and ensuring loop stability. The circuit has been implemented in a 0.18 μm BCD CMOS process, occupying an active chip area of 0.087 mm². Simulation results demonstrate that the LDO achieves a quiescent current consumption of approximately 37.5 μA and a maximum current efficiency of 99.963 %. Under a load capacitance of 100 pF and a load current variation of 100 mA/100 ns, the recovery time is 175 ns.

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来源期刊

Microelectronics Journal 工程技术-工程：电子与电气

CiteScore

4.00

自引率

27.30%

发文量

222

审稿时长

43 days

期刊介绍： Published since 1969, the Microelectronics Journal is an international forum for the dissemination of research and applications of microelectronic systems, circuits, and emerging technologies. Papers published in the Microelectronics Journal have undergone peer review to ensure originality, relevance, and timeliness. The journal thus provides a worldwide, regular, and comprehensive update on microelectronic circuits and systems. The Microelectronics Journal invites papers describing significant research and applications in all of the areas listed below. Comprehensive review/survey papers covering recent developments will also be considered. The Microelectronics Journal covers circuits and systems. This topic includes but is not limited to: Analog, digital, mixed, and RF circuits and related design methodologies; Logic, architectural, and system level synthesis; Testing, design for testability, built-in self-test; Area, power, and thermal analysis and design; Mixed-domain simulation and design; Embedded systems; Non-von Neumann computing and related technologies and circuits; Design and test of high complexity systems integration; SoC, NoC, SIP, and NIP design and test; 3-D integration design and analysis; Emerging device technologies and circuits, such as FinFETs, SETs, spintronics, SFQ, MTJ, etc. Application aspects such as signal and image processing including circuits for cryptography, sensors, and actuators including sensor networks, reliability and quality issues, and economic models are also welcome.